Research window: Past 24 hours (2026-09-02 08:18 ~ 2026-09-03 08:18, Beijing Time) Sources: HN, Google News aggregation, CNX Software, EE Times network, Business Wire, Guancha/Sina Finance/Lao Yao Ba, GitHub API (org repo and commit search), etc. (see appendix for details)

Index

  • I. Open Source Community and Software Ecosystem
    • XiangShan Kunminghu open-source core iterates at high cadence: XiangShan main repo sees 10+ commits in one day, intensive fixes for vector instruction exception handling (09-02)
    • The Chip Letter reader re-poll: confidence that “RISC-V will become mainstream in 20 years” drops 22 percentage points over three years (09-02)
    • ship-your-interpreter: Lean 4 + Sail RV64D model performs CompCert-style refinement proof on RISC-V binaries (09-03)
  • II. Product and Ecosystem Developments
    • Andes introduces agentic AI platform ChipAgents: custom processor design time cut by ~30%, verification cycle shortened to ~3 weeks (09-02)
  • III. Domestic Team Developments and Deep Dives
    • Lingrui Zhixin: P100 domestic server-class RISC-V core technical details disclosed, China’s first dynamic SMT4 implementation, test chip tape-out imminent (09-02)
    • Sophgo: LLM-TPU adds Microsoft Mage-VL streaming multimodal deployment, with precompiled bmodel (09-02)
    • Comprehensive GitHub check of domestic teams: T-Head submits hypervisor test suite, others mostly documentation and sync (09-02/03)
  • IV. Embodied Intelligence and Robotics Special Section
    • MIPS (by GF) launches Acies / Actus / Aegis three major Physical AI platforms, with RISC-V high-level ecosystem endorsement (09-02/03)
  • V. Summary and Trend Observations
  • Appendix: Complete Source List

I. Open Source Community and Software Ecosystem

1.1 XiangShan Kunminghu Open-Source Core Iterates at High Pace: 10+ Commits in One Day on the XiangShan Main Repo, Dense Fixes for Vector Instruction Exception Handling

Date: 2026-09-02 (continuous commits from 09-02 09:57 to 09-03 01:47 Beijing time)　Source: GitHub openxiangshan/XiangShan commits, openxiangshan organization repos

XiangShan (Kunminghu architecture), the open-source high-performance RISC-V processor core led by the Institute of Computing Technology, Chinese Academy of Sciences, maintained a high development pace during the window, with 10+ commits merged into the main repo in a single day, concentrated on correctness fixes for vector instructions and exception handling:

  • Instruction decode side: fixed sign extension of immediates for vector comparison instructions such as VMSGTU.VI (SelImmField/ImmIsUnsign5b), added vill operand checks to VSetFuncUnit, and made VsetDecoder correctly trigger illegal instruction exceptions when VS (vector state) is disabled—vector extension functionality and state machine semantics continue to tighten;
  • Execution unit side: fixed exception generation logic in AtomicsUnit for atomic operations, and preserved head TLB metadata during unaligned replay in LoadUnit;
  • Microarchitecture and verification infrastructure: added register-level register slicing timing paths in DecodeStage, dramsim3 sampling Verilator DPI at clock edges, and a new “student coverage learner” (feat(BOP)) experimental feature.

Companion repos were refreshed in sync: ready-to-run (bump NEMU reference, 16:44 UTC), NEMU, XSCache, workload-builder, and GEM5 all had pushes within the window, indicating that the “processor + simulator + image” development loop is active across the board. Vector and reliability polishing for subsequent Kunminghu releases is still underway, echoing the RVA23/RVV ecosystem software trend (yesterday’s NVIDIA CUDA requirement for RVA23 on RISC-V host CPUs).

1.2 The Chip Letter Reader Poll: Confidence That “RISC-V Will Become Mainstream in 20 Years” Falls 22 Points in Three Years

Date: 2026-09-02 (published the same day as the HN hot thread)　Source: The Chip Letter (Babbage), Hacker News

Semiconductor industry newsletter The Chip Letter ran the same reader poll in August 2023 and August 2026: “In 20 years (2043), will RISC-V become the standard or most popular instruction set?” The results contrast sharply: in 2023, most readers said yes; in 2026, that share fell below half, down about 22 percentage points. Author Babbage offers two explanations: first, massive AI investment has siphoned off resources and attention that might otherwise have gone to RISC-V, leaving RISC-V in a supporting role in many accelerators; second, RISC-V’s progress depends heavily on the strength of its rivals—over the past three years Intel has staged a strong comeback, and Arm’s in-house server SoCs and high-performance cores from NVIDIA and others have also advanced, and the combination has eroded RISC-V’s “mindshare.” Commenters are divided: some readers argue RISC-V has no constant area/performance advantage and that its best case is spreading through the enthusiast market; others cite Espressif ESP32-C3/C6 as evidence of its value in cost-sensitive markets as “cheap and good enough.” While the survey reflects community opinion rather than factual data, the potential impact of “AI-era narrative and mindshare” on RISC-V’s high-end trajectory is worth continued tracking.

1.3 ship-your-interpreter: Lean 4 + Sail RV64D Model Provides CompCert-Style Refinement Proof for RISC-V Binaries

Date: 2026-09-02/03 (new repo, updated within the window)　Source: GitHub BasisResearch/ship-your-interpreter

The new open-source project ship-your-interpreter represents a new approach to formal verification: “don’t verify the interpreter source, verify the interpreter binary directly.” The project compiles a WHILE-language interpreter into a bare-metal RV64 ELF (with I/O via HTIF), then uses a Lean 4-embedded Sail-generated RISC-V RV64D instruction set model to prove, in CompCert-style forward simulation, that “the inductive big-step semantics abstract the machine behavior”: the core theorem guarantees that all derivable behaviors can halt on the machine (with exit code 0), and non-derivable programs never halt cleanly. The repo states that all builds have zero sorry, zero axioms (only the classical choice lemma), with unfinished obligations honestly recorded as Prop-typed definitions rather than hidden behind sorry; it ships with a fuzzer/SMT/census verification stack and per-function simulation lemmas (about 500 decode table modules). This provides a rare end-to-end reference implementation in the Lean ecosystem for “binary-level RISC-V software correctness,” complementing RISC-V formalization toolchains (ACT, Sail). The repo is still new (low star count) and is an early-stage project worth watching.

II. Product and Ecosystem Developments

2.1 Andes Technology Adopts Agentic AI Platform ChipAgents: Custom Processor Design Time Cut by About 30%, Verification Cycle Compressed to About 3 Weeks

Date: 2026-09-02 (Andes official website news)　Source: Andes Technology official website, Dealroom repost

Andes Technology (TWSE 6533), a founding premier member of the RISC-V International Foundation and one of the world’s leading RISC-V CPU IP suppliers, announced that it has adopted the agentic AI platform ChipAgents in its custom processor design flow, with notable results: custom processor design time cut by about 30%, and a verification workflow that previously took months compressed to about three weeks. This marks another leading CPU IP vendor writing “AI agent-assisted chip design/verification” into its official flow, consistent with the AI-for-chip-design trend previously pursued by several EDA/design services companies; for Andes, whose business model relies heavily on customizing AndesCore for customers (instruction extensions, SoC integration), verification automation translates directly into delivery-cycle competitiveness. ChipAgents is a third-party agentic AI platform (an agent platform for chip design). Currently available public information is mainly vendor statements; methodological details await further disclosure.

III. Domestic Team Updates and Deep Dives

3.1 Lingrui Zhixin: P100 Domestic Server-Class RISC-V Core Technical Details Disclosed, First Dynamic SMT4 Deployment in China, Test Chip Nearing Tape-Out

Date: 2026-09-02 (Guancha.cn in-depth interview)　Sources: Guancha.cn, Sina Finance reprint, Laoyaoba/JiWei, China Daily 2026-07 funding report

Domestic chip startup Lingrui Zhixin, less than two years old, disclosed for the first time through a Guancha.cn interview its fully self-developed server-class RISC-V CPU core P100 (v1 released in early 2026, test chip nearing tape-out). The key selling point is dynamic SMT4 targeting agent workloads: up to 4 threads per core, with real-time dynamic switching between SMT1 and SMT4 based on workload without system restart — the company claims this is China’s first maturely deployed dynamic SMT technology (described in the article as “the only benchmark product on the domestic SMT technology roadmap,” which is the company’s own characterization). Other specifications: 20+ stage out-of-order superscalar pipeline, 8-decode 10-issue, TAGE branch prediction, single-core performance claimed to exceed 20/GHz (SPEC CPU2006); enhanced enterprise-grade RAS for long-chain unattended agent scenarios (end-to-end error detection, hardware-level error isolation, automatic core recovery via automatic re-execution of faulting instructions); custom extension interfaces reserved based on the open RISC-V instruction set, supporting customers in integrating dedicated acceleration units within the pipeline.

Company narrative background: reassessment of CPU value in agent execution (control-flow workloads such as task decomposition, tool invocation, sandbox lifecycle management; citing Intel/Georgia Tech research showing CPU-side runtime accounts for 50%–90.6%), with server CPU/GPU ratios shifting from approximately 1:4 toward 1:1; Morgan Stanley predicts the agent-driven CPU incremental market will reach $32.5–60 billion by 2031. Market strategy: long-term focus on CPU product sales, short-term selective IP licensing (targeting DPU, autonomous driving, embodied intelligence brains, AI accelerator chips; not licensing to general-purpose CPU competitors); deep alignment with domestic process nodes; domestic GPU vendors including Biren Technology participated in its several-hundred-million-yuan Pre-A round (officially announced 2026-07), with the two parties jointly optimizing “CPU+GPU” scheduling and building domestic agent compute all-in-one machines. Roadmap: a 128-core server-class CPU based on P100 is expected to tape out in 2027 and enter mass production in 2028; domain-enhanced processors for embodied intelligence and edge inference are being advanced in parallel. Note: Lingrui Zhixin has not previously been covered in this daily series; this issue marks the team’s first appearance. Most technical metrics are company self-reported and should be treated with caution pending mass-production validation, but its “agent-native CPU + SMT” positioning provides a new sample for the domestic RISC-V server narrative.

3.2 SOPHGO: LLM-TPU Adds Microsoft Mage-VL Streaming Multimodal Deployment with Pre-Compiled bmodel

Date: 2026-09-02　Sources: GitHub sophgo/LLM-TPU, Mage-VL project page (Microsoft), arXiv:2607.24904

SOPHGO’s open-source model deployment stack LLM-TPU (targeting BM1684X/BM1688/CV186X series TPUs) merged Mage-VL deployment support within the window: the commit shows a new Mage-VL streaming inference demo with a pre-compiled bmodel download link (README updated 07:38 UTC). Mage-VL is Microsoft’s “codec-native” streaming multimodal foundation model open-sourced in July 2026 (arXiv:2607.24904), focused on low-latency multimodal inference for real-time video/event streams. This means SOPHGO’s TPU-side VLM coverage extends from static image-text to streaming video understanding scenarios, with pre-compiled models lowering the deployment barrier for users. Combined with SOPHGO’s recent CV84X6 specification rollout and sophon-tools maintenance (reported yesterday), its AI software stack remains in a high-frequency iteration phase.

3.3 Comprehensive GitHub Audit of Domestic Teams: T-Head Submits Hypervisor Test Suite, Rest Mostly Documentation and Syncs

Date: 2026-09-02/03　Sources: XUANTIE-RV/damo-rv-priv-ats, Nuclei-Software, spacemit-com, sipeed, eswincomputing and other organization repos APIs

Window audit of ten domestic RISC-V team GitHub organizations (pushed_at ≥ 09-02 08:18 Beijing time):

  • T-Head (XUANTIE-RV, 72 repos): The only substantive commit was in damo-rv-priv-ats (created 2026-06, C language, low public star count) — “Added more Hyprevisor test suites (#26)” (09-02 09:45 CST). This repo appears to be a public-facing project for DAMO Academy/T-Head’s RISC-V privileged architecture (hypervisor/address translation) test suites, an internal tool spillover with limited information value;
  • XiangShan (openxiangshan): See 1.1, most active within the window;
  • Nuclei (Nuclei-Software, 42 repos): Only one push to lauterbach-startup (Lauterbach debugger startup configuration), routine maintenance;
  • SpacemiT (spacemit-com): Updates to three documentation repos — docs-bianbu / docs-chip / docs-ros (Bianbu system, chip manuals, ROS documentation) — plus edk2-platforms sync, continuing the documentation completion cadence (K3 UEFI/P3 manuals reported yesterday);
  • SOPHGO (sophgo): See 3.2; Sipeed (sipeed): maix_ax620e_sdk_kernel kernel SDK update; StarFive (starfive-tech): u-boot repo push (likely non-default branch/upstream sync); RevyOS: linux fork kernel sync; ESWIN Computing (eswincomputing): no pushes.

Conclusion: Apart from XiangShan and SOPHGO, domestic teams showed no architecture-level or product-level new developments within the window, continuing the routine quiet period following major version releases.

IV. Embodied Intelligence and Robotics Special Section

4.1 MIPS (by GF) Launches Acies / Actus / Aegis Physical AI Platforms, Backed by High-Level RISC-V Ecosystem Endorsements

Date: 2026-09-02 (US Pacific, Beijing time early 09-03)　Sources: Business Wire press release, Yahoo Finance reprint

MIPS under GlobalFoundries (now fully pivoted to the RISC-V architecture; just promoted to RISC-V International’s top-tier membership and appointed to its board as vice chair in August, reported in this series on 08-29) has launched three “workload-native” developer platforms for Physical AI, pushing AI capabilities down into industrial machines, vehicles, and embedded systems:

  • MIPS Acies: Inference-Native — an AI inference developer platform for modern edge workloads, featuring an open, standards-based NPU and an open software stack;
  • MIPS Actus: Event-Native — a real-time developer platform for event-driven embedded applications such as motion control, sensor fusion, and predictive maintenance;
  • MIPS Aegis: Safety-Native — for mission-critical Physical AI systems requiring low latency and agentic processing.

MIPS CEO Sameer Wasson said computing platforms must adapt to workloads, and MIPS provides a unified foundation with an “open, software-first” platform, positioning “efficiency and tokens-per-watt” as its technical cornerstone; the platforms leverage RISC-V’s open characteristics plus GF’s process/packaging/manufacturing capabilities to deliver an integrated path from AI and processor IP, workload modeling, to custom silicon (software-to-silicon). Notable endorsements: AMD Embedded Silicon Marketing Director Manuel Uhm and MediaTek Co-COO/CFO David Ku both sent welcoming statements on the RISC-V ecosystem and MIPS’s commitment — corroborating yesterday’s report on NVIDIA’s CUDA-on-RISC-V host CPU requirements list and the MediaTek-NVIDIA NVLink Fusion collaboration (08-31): Physical AI/embodied intelligence is becoming the most important narrative and battleground for RISC-V’s high-end push. Specific customer deployments and timelines for the platforms have not yet been disclosed.

No other new embodied intelligence hardware products on the RISC-V side in this window; MIPS’s platform launch and the domestic “agent CPU” narrative (see 3.1) jointly point to: RISC-V is entering robotics/embodied intelligence as “purpose-built compute for the physical world and agents,” not merely on general-purpose core cost-performance.

V. Summary and Trend Observations

  1. Two main threads advancing in parallel: Physical AI platformization (West) and agent CPU (China). MIPS’s three platforms (Acies/Actus/Aegis) package “inference + real-time + safety” into a RISC-V Physical AI development foundation; domestically, Lingrui Zhixin enters with a “dynamic SMT4 agent-native CPU” narrative. Combined with yesterday’s NVIDIA disclosure of hard requirements for porting CUDA to RISC-V host CPUs (RVA23/ACPI/coherency), the commercial narrative for high-end RISC-V is rapidly taking shape around AI data centers and embodied intelligence.
  2. Watch for signals of “mindshare” decline. The Chip Letter’s two reader polls over three years show confidence in RISC-V going mainstream within twenty years dropping 22 percentage points, which the author attributes to AI investment diversion and x86/Arm counteroffensives — opinion surveys don’t represent facts, but they remind the ecosystem that beyond technical progress, it also needs to compete for narrative.
  3. Open-source core iteration continues: 10+ commits in the XiangShan Kunminghu window focused on vector instruction exception correctness and reliability; formal verification (ship-your-interpreter’s binary-level refinement proof) and AI-assisted design (Andes × ChipAgents) are becoming new levers for software and design efficiency.
  4. Domestic teams are generally in a post-launch quiet period; next milestones worth flagging: Lingrui Zhixin P100 test chip tape-out, StarFive Tianshu-100 customer chip progress, future XiangShan versions, and Sophgo CV84X mass-production support.

Appendix: Complete Source List

Source Verification Result
gnews “RISC-V” when:1d (9 items) Qualcomm Dragonwing (reported 09-01, excluded), MIPS Physical AI (included in 4.1), Qwen LLM/GPU coil noise (excluded), GCC17 ACE (x86 feature, excluded), Andes×ChipAgents related (included in 2.1)
gnews SiFive when:3d Only market reports and NVIDIA-MediaTek (08-31 old news, reported yesterday), no new items in window
gnews “RISC-V Summit” when:7d / Milk-V / SpacemiT / SOPHGO when:7d No valid hits (Summit Europe 2026 is actually old news from Bologna in June, not an event in this window)
gnews Andes when:3d No valid hits (known noise from Chile’s Andes energy storage with the same name)
gnews T-Head/XiangShan/Sophgo/Nuclei/Ventana when:7d Mostly noise (XiangShan = Beijing Xiangshan Forum, Sophgo = smart computing centers/gambling), valid hits: Observer Network Lingrui Zhixin interview (included in 3.1), EE Times China RISC-V overview (repost of old news from June Summit Europe, excluded)
HN Only 2 items: The Chip Letter poll results (included in 1.2), SERV teaching core repost (old project, excluded)
GitHub org scan (10 orgs) XiangShan 11 repos, Espressif 31 repos (mostly upstream sync/toolchain forks, no dedicated new activity) active in window; T-Head/Nuclei/Sophgo/Ventana/Sipeed/StarFive/RevyOS 1 each; ESWIN 0 (see 3.3 for details)
GitHub new repos ship-your-interpreter (included in 1.3); BasisResearch new project, low star count, noted as early-stage project for observation