Reporting period: Monday, September 21, 2026 to Friday, September 25, 2026 — 5 working days, source material from 5 daily issues Sources: Daily RISC-V Global News Briefing (five issues: 09-21, 09-22, 09-23, 09-24, 09-25; the 09-21 issue covers a three-day window including developments from the prior weekend); additionally reinforced by a 168-hour window review of GitHub organizations and key repositories, dual-source verification of openRuyi, and website inspections of member companies Editorial note: This period covers four thematic dimensions: instruction set and architecture ecosystem, operating systems and distributions, chips and hardware, and open-source community and industry activities. Core items from the five daily issues are aggregated by theme; facts, version numbers, and dates all come from verified sources for the respective period plus hands-on verification during this period. Vendor, park, and media one-sided claims are noted in the body text.

1. This Week’s Highlights

  • ESWIN Computing passes HKEX listing hearing, poised to become the HK stock market’s “first RISC-V stock” (09-21): According to HKEX filings, Beijing ESWIN Computing Technology Co., Ltd. passed the main board listing hearing on 09-21 (joint sponsors CITIC Securities and CITIC Securities International), and if the offering proceeds smoothly it will fill the gap in listed vehicles in the RISC-V chip sector. The company uses RISC-V as its technology foundation, with products covering human-machine interaction and multimedia processing chips, interconnect and compute chips, focused on smart terminals and embodied intelligence; revenue for 2023 to 2025 was RMB 1.752/2.025/2.431 billion, with a net loss of RMB 1.516 billion in 2025, and Q1 2026 revenue of RMB 494 million (up 18.4% YoY); compute product revenue grew from RMB 375,000 in 2023 to RMB 320 million in 2025. According to Frost & Sullivan, China’s RISC-V main control chip market grew from RMB 1.1 billion in 2021 to RMB 37.7 billion in 2025, and is expected to expand to RMB 219.4 billion by 2030. On the same day, the company created a new release-EIC7X-2026.06 release branch on GitHub and landed the eic7700_sample repository (see Section 4). Boundary: the hearing still leaves process to go before formal issuance and pricing, and narrowing net losses and the pace of compute product ramp-up are the most direct test indicators. Source: Yicai, Sina Finance / Guandian

  • EVAS Intelligence completes nearly RMB 2 billion financing, the largest single disclosed round in China’s RISC-V space (09-18 news, included in this cycle’s briefing): RISC-V cloud AI compute chip company EVAS Intelligence completed a new round of nearly RMB 2 billion (about USD 295 million), with a post-money valuation approaching RMB 15 billion, and more than 20 investors (including Xinyi Leasing, a sub-fund of the National Big Fund Phase I, Huatai Innovation, Zhongding Capital, and SMIC Capital). On the product side: the first-generation Epoch chip has entered scaled mass production and delivery, with native support for block-wise quantized FP8; the industry’s first RISC-V AI compute supernode (64 nodes, E200-L liquid-cooled OAM modules) has completed cluster deployment at an operator data center in Shijiazhuang; the new-generation cloud chip has been taped out, with an iteration cadence of “one generation per year”; the company is advancing open-sourcing of the VISA virtual instruction set, with a software stack compatible with PyTorch, TensorFlow, JAX, and ONNX, and collaboration with the vLLM, Triton, and FlagOS communities. Boundary: a valuation approaching RMB 15 billion does not equal performance delivery, and subsequent order and revenue cadence are the harder test. Source: Lieyunwang via Tencent News, 36Kr English

  • Monte Cimone v3: Sophgo SG2044 gains third-party HPC energy-efficiency benchmark (09-23): The RISC-V International official blog published an evaluation of the third-generation RISC-V HPC testbed (MCv3) jointly completed by the University of Bologna, Italy’s Cineca supercomputing center, and E4 Computer Engineering: a cluster built on Sophgo Sophon SG2044, measuring power consumption alongside HPL and STREAM benchmarks, benchmarked against Intel Xeon Platinum 8480+ (Sapphire Rapids) and NVIDIA Grace CPU Superchip. Data: SG2044 single-core performance is more than double that of the previous generation SG2042; energy efficiency reaches 3.08 GFLOPs/W (about 10x that of the first-generation testbed), with peak energy-efficiency point performance at 46% of Sapphire Rapids and 91% of Grace CPU Superchip. Significance and boundary: this is the first time a third-party academic team has placed a domestic RISC-V server chip into the same benchmarking framework as international server platforms to provide an energy-efficiency comparison; total performance still lags, and the realistic entry point remains energy-efficiency-sensitive and open, customizable scenarios. Source: RISC-V International blog

  • UPC research: using DAMO XuanTie C910 and on-chip performance counters to let RISC-V chips “self-detect” microarchitectural attacks, with 99% detection accuracy (09-24): A team from the Universitat Politècnica de Catalunya (UPC) in Spain completed experiments on real commercial silicon — DAMO XuanTie C910 (RV64GCV) mounted on a Sipeed LicheePi 4A, running Debian 13 — using hardware performance counters combined with machine learning for real-time detection of microarchitectural attacks; the paper was published in the journal Cybersecurity, and the dataset HARPY-V was released (about 64,000 labeled samples, 16 types of microarchitectural attacks including GhostWrite, and 16 benign programs); binary detection accuracy is 99%, and multi-class classification about 95%. The team also disclosed empirical findings: on the C910, monitoring multiple perf counters simultaneously causes mutual interference (some readings inflated by more than 3x), so counters must be collected individually, and perf event descriptions are often inaccurate, requiring reliance on the official manual’s counter mappings. Significance and boundary: one of the first studies completed using commercial RISC-V silicon plus a publicly reproducible dataset; it covers only a single core model, requires retraining across chips, and generalization to entirely new attack types remains to be verified. Source: Scienmag, paper

  • Yunqi Conference: DAMO XuanTie team unveils Zhenwu V900 AI chip, discloses Yitian 720/730/750 CPU roadmap for the first time (09-22): Zhenwu V900 adopts a self-developed parallel computing architecture, 216GB memory, 1,200GB/s inter-die interconnect bandwidth, and single-chip performance three times that of the previous generation Zhenwu M890, with native support for FP8/FP4; it will enter mass production in Q1 2027 and be deployed at scale in Alibaba Cloud data centers, paired with Panjiu supernodes and a self-developed ICN Switch (connecting up to 500,000 chips per cluster); Yitian 720 (192 cores, 96 PCIe lanes) and Yitian 730 (first based on a fully self-developed microarchitecture, supporting SMT, with single-core SPECint2017/GHz up to 1.4x that of Yitian 710) are scheduled for Q3 2027, and Yitian 750 will use a second-generation self-developed core with native ICN interconnect support. Boundary and background: neither Zhenwu nor Yitian is a RISC-V product (Yitian continues to use the Arm instruction set), and they are included under the “domestic core teams” criterion; DAMO XuanTie is a core team in the RISC-V ecosystem, and its RISC-V line (XuanTie C-series IP, the Wujian Alliance, and joint open-source XiangShan R&D) had new developments during the same week (see Sections 2 and 3). Source: ITHome, MyDrivers, TrendForce

  • Automotive RISC-V enters the “mass-production list”: Dongfeng DF30 set for scaled mass production in 2026, Infineon’s next-generation automotive MCUs shift fully to RISC-V (09-21 ~ 09-23): Dongfeng disclosed that the DF30 (jointly developed with China Information and Communication Technologies Group, domestic 40nm automotive-grade process, functional safety up to ASIL-D, Nuclei core) has completed validation in models including Dongfeng Yipai 007, M-Hero M817, and Aeolus Haohan, first deployed in engine ECUs, with plans for scaled mass production in 2026 and the first batch of production vehicles rolling off the line by year-end; the Nuclei core team has expanded to about 500 people, and the chip has completed more than 600 tests. Infineon announced that its next-generation automotive MCUs will shift fully to RISC-V (incorporated into the AURIX family), with its automotive MCU share rising to 36%, and it is working with Vector, Neusoft Reach, and Puhua to adapt AUTOSAR and advance FreeRTOS/Zephyr/NuttX. The final installment of Gasgoo’s series adds the “cost accounting” and cadence judgment: commercial RISC-V core licensing fees are about one-tenth of Arm’s, but commercial IP, tools, and verification environments all require payment, and ecosystem investment is the main barrier (Infineon invested 2 to 3 years ahead); automotive penetration is expected to rise from about 10% in 2025-2026 to about 31% by 2031, following an “edge-to-center” path. Source: Ifeng (Wangtongshe), Ifeng (Wangtongshe), Gasgoo

  • XiangShan processor: vector floating-point instructions merged into the default branch, cache subsystem “Oceanus” L2 advances in parallel (09-22 ~ 09-24): On 09-22 the main repository merged “vector floating-point instruction support” (adding a floating-point vector operation path to the Kunminghu vector unit) and added Zicbop instructions to decode’s uopTable; on 09-23 the XSCache “Oceanus” next-generation L2 development branch advanced 20 commits (L2 port parameterization, AMBA CHI port exposure, StashShared/StashUnique transaction support, and multiple coherence issue fixes); on 09-23 the main repository fixed a pingpong deadlock on loads/stores crossing 16-byte alignment (#6590), and on 09-24 the default branch merged uBTB hit-check timing and CommonHR redirect history maintenance fixes; on 09-25 multiple branches advanced in parallel with fixes and tuning for vectors, TAGE branch prediction, free list refactoring, and load-to-use timing. The simulation and verification chain (NEMU/GEM5/difftest) followed in step (see Section 2 for details). Source: XiangShan commit log, XSCache commit log

  • Aowei Lingxin completes over RMB 200 million Pre-A+ round (09-23): Shenzhen Aowei Lingxin announced the full closing of its Pre-A+ round, with the amount exceeding RMB 200 million, bringing in state-backed institutions such as Suzhou Venture Capital, Guoxin Guozheng, Puhua SME Phase II, and Chengdu Peikun, as well as industrial capital including SigmaStar, Juhe Capital, and Shenzhen Industrial Investment, with existing shareholders participating; the Pre-A series totals more than RMB 300 million, with funds directed toward next-generation chip R&D, team expansion, and commercialization. Its technical path is a “RISC-V foundation + DSA modular configurable heterogeneous architecture,” and its self-developed RV9000 series (up to 24 heterogeneous compute cores, with a built-in national cryptographic security engine) was taped out and lit up on 09-15 (reported in the previous briefing). Boundary: the financing amount and use are per the company’s official announcement, and the chip still lacks third-party performance data and a mass-production timeline. Source: PEdaily

II. Instruction Set and Architecture Ecosystem

XiangShan Processor: Vector Floating-Point Merged into Default Branch, Cache and Frontend Progressing in Parallel

  • Vector floating-point enters main branch: On 09-22, the main repository merged feat(vector): support vector-float instructions, adding a floating-point vector computation path for the Kunminghu vector unit and cleaning up vecRegion connections; on the decode side, the missing Zicbop instructions were added to uopTable (#6586). The vector development branch (0923) continued to fix six items—vector store mask support for the new store path, vector load VL dependency tracking, vle exception handling, vldSNMergeInfo initial value correction, merging old vd on writeback, and cancellation of vstd uops outside the physical store queue—representing final polish of the vector memory access path.
  • Default branch merges and cache subsystem: On 09-23, the main repository fixed a pingpong deadlock on loads/stores crossing 16-byte alignment (#6590); on 09-24, the default branch merged uBTB hit check timing (#6489) and a CommonHR redirect history maintenance fix. The XSCache “Oceanus” L2 branch advanced 20 commits on 09-23: L2 port parameterization (compatible with multiple D-Cache bank combinations), exposing ports externally via the AMBA CHI interface, CHI semantic StashShared/StashUnique transaction support, and coherence fixes including EVT commit, peer metadata writes, and ReplRd returning to I state—the memory system is evolving toward multi-core and coherent interconnect.
  • Frontend and microarchitecture tuning track: The TAGE branch predictor fixed bank conflicts and CommonHR maintenance errors; the free list refactor branch uses bitmap enqueue counting to rotate and refill banks (performance); the ECC RERI feature branch was committed; the load-to-use timing branch fixed specMiss timing; on 09-22 the main repository switched the docker base image to xs-env:stable (#6577), added nightly fuzz to CI, and improved ckpt_select.py (#6604). Overall, the rhythm is dual-track: “vector memory access wrap-up + frontend prediction and cache microarchitecture tuning.” Source: XiangShan, XSCache

Simulation and Verification Chain: Matrix Extension, Prefetching, and Multi-Core Convergence in NEMU, GEM5, and difftest

  • NEMU: Made mseccfg a Kconfig-configurable option (#1221), disabled the virtualization supervisor timer only when nemu_timer is enabled (09-21); changed NutShell unimplemented CSRs to be omitted (#1222), kept CY/TM/IR writable when Zicntr is absent (#1223) (09-22); released v2026.09.r17 (09-23); completed CUTE AMU callbacks and optimized the share-ctrl controller (09-24). Earlier in the window (09-18 to 09-20), there was another batch of AME matrix extension work: detection of reads from undefined tile register regions (#1224), limiting matrix load comparison range to active regions (#1217), SHARE REF marking CSR dirty bits (#1220), and memmove-accelerated GCC register export (#1219).
  • GEM5 (XiangShan branch): PDB (prefetch data buffer) model and replay cleanup, prefetch admission fixes; mem-cache fixed probeHit boundaries and then enabled hit-under-block (#1164); cpu-o3 fixed pflush vset (#1135); SMT added a per-IQ safety watermark policy (#1175); FP division latency aligned across formats (#1167); KMHV3 vector computation issue queue aligned (#1179); L2 low-precision offload made configurable (#1183), H2P page table enabled by default; weekly performance coverage refreshed (#1188) and branches such as Hybrid ROB and MaskRAT modeling advanced.
  • difftest: AME packed events adapted to the NEMU ABI (#962), iotrace preserves the last zstd chunk at EOF (#972), OpenIOMMU file manifest changed to conditional append (#974), and AME MinimalMatrixConfig validator compatibility fixed.
  • Merge observations: matrix extension (AME) boundary semantics, prefetch mechanisms, and multi-core compute alignment are the three main lines of the simulation chain this week; XiangShan’s verification infrastructure continues to do two things: “simulate more accurately, run faster.” Source: NEMU, GEM5, difftest

Compilers, Toolchains, and Ecosystem Libraries: Binary Translation, Vector Backends, and Open-Source IP Tooling

  • felix86 (running x86/x86-64 programs on RISC-V Linux): Five commits on 09-23—updating RIP after x87 operations, fixing a signal race before futex locking, a VK_AMD_buffer_marker graphics thunk, and MSVC string lookup optimization; four commits on 09-24—optimizing the MOV+SHUFPS combination to PSHUFD, fixing a REPL regression, semaphore lock/unlock around fork, and Zydis decode optimization, with game and workload compatibility continuing to be polished.
  • Emulators and specification tools: RVVM merged five floating-point fixes (fcvt dynamic rounding mode, fcsr reserved bits and frm clarification, NaN and sqrt result normalization, involving #259, #260, #280); qtrvsim fixed window sizing and modal event loop issues in the WebAssembly build, and switched packaging for older SUSE distributions to GCC-13; riscv-unified-db (machine-readable specification library) added WFI timeout and U-Mode support parameters (#2526).
  • Vector backends and library ecosystem: simdjson gained an experimental RVV (RVV 1.0) length-agnostic (VLA) backend, with accompanying GCC/Clang validation, runtime dispatch, and reproducible benchmarks (a personal experimental repository; upstream acceptance progress remains to be verified); the Sipeed SLogic toolchain migrated drivers from a private implementation to the shared libslogic library and released slogic16u3-tools v0.1.3 (more detailed flashing verification logs).
  • Open-source IP and build layer: The Bluespec open-source hardware IP library Tape-Out (FukuzSoC) opened a batch of new repositories—three reference SoCs (MCU/Linux/SMP) and components such as PLIC, with each IP including ip.yaml (with measured area), regmap.yaml, and full-configuration-matrix behavioral tests, paired with the self-developed xirang package manager and maturity displayed via a five-level badge system; Tiny-Vedas released the arxiv-v0 snapshot (RV32IM core + 8x8 int8 GEMM accelerator + complete PyTorch JIT to RV32 ELF pipeline, entering the paper version); GNOME Flatpak riscv64 unofficial builds continue to be updated; the Exercism programming platform opened a RISC-V track; the AG32 (RISC-V MCU + FPGA hybrid chip) open-source SDK toolchain AGaMEMnon remains active. Source: felix86, RVVM, Tape-Out, Tiny-Vedas, simdjson RVV

III. Operating Systems and Distributions

openRuyi: Dual-Track Kernel Upgrades and Batch Security Landings, September Release Still in Release Window

  • Dual-Source Verification: No new announcements on the official news page this week; the latest remains the 2026.08 release (published 08-27), and the 2026-09 release page continues to be absent. Given the distribution’s monthly cadence (releases in late each month), the September release has entered its release window and must be tracked closely in the next issue (key items to verify after release: toolchain and kernel versions, RVA23 integration, cloud-native and AI software stack updates).
  • Dual-Track Kernel Upgrades (09-21): linux upgraded to 7.2.6 and linux-lts to 6.18.52 (both with patchset and config refreshes); kernel-team-tools updated in sync with four kernel build tags — 6.18.52-1, 7.0.14-5, 7.1.13-1, 7.2.6-1 — with kernel configs enabling options such as ULTRARISC, VFIO_IOMMU_TYPE1, and ARCH_ANLOGIC; all four maintenance branches (ruyi/6.18.y through 7.2.y) pushed in sync; a new unified openruyi-linux-build component added, with three specs switched to unified maintenance via rpm macros.
  • Build and Security Batch (09-21 ~ 09-24): glibc 2.44 caught up to the upstream snapshot; batch security updates for python-pytorch-lightning 2.6.6, python-datasets 5.0.1, python-ujson 6.0.0, ImageMagick 7.1.2.31, and pcre2 10.48; expat bumped to 2.8.5 (09-24 security fix batch); on the cloud-native side, new Go packages including konnectivity-client and kms, dd-trace-go, and VictoriaMetrics; KDE desktop installation components had dependencies supplemented.
  • Quality and Standards: kvm-unit-tests added a new BRS (Boot and Runtime Services) SBI requirement test and decoupled SBI console initialization from UART (09-23) — adding a test hook for verifying a “BRS-compliant boot chain” for the distribution; clang-wrap regularized linker options and static library member selection, while llvmir-converter preserves protected target features and caches versioned templates; a new SPDX license header check hook (new precommit-hooks repo) and python-pyzmq package naming conventions added; the Ceph port CI (ceph-ci) installs build artifact rpms into a clean image via dnf for verification, and applies a GCC 16 compatibility patch to rocksdb (first day of the window).
  • Summary: openRuyi this week focused mainly on “security updates + packaging standards + server software,” making final preparations for the September release; the server and cloud-native software package stack continues to thicken. Sources: openRuyi news page, openRuyi repository, kvm-unit-tests BRS test

Distribution and Platform Side: revyos, openKylin, and Other Developments

  • revyos: Within the window, revyos/linux and the runner repository show push records (routine CI and maintenance branch updates, with no version-level changes); boot chain and kernel configuration work for the SG2044/K3 platforms continues at the previous cycle’s pace.
  • openKylin: Presented its progress in hardware adaptation, AI capability integration, cloud-native support, and embodied intelligence scenarios at the RISC-V Open Computing Power Forum at the IC WORLD conference (reported 09-21). Sources: revyos/linux, OSChina

Firmware and Mass-Production Toolchain: XuanTie Zero-Stage Boot Ships Stable Release, Sophgo ZSBL and K3 UEFI Continue Iterating

  • DAMO XuanTie: zero_stage_boot released the XuanTie_V1.4.0 stable version (09-18, following three pre-release rounds from rc1 to rc3). The complete prebuilt set includes zsb firmware, OpenSBI 0.9/1.7, and Linux 5.10/6.6, covering three ABI combinations — 32ilp32, 64ilp32, and 64lp64 — aimed at boot chain integration for downstream SoC vendors and board partners; the privileged-mode test repository damo-rv-priv-ats continues its “test alignment with spec” work — test plans are linked to spec clauses (PR #32), and the hypervisor test suite was changed to run via PLATFORM or SUITE configuration (09-22).
  • Sophgo ZSBL: v3.2.0 (09-18) incorporates device model improvements such as naming platform devices by device tree path and no longer instantiating driverless devices; the psewriter tool in the sophon-tools flashing utility shipped four consecutive versions from 2.1.0 to 2.1.3 and added f2fs support and BOOT/recovery partition type protection — moving from “can flash” to “field delivery reliability.”
  • SpacemiT UEFI: edk2-spacemit pushed 20 commits in a batch (09-22), spanning three consecutive versions 0.0.7 through 0.0.9 — converting edk2 and edk2-platforms from submodules to in-repo inline source and syncing with upstream, refining Debian packaging (loading kernel modules on demand, fixing K3 platform detection, using the deb version number as the platform version), with firmware moving toward Debian-based distribution.
  • Sophgo bootloader-riscv adjusted its build convention to use RV_EDKII_SRC_DIR as the edk2 top-level source directory (09-24), making it easier to specify an external edk2 source tree. Sources: zero_stage_boot XuanTie_V1.4.0, damo-rv-priv-ats, sophgo/zsbl, edk2-spacemit

IV. Chips and Hardware

Domestic Chips and Capital Moves: ESWIN, Lanxin, Ruixin

  • ESWIN Computing (ESWIN): On the same day as the hearing, a new release-EIC7X-2026.06 release branch was created on GitHub (the linux-stable branch includes a batch of fixes for the ESWIN ISP media subsystem—frame rate recovery, ISP restart, imx415 and dvp2axi corrections—plus RISC-V DTS additions; the u-boot branch includes HDMI display and emmc partition fixes), and a new eic7700_sample repository was opened—the establishment of a release branch for EIC7X (the EIC7700 series edge computing SoC) typically signals version freeze and customer-facing release preparation, with capital moves and engineering delivery proceeding in parallel in the same week.
  • Lanxin Computing LX500 (reported 09-20, 2026 Semiconductor Ecosystem Development Conference): In February this year, the company brought up its first RISC-V-based “intelligence-connectivity integrated” all-in-one CPU, the Lanxin LX500, and launched an AI-native agent all-in-one machine; it has completed adaptation for Qwen 3.5 35B (BF16) and the Kimi K2.6 trillion-parameter model, with the Kimi K3 128K ultra-long-context version in progress; customers cover leading telecom operators, central and state-owned enterprise groups, cloud service providers, financial institutions, universities, and the industrial sector, with volume orders beginning delivery in 2026. At the same event, Chaorui Technology gave its judgment on the RISC-V international standard timeline: “The most optimistic estimate is approval by the end of 2027; objectively, it may take 2 to 3 years or even longer,” emphasizing that this is an irreversible major trend.
  • Suzhou Ruixin (Digital Trade Fair 09-23): The Gaoguang D35 dataflow chip was exhibited as a “fully self-developed physical AI chip” at the 5th Global Digital Trade Expo (MyDrivers said it can “support five major AI scenarios”); media reported it under the headline framing “12nm performance exceeds Nvidia’s 7nm” (this is media/vendor promotional framing, with no third-party benchmark); Jiwei.com analyzed the architectural reasons behind its becoming a computing power partner for Qiyuan Robotics (triggering computation on data arrival, reducing data movement overhead), continuing the previous issue’s “D35 mass production and entry into the Qiyuan ecosystem” from the exhibition. Sources: eswincomputing/u-boot, East Money, Jiwei.com

Sophgo: Dual Lines in Edge AI and Server CPUs, Software Support Rapidly Filling Out

  • New board OrangePi O1 (09-24): Based on the BM1688 (8-core Arm Cortex-A53 plus RISC-V C906 coprocessor; TPU provides INT8 16 TOPS / INT4 32 TOPS), with onboard M.2 NVMe, SATA 3.0, dual Gigabit Ethernet ports, Wi-Fi 6E/Bluetooth 5.3, HDMI 2.0 4K60, dual MIPI-CSI and 6-channel video input, supporting 16-channel 1080p30 decoding, positioned for edge-side large-model and vision inference.
  • Large model and vision adaptation: LLM-TPU added multi-image input and ViT output caching for the Qwen3.5 demo (09-23), and added CV84X6 bmodels for Qwen3-Embedding and Qwen3-TTS (09-21); sophon-demo fixed the Qwen3.5 prefix cache issue, adapted Qwen3.5 35B-A3B (MoE architecture) to CV84X6, and added CV186X dual-core support for YOLOv8_plus_seg (09-21 to 09-22).
  • Toolchain: sophon-tools released v1.6.0 with multiple batches of fixes over the week—VPSS per-component utilization capture, CV84X2 network interface name determination, f2fs guard in the packaging chain, performance history export optimization, and VPP_USAGE coverage extended to all 13 VPSS components.
  • Combined with Monte Cimone v3 (see Top Stories), Sophgo’s ecosystem moves are simultaneously visible across both product lines: “cloud-side TPU inference” and “RISC-V server CPUs.” Sources: LinuxGizmos, LLM-TPU, sophon-demo

SpacemiT: K3 Platform Software Stack and Inference Backend Modularization

  • llama.cpp branch v0.2.0 (09-24): Introduces an independent ggml-spacemit backend (build flag -DGGML_SPACEMIT=ON)—a single main thread submits tasks to the spine runtime, which then spawns worker threads; compute cores are specified via a list of physical core IDs, and llama-cli, llama-bench, and llama-server all schedule uniformly in this way; the server side continues its multi-channel ASR capability and can work with the media backend to process audio requests concurrently. This branch has continued to evolve since the MTMD refactor in v0.1.7, and this release lands “backend independence,” marking a signature version in its inference stack’s march toward modularization.
  • spine-runtime v0.6.3 (09-23): A new version of the AI multi-core execution runtime for RISC-V SoCs (responsible for task scheduling and synchronization between general-purpose cores and AI compute cores).
  • Vision and multimedia: model-zoo-vision iterated continuously over the week—RVV-accelerated image preprocessing fusion (CPU pack fusion, face and clip model migration, tracking and RVV OCR, shared u8c3 helper functions), tightened detection post-processing, added benchmark scenarios and inference timing, post-processing speedups, and superpoint descriptor precomputation; mpp completed vdec channel lifecycle simplification, concurrent throughput testing, and alignment verification fixes; ai-gateway added a Qwen3-Embedding embedding model preset; model_zoo_rl added inference thread configuration and model warmup.
  • Branch synchronization and documentation: On the evening of 09-18, nearly 30 repositories in the K3 product line were batch-synchronized across branches (buildroot, U-Boot, OpenSBI, Linux 6.18, Mesa, MPP, and testing tools, etc.; spot-checking linux-6.18 shows it is the k3-br-v1.0.y product branch)—providing downstream integrators with a unified baseline; docs-chip and docs-product adopted terminology linting and knowledge synchronization workflows. Sources: llama.cpp v0.2.0, spine-runtime v0.6.3, model-zoo-vision

Dev Boards and Edge Hardware: ESP32-S31, BeagleV-Fire, and Sipeed Toolchain

  • Espressif ESP32-S31 Linux porting heats up (09-24): Dual-core 32-bit RISC-V main core (up to 320MHz, plus a 40MHz low-power core) and the first ESP32 with a built-in Sv32 MMU, featuring a Gigabit Ethernet MAC, USB 2.0 High-Speed OTG, dual-slot SDIO, DVP camera input, and a parallel LCD controller—the peripheral combination is already approaching that of a modern single-board computer; in August the official Linux BSP developer preview was released (Buildroot 2025.02 plus U-Boot plus a Linux 6.18 branch, with a full image of about 13.7MB), and the community completed ports including Linux 6.12 supervisor mode and Linux 7.1 plus OpenSBI 1.9 (capable of driving an 800x480 LCD console). XDA’s assessment: the S31’s peripherals, bandwidth, and privilege model are all approaching SBC territory, but Linux support remains experimental. In the same week, 14 items were merged in the esp-idf window, and esp-vision added camera runtime IPA and ISP control.
  • BeagleV-Fire enters the Yocto mainline layer (09-22): meta-riscv added the BeagleV-Fire (Microchip PolarFire SoC) board BSP and the hss-payload-generator-native recipe; BeagleV-Ahead gained SD card boot support; gptfdisk was upgraded and milkv-duo-fsbl adjusted; usage limitation documentation was added later (09-23).
  • Sipeed SLogic software stack: Drivers migrated from a private implementation to the shared libslogic, macOS CI unified the builds of ngscope and sigrok-bridge, and the SLogic32U3 four-channel maximum rate was adjusted from 1600 to 1400 MHz (specification correction); scopehal-apps followed with upgrades; NanoKVM fixed storage mount semantics (image mounted read-only, /data handed to a single writer). Sources: XDA, CNX Software, meta-riscv, SLogic

Embodied Intelligence and Robotics: SpacemiT Robotics Stack Continues to Strengthen and “Brain-Cerebellum Fusion” Plans

  • Linglong humanoid (humanoid_linglong): Hip joint configuration fix and retention of legacy policy damping (09-21); corrected dynamics mimic policy and station-keeping policy gain fixes (09-22); integrated the SONIC motion tracking policy (PR #16)—registering the SONIC model and eight optional reference motions, configuring 28-DOF motion mapping and observation inputs; humanoid_common simultaneously added support for SONIC motion selection and RL protection (per-joint target bounds, inference timeout diagnostics) (09-24).
  • Perception, navigation, and peripherals: ros2_humanoid added RGB-D SLAM and Nav2 navigation support (09-23), taking its humanoid ROS 2 stack from motion control toward a “perception-localization-navigation” loop; perception fixed planar stitching rendering (locked to 1080p); peripherals-motor added an RS485 shared-library driver for the M8010-A motor; peripherals-rc_receiver was added to the component manifest (event-driven callback lifecycle alignment); linksee cleaned up unused occupancy grid nodes.
  • Simulation and policy infrastructure: humanoid_common landed the SONIC runtime interface; simulation_mujoco fixed the decoupling of PC rendering from physics simulation (#9), working with the “PC simulation plus K3 board RL inference” sim2sim workflow to facilitate single-machine debugging before moving to real hardware.
  • Chip planning: At the 2026 Global AI Chip Summit (Shanghai, reported 09-21), SpacemiT disclosed its “isomorphic fusion computing” roadmap—using a unified architecture, unified memory, and a unified software system to allocate CPU compute, AI compute, and real-time compute on demand; the K3 is eight-core at 2.4GHz with 60T of AI compute and supports deployment of 30B models, and a “brain-cerebellum fusion chip” will be developed next. Sources: humanoid_linglong SONIC, ros2_humanoid, Xin Dongxi

International Developments: Openchip, Nordic, and India’s Aheesa

  • Openchip BER10 (included 09-17): An interview disclosed details of Europe’s sovereign RISC-V high-performance application processor—the team was assembled from scratch in early 2024, has more than 350 employees, and completed tapeout in under two years with first-pass success and no respin; the chip is 64-bit, can run Linux, and integrates a vector unit, coherent fabric, and an independent management tile; it is backed by EUR 111 million in support from the EU IPCEI microelectronics program. Its positioning emphasizes “delivering systems” rather than just chips, and it is in discussions with multiple European parties about a sovereign system stack based on seL4.
  • Nordic nRF54LC10A (included 09-17): A multiprotocol SoC with a 128MHz Cortex-M33 main core plus a 128MHz RISC-V coprocessor (for software-defined peripherals and time-critical task offload), supporting Bluetooth LE, Thread, Zigbee, and Matter, offered in CSP29/CSP39 and QFN48 packages, with mass production expected in Q2 2027—another instance of RISC-V entering the mainstream IoT product lines of a major international vendor as an internal control core.
  • India’s Aheesa VIHAAN-I (09-21): The Chennai-based fabless company showcased a domestically developed RISC-V broadband network SoC (28nm, targeting GPON/EPON and telecom infrastructure); tapeout has been completed, MPW manufacturing is planned, and the commercial target is Q1 2027; the project has been recognized under India’s MeitY Design Linked Incentive (DLI) scheme. Caveats: the product is not yet in mass production, and process and performance details are vendor and exhibition framing. Sources: RISC-V International, LinuxGizmos, EE Times

V. Open-Source Community and Industry Events

Domestic Industry Events: Open-Source Innovation Competitions, Industry-Education Integration, and Expo Updates

  • Beijing Open-Source Innovation Competition (reported 09-21): The 4th OpenAtom Competition · 2026 Open-Source Industry Solutions Innovation Competition has established a dedicated “Open-Source Intelligent Hardware Solutions” track, soliciting integrated hardware-software solutions for intelligent terminals, embedded systems, IoT devices, and embodied intelligence hardware. Requirements include open-sourcing control programs and publicly releasing 3D model drawings of structural components; registration and materials are due by October 31, with the finals held November 13–14 in Beijing Yizhuang (30 teams, RMB 1 million prize pool). Outstanding works will be exhibited at GOTC 2026 Global Open-Source Technology Summit (November 14).
  • Industry-Education Integration: Approximately 50 students from the School of Mathematical Sciences at Zhejiang University of Technology visited SpacemiT’s Hangzhou R&D frontline on the first day of the semester, where the company delivered the first class of the new term (09-18) — universities organizing students to take their “first class” at domestic chip companies at the start of the semester reflects the normalization of Yangtze River Delta chip companies participating in local talent development.
  • At the 5th Global Digital Trade Expo (opened 09-23, Hangzhou), developments including the display of Raycore Gaoguang D35 are covered in Section IV. Sources: OSChina, Tidenews

International Events and Expos: SEMICON India Concludes and AI Infra Summit Recap

  • SEMICON India 2026 Concludes (09-19 ~ 09-20): Among 15 new announcements, RISC-V occupied a prominent position — the Digital India RISC-V (DIR-V) Grand Challenge results were unveiled, with 1,236 teams and over 5,000 participants; three teams shared a prize pool of 600,000 rupees (SASTRA University’s water surface cleaning robot based on the SHAKTI processor, a digital stethoscope running on the C-DAC VEGA processor, and IISc’s forest monitoring system), all based on India’s indigenous RISC-V processors; C-DAC released the PARAM Vidya and PARAM Shavak-QS platforms and signed cooperation agreements with NLC India and Bharat Electronics. A joint report by EY and ISEA projects India’s semiconductor market growing from approximately USD 64 billion in 2026 to USD 200 billion by 2035.
  • AI Infra Summit Recap (reported 09-22, expo 09-15 ~ 09-17, Santa Clara): Epic Semi showcased a “full RISC-V from top to bottom” server solution at a formal booth (both the host CPU and AI processors based on RISC-V cores); Tenstorrent, Axelera (AI card dataflow control), Xcena MX1 (over a thousand RISC-V cores for data movement and caching) — RISC-V’s role in the “control plane/orchestration layer” of AI infrastructure has a presence far exceeding its booth share. Sources: thepublicworld, More Than Moore

VI. Trend Watch

  • RISC-V has moved from community narrative to capital-market pricing, with the test shifting to delivery and revenue: Within a single week, ESWIN Computing passed its HKEX hearing, Epoch Intelligence closed nearly RMB 2 billion in funding (the largest single domestic round), and Aowei Lingxin completed over RMB 200 million in Pre-A+; combined with Nuclei’s Beijing Stock Exchange tutoring filing and being named in the 15th Five-Year Plan (previous cycle), the capital pricing window for RISC-V has opened. Industrial moves in the same week (EIC7X release branch, EIC7700 example repository, RV9000 tape-out) corroborate each other. The key variables ahead are product delivery and order fulfillment.
  • Third-party quantitative benchmarks are landing densely, with “comparable and reproducible” becoming the keyword of the new phase: Monte Cimone v3 places a domestic server chip (SG2044) into the same HPC benchmark framework as Intel and NVIDIA (peak efficiency points at 46% of Sapphire Rapids / 91% of Grace CPU Superchip), while UPC achieves 99% detection accuracy using commercial silicon plus public datasets — the external narrative has upgraded from “it can run” to “there is comparable data,” and the research side is beginning to consolidate reusable methodologies (datasets, testbeds, tutorials).
  • The automotive side has moved from “discussion” to a “mass-production checklist”: DF30 is scheduled for volume production in 2026, and Infineon (36% automotive MCU share) has announced a full transition to RISC-V for its next generation. A series of analyses brings the discussion down to delivery and cost accounting (commercial core licensing fees are roughly one-tenth of Arm’s, with ecosystem investment as the main barrier), with penetration coordinates from 10% to 31% (by 2031), and 2026 to 2028 as the critical three years for E/E architecture transition.
  • Open-source cores and distributions advance on dual tracks, with pace mismatch as the norm: XiangShan maintains a high development density with “vector memory access wrap-up plus front-end and cache microarchitecture tuning,” while XSCache evolves toward CHI coherent interconnect; openRuyi focuses on security updates and packaging specifications, with the 2026.09 release entering its release window but not yet shipped — the pace mismatch between open-source hardware and open-source software (month-level vs. quarter-level) continues to be the main variable in ecosystem expectation management.
  • The form-factor boundary of edge RISC-V continues to expand: ESP32-S31 brings an MCU vendor close to SBC form (Sv32 MMU, Gigabit Ethernet, Linux BSP preview), Sophgo’s new BM1688 board covers edge vision and storage interfaces, and SpacemiT modularizes the inference backend (ggml-spacemit) — the edge is moving from “it can run” to “it runs well” in the engineering phase; RVV vector acceleration continues to sink from flagship projects into routine optimization targets for general-purpose libraries (simdjson, etc.).
  • Embodied intelligence has become a shared narrative among domestic vendors, with the software stack consolidating layer by layer: SpacemiT’s robotics stack filled in SONIC motion tracking, RGB-D SLAM and Nav2, and motor and peripheral drivers within a week (advancing layer by layer as “runtime interfaces — policy assets — simulation loop — peripherals”), and disclosed plans for a “brain-cerebellum fusion chip”; Suzhou Ruixin binds to the humanoid robot ecosystem with a dataflow architecture; on the academic side, reproducible methodologies (datasets, tutorials) are thickening the infrastructure.
  • Next issue’s focus: Whether openRuyi 2026.09 will be released (including RVA23 integration and cloud-native stack updates); ESWIN Computing’s IPO pricing and EIC7X release cadence; XiangShan XSCache “Oceanus” and vector branch merge developments; the pace at which the ESP32-S31 Linux BSP moves from developer preview to official; upstreaming developments for SpacemiT’s ggml-spacemit backend.

Appendix: Sources and Verification Notes

Sources (Five Daily Briefings)

  • 09-21 issue: window 09-18 05:18 to 09-21 05:18 (Monday three-day window, covering the previous weekend); this issue includes entries from 09-18 to 09-20 (such as the Yixing Intelligent funding round and DAMO XuanTie XuanTie_V1.4.0), with original dates retained in the body text.
  • 09-22 issue: window 09-21 05:00 to 09-22 05:00; 09-23 issue: 09-22 05:00 to 09-23 05:00; 09-24 issue: 09-23 05:00 to 09-24 05:00; 09-25 issue: 09-24 05:00 to 09-25 05:00.
  • Developments from the weekend following this period (09-26 to 09-27) will be merged into next Monday’s briefing; developments from the previous weekend (09-19 to 09-20) have already been covered in the 09-21 issue.

Verification Methods

  • GitHub organization verification (168-hour window): covering organizations and key XiangShan-family repositories including DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT (including its robotics organization), Sipeed, revyos, OpenHW, Radxa Linkr, and openRuyi, with commit-level review and Atom feed fallback.
  • openRuyi dual-source verification: cross-checked between the official website news page (latest 2026.08, published 08-27) and the GitHub repository (dual-line kernel upgrades, kvm-unit-tests, SPECS commits).
  • Member company website inspection: 391 companies completed (240 unchanged / 82 changed / 69 failed); all changes were homepage marketing and news feed updates (NVIDIA, AMD, Infineon, Tenstorrent, university pages, etc.), with no substantive developments identifiable as new product, funding, or architecture announcements; failed sites were mainly domestic and anti-scraping sites, which did not block the inspection process.

Scope Notes

  • Vendor, park, and media single-source entries are flagged in the body text: Ruixin “Gaoguang D35” mass production and the “12nm beats NVIDIA 7nm” claim, Aowei Lingxin funding (official announcement basis), Lanxin LX500 customers and orders, Aheesa VIHAAN-I (not yet in mass production), UPC research (single core model only, cross-chip requires retraining).
  • Non-RISC-V entry boundaries: Zhenwu V900 and the Yitian series are included under the “domestic core team” criterion (Yitian uses the Arm instruction set); Espressif ESP32-S2/S3 use Xtensa cores, while the ESP32-C series and P4, S31 use RISC-V cores, and related entries have been filtered by core attribution.
  • Conference-related information (2026 Semiconductor Ecosystem Development Conference, IC WORLD Forum, Global AI Chip Summit, Global Digital Trade Expo, SEMICON India, AI Infra Summit) is all annotated with conference dates; some “follow-up” entries are secondary disclosures of conference content and are not double-counted as new events.

Main References

Data sources: Daily RISC-V Global Developments Briefing (five issues from 2026-09-21 to 2026-09-25) and hands-on verification during this period; reporting period is September 21 to September 25, 2026.