Research window: 2026-10-28 05:00 ~ 2026-10-29 05:00 (Beijing time, 24 hours).

Sources: Google News aggregation (14 supplementary and 17 regular queries in Chinese and English, via proxy), Hacker News, Phoronix, CNX Software, LinuxGizmos, riscv.org, the openRuyi official news page and main repository, website inspections of RISC-V International member companies (391), riscv100.top leaderboard inspection, and GitHub (XiangShan/NEMU/difftest/XSCache/GEM5, DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT and spacemit-robotics, Sipeed, revyos, openRuyi-Project, Radxa Linkr, OpenHW, and other organizations and key repositories for commit and release searches).

In This Issue

  • Today’s Highlight: Qwenputer compiles an RV32IM CPU into Qwen3.5 weights, using GDN state as RAM (10-28)
  • I. Open-Source Community and Software Ecosystem
    • XiangShan difftest supports remote XDMA board relay, enabling cross-machine FPGA verification scheduling (10-28)
    • XiangShan GEM5 adds TEA profiling option; XiangShan CI updates profile and fuzz testing (10-28)
    • openRuyi: 20 commits in one day; rust-vmm component family merged as a group, krb5 service architecture refactored (10-28)
    • CORE-V CVW fixes CBO cache management: final-beat stall for uncached cbo.zero and PBMT alias dispatch (10-28)
  • II. Product and Ecosystem Updates
    • LILYGO T-Display K230: Kendryte K230 dual-core RISC-V handheld dev kit (10-28)
    • Microchip PIC64-HPSC releases early irradiation results: TID 200 krad(Si), SEL 78.2 MeV·cm²/mg (10-28)
    • GUITION launches VisionGo series, led by 7-inch ESP32-P4 all-in-one display module (10-28)
    • SiFive positions RISC-V as AI accelerator control layer, with X100/X200/X300 as ACUs (10-28)
  • III. Deep Dive on Domestic Teams
    • ESWIN Computing CTO He Ning: automotive-grade and embodied intelligence as second and third growth curves; RISC-V consumer AI NAS to enter mass production in Q4 (10-28)
    • SpacemiT spine-triton follows spine-mlir 0.8.1, VMT4D example re-tunes tiling (10-28)
    • Sophgo LLM-TPU adds Qwen3.6-35B-A3B bmodel link (10-28)
  • IV. Special Chapter: Embodied Intelligence and Robotics
    • SpacemiT humanoid_common integrates motion adapter and operator client; whole-body control supports tabulated coupling (10-28)
    • unitree-go2 switches to terrain-only V2 walking policy, zero-copy IMU snapshot reads (10-28)
    • peripherals-imu supports HI91 serial feedback, BMI270 IIO channel multiplexing (10-28)
  • V. Summary and Trend Observations

Today’s Focus: Qwenputer compiles an RV32IM CPU into Qwen3.5 weights, using GDN state as RAM (10-28)

Developer Divyansh Agrawal has released Qwenputer: an untrained Qwen3.5-4B that compiles a 32-bit RISC-V CPU directly into the model weights and uses the model’s own Gated DeltaNet layer state as memory. Within the window it was picked up by Adafruit, Startup Fortune, and several other outlets, and sparked discussion on Hacker News.

The technical path has three steps. The first step turns GDN into precisely addressable RAM: set the gate to 1, set the write strength beta to 1, and encode keys with one-hot vectors, so each write overwrites exactly one row and each query reads exactly one value; the GDN head thus becomes row-addressable storage whose state size does not grow with context. The second step compiles the CPU into layers: with no training, a compiler maps steps such as “read register / add / conditional jump” one by one onto attention heads (table lookup), feed-forward layers (arithmetic), and DeltaNet heads (RAM), with the CPU occupying the 11 layers before Qwen’s 32 layers. The third step runs execution out during decoding: each instruction corresponds to a few generated tokens (ADDR specifies the write row, VAL carries the value, STEP ends the instruction), and these tokens are themselves the execution trace.

The core is RV32IM plus the Zba extension, along with a small big-number unit. The official claim is that it passes riscv-tests, that program results match qemu, and that it free-runs (i.e., advances entirely on its own output with no reference machine correcting it mid-way) for 18 million instructions with not a single error; about 230,000 output positions were compared against reference-machine replay with zero mismatches. It can run C and MicroPython, but requires a small driver, RvChat, to load firmware and keep trace tokens out of the Qwen layers, so for now it cannot be run directly via an ordinary generate call. On performance, each instruction costs several decoding tokens, and the benchmark batched executor runs at about 3,200 CPU tokens/second on an L4.

On results, on the DeepMind arithmetic set div_big scores 97.5% (Qwen with a Python tool: 95%; base model: 72.5%), mul_big 97.5% (tool: 100%; base: 55%), mul_div_multiple_longer 100% (tool: 97.5%; base: 90%), and add_or_sub_big 97.5% (tool: 97.5%; base: 87.5%); on NUPA long-integer arithmetic it rises from 48.6% to 100%. An experimental file system was also built alongside it (1,024-slot directory, up to 512 files, roughly 53,000 tokens of text), which persists across sessions once written to GDN state. The cost is an 18.8 GB checkpoint (about twice the base model, mostly zero padding).

  • Observation: This is not industry news and should not be read as a product announcement. It is worth including because it demonstrates two things related to RISC-V: first, any deterministic ISA can be compiled into weights — the barrier to an ISA has never been instruction encoding but the software stack and ecosystem; second, the model’s internal addressable state can serve as a deterministic execution environment, which is a ready-made testbed for safety research such as “compiling monitoring capability into the weights so the model itself cannot tamper with it.” The flip side must be seen just as clearly: 18.8 GB of weights, several tokens per instruction, and the need for a dedicated driver mean it is destined to be a research apparatus rather than a chip replacement — teams actually building RISC-V chips need not adjust their roadmaps because of it.

I. Open-Source Community and Software Ecosystem

1.1 XiangShan difftest supports remote XDMA board relay, enabling cross-machine scheduling for FPGA verification

Date: 2026-10-28　Source: GitHub: OpenXiangShan/difftest commit history

Three commits landed in the difftest window, the core one being feat(fpga): support a remote XDMA board relay (#1011): the link between the DUT on FPGA and the reference model is reworked to be relayed through a remote XDMA board, so the verification machine and the board no longer need to be co-located on the same host. Two companion commits: fix(fpga): let fork REF finish after the final endpoint (#1010), which corrects the timing under which the reference model wraps up after the final endpoint in fork scenarios; and fix(mma): accept zero-sized reference operations (#1012), which lets the matrix extension path tolerate zero-length reference operations so that no-ops are not rejected as errors.

  • Observation: Taken together, these three commits show difftest evolving from a “single-machine comparator” into a “remotely schedulable verification service.” The remote relay addresses resource utilization—a single FPGA verification setup often sits idle in a queue, and once the link can cross machines, multiple users and tasks can time-share it. For teams building RISC-V cores, verification machine time is usually scarcer than design manpower, making this kind of change more practical than yet another performance optimization.

1.2 XiangShan GEM5 adds TEA profiling option; XiangShan CI updates profile and fuzzing

Date: 2026-10-28　Source: GitHub: OpenXiangShan/GEM5 commit history, GitHub: OpenXiangShan/XiangShan commit history (kunminghu-v3 branch)

On the GEM5 side, cpu-o3: Add optional TEA profiling for XiangShan (#1255) was added, attaching an optional TEA profiling path to the XiangShan model; earlier in the same window the repo had just merged a batch of architectural fixes, including sv48 functional-level TLB initialization, L2 prefetch source identification in CDP, and Sstc timer support. The main XiangShan repo landed ci: update profile & improve fuzz (#6758) the same day, updating the CI profiling configuration and strengthening the fuzzing workflow.

  • Observation: Profiling capability and fuzzing advancing in tandem is a sign that a core has entered the “performance attribution + long-run stability” phase. The GEM5 line deserves particular attention—it is not a mere performance model but an architecture exploration platform with TEA profiling, where many of XiangShan’s microarchitectural decisions are tried before reaching RTL.

1.3 openRuyi lands 20 commits in one day: rust-vmm component family merged as a group, krb5 service stack reworked

Date: 2026-10-28　Source: GitHub: openRuyi-Project/openRuyi commit history

The openRuyi main repo saw 20 commits in the window (the top 20 commits before the cutoff all fall within it), in four groups. First, the rust-vmm component family merged as a group: rust-linux-loader 0.14, rust-vm-memory 0.18, and rust-kvm-ioctls 0.25 added, with rust-acpi-tables bumped to 0.2.1. Second, the krb5 service stack reworked in three commits: KDC paths aligned with systemd services, realm configuration made neutral and able to follow upstream credential conventions, and build options switched to system libraries with upstream tests run. Third, language and build infrastructure: go backported index optimization, go-google-api and go-git-related packages following the gcfg v2 dependency, cmake providing Python distribution package metadata, python-scikit-build-core bumped to 1.1.1, python-httptools relaxing its setuptools version pin, and attr bumped to 2.6.0. Fourth, cleanup fixes: ceph following a new main-branch snapshot, procps fixing the rpm name and restoring uptime, sql-migrate added, python-graphql-core downgraded to 3.2.13, and python-backports-zstd removed.

  • Observation: The one-shot landing of the four rust-vmm components is the most substantive signal this issue. This component set is the foundation of Rust virtualization stacks such as Cloud Hypervisor, and their group entry into the distribution means the dependencies for running a Rust-written VMM on RISC-V are now in place. Compared with porting an individual application, swapping out the language stack of the virtualization base has a deeper impact.

1.4 CORE-V CVW fixes CBO cache management: uncached cbo.zero stalls through final beat and PBMT alias dispatch

Date: 2026-10-28　Source: GitHub: openhwfoundation/cvw commit history

The CORE-V CVW repo merged two cache block operation (CBO) fixes: Stall an uncached cbo.zero through its final beat makes cbo.zero in uncached regions stall all the way to the final beat, preventing the pipeline from being released before the write response completes; Send cbo.clean/flush/inval to the D$ through PBMT=NC/IO aliases ensures these three operations still reach the data cache correctly when the page table entry is marked as non-cacheable or an IO alias. The two were merged via PR #2010 and #2008.

  • Observation: CBO is among the most easily overlooked instruction groups in RVA23—it does not show up on performance leaderboards like vector extensions do, but the final-beat timing in uncached regions and PBMT alias handling are exactly the spots that “never trigger in normal operation, and corrupt data when they do.” This is precisely where projects like CORE-V, which test spec boundaries one by one, earn their value.

II. Product and Ecosystem Updates

2.1 LILYGO T-Display K230: A Kendryte K230 Dual-Core RISC-V Handheld Dev Kit

Date: 2026-10-28　Source: CNX Software: LILYGO T-Display K230 RISC-V AI dev kit, GitHub: Xinyuan-LilyGO/T-Display-K230

LILYGO has launched the T-Display K230 handheld development kit, built around Canaan’s Kendryte K230 dual-core 64-bit RISC-V: a 1.6GHz big core with the RISC-V Vector Extension 1.0 and FPU, an 800MHz little core supporting RV64GCB, plus an integrated KPU supporting INT8/INT16 (official typical network performance: ResNet50 at no less than 85fps, MobileNetV2 at no less than 670fps, YOLOv5S at no less than 38fps) and H.264/H.265 hardware codec. The device features a 4.1-inch 568×123 AMOLED touchscreen (MIPI DSI), 1GB LPDDR4, a 2MP GC2093 camera, HDMI 1080p30 output, 100M Ethernet, WiFi 4, and an SX1262 or LR2021 LoRa transceiver; an optional keyboard base adds an nRF9151 supporting LTE-M, NB-IoT, and GNSS, along with two 21700 battery bays. On the software side, there is the K230 Linux SDK, CanMV/RT-Smart firmware, and an LVGL launcher, and the new firmware already offers experimental Meshtastic and LoRaWAN support. Pricing: roughly $98.79 for the bare board, about $150 for the kit, and an additional $70.94 for the keyboard base ($113.25 with the nRF9151).

  • Observation: The K230 is one of the few domestic dual-core RISC-V chips that both runs Linux and integrates a KPU. LILYGO has packaged it into a handheld form factor with a physical keyboard, and the target is clear: ad-hoc networking scenarios like LoRa and Meshtastic need keyboard input, long battery life, and offline AI, and previously only Raspberry Pi solutions or pure-MCU solutions existed, neither of which fit well. At the ~$150 price point, it is affordable enough for both the amateur radio community and the vocational education market.

2.2 Microchip PIC64-HPSC Releases Early Radiation Results: TID 200 krad(Si), SEL 78.2 MeV·cm²/mg

Date: 2026-10-28 (announced 10-27)　Source: Microchip: PIC64-HPSC program milestone press release, Hacker News discussion: PIC64GX 64-bit RISC-V quad-core microprocessor

Microchip announced early program milestones for the PIC64-HPSC high-performance spaceflight computing series. Early radiation characterization of the radiation-hardened PIC64-HPSC1000-RH shows a total ionizing dose (TID) of 200 krad(Si), with single-event latchup (SEL) tested to 78.2 MeV·cm²/mg under specified operating conditions; in single-event effect characterization, the system controller exhibited no uncorrectable errors and required no external reset. Meanwhile, the early access program has delivered silicon and development kits to customers, and board partners are developing VPX and VNX+ compute modules based on the platform. The series originated from NASA and JPL’s assessment of future spaceflight computing needs, with the HPSC contract awarded to Microchip in 2022; NASA’s FY26 Civil Space Shortfall priority list ranks “advanced in-orbit computing for spaceflight operations” as the third-ranked technology shortfall.

  • Observation: Space is one of the few markets for RISC-V where demand is real, the metrics are hard, and substitutes are not accepted. The 200 krad(Si) tier means mission coverage can extend from LEO to beyond the Moon, and SEL and SEE data are the entry ticket for space-grade selection—without measured radiation data, no matter how open the architecture, it will not make it into a qualified parts catalog. Another notable aspect of this thread is the path: the government defines the requirements first (NASA/JPL assessment), a commercial company delivers the platform, and then board partners adapt it into VPX form factors—a supply chain far longer than consumer electronics but with much greater certainty.

2.3 GUITION Launches VisionGo Series, Led by a 7-Inch ESP32-P4 All-in-One Display Module

Date: 2026-10-28　Source: StreetInsider/ABNewswire: GUITION launches VisionGo series press release

GUITION, under Shenzhen Jingcai Intelligent, has released the VisionGo series of embedded display modules, led by the 7-inch ESP32-P4 all-in-one display JC1060P470C_I_W_Y: dual-core RISC-V at 360 to 400MHz class, 1024×600 IPS capacitive touch, 32MB PSRAM, 16MB Flash, integrated WiFi and Bluetooth, a TF card slot, multiple GPIOs, and MIPI-CSI support on some models. The full series spans 1.28 inches to 21.5 inches, and the company says it is compatible with ESP-IDF, Arduino IDE, MicroPython, LVGL, ESPHome, and Home Assistant.

  • Observation: The ESP32-P4 is solidifying the “HMI display plus main controller” into a standard module form factor. For teams building smart home panels, energy storage inverter HMIs, or EV charger displays, such modules lower the hardware barrier to “pick a screen and write the UI,” leaving differentiation only in structure and algorithms—which also means hardware margins in mid-to-low-end HMI will be eroded even faster.

2.4 SiFive Positions RISC-V as the AI Accelerator Control Layer, with X100/X200/X300 as ACUs

Date: 2026-10-28 (SiFive blog 10-16, Jon Peddie analysis 10-26, community discussion sparked 10-28)　Source: SiFive: The Next Leap in Datacenter AI — Orchestrating Custom Accelerators with Intelligent Control Units, Jon Peddie Research: SiFive makes the case for RISC-V as the control layer for custom AI accelerators

SiFive proposes using its Intelligence series processors as “accelerator control units” (ACUs), inserting a programmable control plane between the host processor and custom accelerators to handle low-latency command dispatch, data movement, pre/post-processing, and algorithm tuning. Its argument targets three shortcomings of conventional approaches: hardwired state machines require costly hardware respins when algorithms or data formats change; frequent data movement on a shared bus introduces unacceptable latency and blocks memory pipelines; and offloading low-level scheduling to the host CPU consumes host compute while amplifying latency. The series is segmented with the X100 for control-intensive scenarios sensitive to area and latency, while the X200 and X300 offer greater vector bandwidth and compute. Jon Peddie Research’s analysis adds two deployment data points: Google data centers already use the Intelligence X200 as AI compute hosts, and another unnamed top-tier US semiconductor company has licensed the X100 for industrial edge AI.

  • Observation: This judgment is worth noting in the trends column—RISC-V’s commercial value is shifting from “ISA substitute” to “a fixed role in heterogeneous systems.” SiFive’s own phrasing is that “value is moving out of the ISA,” with the remaining differentiation in implementation and system integration. The implication for domestic vendors is equally direct: rather than directly replacing Arm main controllers, it is better to build the control and scheduling layer alongside AI accelerators—a path with far lower software ecosystem requirements and one that is easier to win orders with first.

III. In-depth Look at Domestic Teams

3.1 ESWIN Computing CTO He Ning: Automotive-Grade and Embodied Intelligence as Second and Third Growth Curves; RISC-V Consumer AI NAS to Enter Mass Production in Q4

Date: 2026-10-28　Source: [21st Century Business Herald: 21 Dialogue ESWIN Computing CTO He Ning, the High-Value Inflection Point for RISC-V Is Coming](https://m.21jingji.com/article/20261028/herald/c00176cd6a36a5ee0b9f1caf628e8f13_zaker.html)

In an interview after the summit, He Ning, Senior Vice President and Chief Technology Officer of ESWIN Computing, offered several specific judgments. First, the integration of RISC-V and AI follows three paths: RISC-V as the main control CPU with an external NPU (loose coupling, already common in products); RISC-V entering the AI unit to handle scheduling (NVIDIA GPUs embed a large number of small RISC-V cores internally); and giving RISC-V its own AI compute capability through vector and matrix extensions. He gave a timeline: matrix extensions account for more than 80% of large-model computation, and it will take another one to two years for the specification to mature and enter products, and another two to three years after that before standardized products reach scale; “the explosion of deep RISC-V-AI integration will probably take more than three years.” Second, the software ecosystem remains the biggest obstacle, but three windows of opportunity have emerged: AI is restructuring software and hardware together, large models have restructured the algorithm and operator toolchains, and the center of gravity of compute is shifting from training to inference (the inference ecosystem is significantly less complex than training).

On the implementation side, there are three concrete advances. On the automotive-grade side, the EAM2011 is China’s first automotive-grade MCU supporting lightweight AI applications, equipped with a self-developed 32-bit RISC-V core, and has entered volume application in display assemblies, in-vehicle wireless charging, and battery management systems; the self-developed RISC-V CPU IP R520A has passed TÜV Rheinland’s ASIL-D functional safety certification, becoming the world’s first multi-core, multi-architecture RISC-V core to pass ASIL-D (the earlier R500A was the world’s first RISC-V core to obtain ASIL-B certification). On the edge and intelligent computing side, the company has partnered with Zspace to launch the world’s first consumer-grade AI NAS based on the RISC-V architecture, with mass production and sales planned for the fourth quarter of 2026. On the ecosystem side, the company has mass-produced more than 150 products, serves 220 customers worldwide, and is advancing its ecosystem through the RISAA ecosystem technology platform and the RDI alliance it led the establishment of.

  • Observation: The most solid statement in the interview is that the barrier in automotive-grade lies not in the chip but in the system—from the supply chain and Tier1 to automaker adoption, the chain is extremely long, and producing the chip is only the first step. ASIL-D matters because it turns “can we get into the intelligent driving domain” from a business question into a certificate question; once the certificate is obtained, RISC-V’s flexibility is qualified to match the frequently changing parts of “intelligent vehicle function integration.” As for the AI NAS, Q4 mass production is a verifiable time point worth revisiting next quarter.

3.2 SpacemiT spine-triton Follows spine-mlir 0.8.1, VMT4D Example Retuned for Tiling

Date: 2026-10-28　Source: GitHub: spacemit-com/spine-triton commit history

SpacemiT’s Triton backend repository saw 5 commits in the window (including 2 merges), substantively two things: first, bumping the precompiled spine-mlir download link to 0.8.1 and updating the version number accordingly; second, retuning the matrix-vector transpose 4D (VMT4D) example to the “benchmark-optimal” 128×32 tiling and adding a preprocessing transpose. The previous day the repository also fixed smt_rvisa: fix constexpr capture shadowing kernel params—a problem where constant capture on the RISC-V ISA side shadowed kernel parameters—as well as a CI guard to skip non-wheel jobs when BUILD_COMMIT is set.

  • Observation: spine-mlir is the upstream on the compiler side, and spine-triton following 0.8.1 shows the two repositories have developed a coordinated release rhythm. More noteworthy is the “example as benchmark” approach: by pinning the VMT4D example’s tiling parameters to the measured optimum, downstream integrators get not a sample that merely runs, but a reproducible performance baseline.

Date: 2026-10-28　Source: GitHub: sophgo/LLM-TPU commit history

The Sophgo LLM-TPU repository added feat: add qwen3.6-35b-a3b bmodel link, providing a download link for the compiled bmodel of Qwen3.6-35B-A3B. The repository’s earlier adaptation cadence included Python examples for MiniCPM5-2B and MiniCPMV4.7 (targeting BM1684X and CV84X6), as well as compatibility support for bge-reranker-v2-m3 and MinerU2.5-Pro.

  • Observation: 35B-A3B is a sparse MoE model with only about 3B active parameters; being able to offer it as a downloadable bmodel on TPU shows that Sophgo’s model adaptation has shifted from dense small models to sparse large models—such models are more sensitive to memory bandwidth and scheduling and less demanding on peak compute, which is exactly the comfort zone of domestic TPUs. Providing only a link and no code is a common distribution approach among domestic vendors, with weights and compiled artifacts hosted by the model provider.

IV. Embodied Intelligence and Robotics Special Chapter

4.1 SpacemiT humanoid_common integrates motion adapters and operator clients; whole-body control supports tabulated couplings

Date: 2026-10-28　Source: GitHub: spacemit-robotics/humanoid_common, GitHub: spacemit-robotics/control_whole_body

spacemit-robotics’ humanoid_common merged integrate motion adapters and operator clients, wiring motion adapters and operator clients into the unified runtime; an earlier commit (10-26) had already integrated the operator voice client and static parameters. control_whole_body merged support tabulated couplings and feedback recovery (#8) the same day, adding a table-driven joint coupling and feedback recovery path to whole-body control.

  • Observation: Yesterday this column still read “batch sync, no substantive commits”; today the same org pushed two functional commits back-to-back at 04:07 and 04:08 (UTC), so that judgment needs revising—SpacemiT’s robot middleware layer is advancing steadily. The so-called “operator clients” are the approach of plugging capabilities such as motion and voice into the on-robot runtime as remote services, which is the same line as its string of commits since late September (operator services, fixed-base trajectory control, upper-limb takeover, SONIC motion selection): humanoid_common is becoming the middleware layer of the robot body itself, rather than a driver collection for a particular model.

4.2 unitree-go2 switches to terrain-only V2 walking policy, zero-copy IMU snapshot reads

Date: 2026-10-28　Source: GitHub: spacemit-robotics/unitree-go2

The unitree-go2 repo had 6 commits in the window, focused on the walking policy and perception reads: it switched to a “terrain-only” V2 walking policy and pinned the model download to a specific version, while retaining the existing model archive download architecture; on the performance side, read IMU snapshots without copying motor state (PR #4) stops IMU snapshot reads from also copying motor state; it also fixed the hardware configuration notes for SBUS dependency loading and optional SBUS recovery under CI regression.

  • Observation: “Terrain-only” means the policy no longer branches by operating condition such as steps or slopes, but covers them with a single terrain policy—a common trade-off that narrows the domain randomization range of sim2real in exchange for real-machine stability and reproducibility. Zero-copy IMU snapshot reads directly target a jitter source in 1kHz-class control loops: by removing motor state from the data path, read latency goes from “proportional to state size” to constant.

4.3 peripherals-imu supports HI91 serial feedback, BMI270 IIO channel reuse

Date: 2026-10-28　Source: GitHub: spacemit-robotics/peripherals-imu

peripherals-imu had two commits in the window: feat(imu): support HI91 serial feedback (#21) adds parsing of HI91 serial feedback; perf(imu): reuse BMI270 IIO channels and pace sensor reads (#22) switches to reusing BMI270’s kernel IIO channels and throttles sensor reads. The repo previously covered BMI270 SPI event-driven operation, UART drivers for IWT603 and Forsense, and interrupt output for ICM42670P.

  • Observation: The IMU driver line is moving from “one protocol per model” toward “a unified kernel IIO entry point plus a few private-protocol fallbacks.” That’s a good signal for robot OEMs—swapping sensors no longer requires application-layer changes, as long as a kernel IIO channel exists; for SpacemiT itself, supporting a third serial protocol (IWT603, Forsense, HI91) means its robot reference design is adapting to more domestic IMU vendors.

V. Summary and Trend Observations

1. The next step for verification infrastructure is resource pooling. Today’s remote XDMA board relay in XiangShan difftest removes the constraint that “the verification machine and the board must be on the same host.” Combined with the past three days’ fast-ref and fork checks, reftrace record replay, and the MMA synchronous verification toggle, difftest’s technical roadmap has shifted from increasing the speed of individual comparisons to scheduling multiple sets of verification resources. Teams working on RISC-V cores in China generally lack machine time, so this path has more practical value than adding yet another performance optimization point.

2. RISC-V’s role in AI is shifting from “replacing the main controller” to “a fixed supporting player.” Two independent statements appeared on the same day: SiFive positioned its Intelligence series as control units for AI accelerators (Google data centers already use the X200 as an AI compute host), while ESWIN’s He Ning broke down the integration of RISC-V and AI into three paths—main-controller offload, intra-unit scheduling, and instruction-set extension—and gave a three-year timeline. Both point to the same judgment: head-on replacement on advanced process nodes is not today’s main battlefield; the control plane, scheduling plane, and inference side are where orders can be won.

3. Automotive-grade certification is the dividing line this round, not consumer electronics. ESWIN’s R520A obtained TÜV Rheinland ASIL-D (the world’s first multi-core, multi-architecture RISC-V core), the EAM2011 automotive-grade MCU has already entered mass production in vehicles, and the consumer AI NAS developed with Jizhikongjian is scheduled for mass production in Q4. Of these three lines, ASIL-D is the only threshold that cannot be bypassed through price competition: it turns “can we get into the intelligent-driving domain” into a certification question. For other domestic RISC-V vendors aiming at high-value scenarios, this certificate’s timeline deserves separate tracking.

4. The robotics stack has moved from “synchronization” to “development.” spacemit-robotics, which yesterday was judged to be batch mirror synchronization, today produced ten substantive commits across four repositories: the middleware layer integrated motion adapters and operator clients, whole-body control added tabular coupling and feedback recovery, Go2 switched to a terrain-only V2 policy, and the IMU driver expanded to a third vendor’s serial protocol while reusing the kernel IIO. The method for reading this section should still be to look at the content of main-branch commits, but conclusions must follow the evidence.

5. Information volume and basis for judgment in this issue. After deduplication within the Chinese and English Google News windows, substantive new items centered on six: Qwenputer, the ESWIN CTO interview, LILYGO K230, Microchip PIC64-HPSC, GUITION VisionGo, and the SiFive control-layer discussion; the rest were follow-up summit interpretations and stock-market pieces, excluded under the deduplication rules. The open-source side was the main body of this issue: the XiangShan verification chain, openRuyi’s rust-vmm, CORE-V’s CBO fixes, and SpacemiT’s compiler/robotics stack all have verifiable commit records.

Full Source List

Source Verification Table

Source Verification result
Google News aggregation (17 standard queries plus 14 supplementary queries in Chinese and English, 24-hour window) After deduplication, 6 substantive new items: Qwenputer (Adafruit, Startup Fortune, HN follow-ups), the ESWIN CTO interview, LILYGO T-Display K230, the Microchip PIC64-HPSC milestone, GUITION VisionGo, and the SiFive control-layer discussion; summit follow-up interpretations (SpacemiT’s full-stack in-house article, DAMO XuanTie shipment figures) and the Lanxin LX500 supernode (published 10-19) and ESWIN’s Hong Kong IPO (listed 10-09) are all existing content in circulation and were not re-included under the deduplication rules; “Sophgo” still returned coal-transport and stock-market pieces, and “Espressif” had no hits within the window, so both were excluded
XiangShan XiangShan/NEMU/difftest/XSCache/GEM5 Kunminghu V3 branch: 1 commit (CI profile and fuzzing); difftest: 3 commits (remote XDMA relay, fork reference wrap-up, zero-length MMA reference operation); GEM5: 1 commit (XiangShan TEA profiling); NEMU and XSCache had no commits within the window
openRuyi main repo and official site Main repo: 20 commits within the window (the four rust-vmm pieces, three krb5 refactors, ceph, go and python build chains, procps and attr, etc.); the latest release on the official news page is still the 2026.09 version; this month’s version has not been released
DAMO XuanTie, ESWIN, Nuclei, Espressif, Sipeed XuanTie, ESWIN, and Nuclei had no organization-level pushes within the window; Espressif had pushes across 43 repositories, the normal cadence of weekly synchronization for its main components; Sipeed had only 1 commit in SLogicWeb (web frontend)
SpacemiT spacemit-com and spacemit-robotics spacemit-com: pushes across 10 repos, substantively 5 commits in spine-triton (spine-mlir 0.8.1, VMT4D tiling retuning) plus routine submodule updates in ai-sdk; spacemit-robotics: 10 substantive commits across 4 repos (humanoid_common, control_whole_body, unitree-go2, peripherals-imu)
CORE-V and OpenHW CVW: 4 commits (two CBO fixes, two merges); CVA6 master became read-only on 10-23, with no commits within the window
Sophgo LLM-TPU: 1 commit (Qwen3.6-35B-A3B bmodel link); the other 22 repos in the same organization showed batch-synchronization characteristics between 06:40 and 07:42 (UTC), not new development
Member company website inspection (391 companies) 391 sites inspected; pages that changed were mainly universities and research institutions (MIT, KU Leuven, Shanghai Jiao Tong University, SIAT, University of Athens, National University of Singapore, etc.), with changes consisting of homepage news and admissions information refreshes and no substantive developments such as new products, funding, or architecture announcements; 67 sites failed to be fetched (including the Institute of Software of the Chinese Academy of Sciences, Beijing Institute of Open Source Chip, Tencent, Ingenic, Sanechips, etc.), which is not blocking
riscv100.top inspection No changes (no additions or numerical changes in What’s New, Upcoming, committee members, or the six SPEC rankings)

Limitations

For this issue, the GitHub side was cross-checked using organization-level APIs plus commit feeds (Atom); the anonymous rate limit for organization-level APIs was still close to exhaustion late in collection, so activity within the window in some non-priority repositories may have been missed. The commit feeds for GEM5 and CVW experienced fetch failures during secondary review; the data in this article is based on the first successful fetch. For the member company website inspection, 67 sites could not have their body text retrieved due to anti-scraping measures, redesigns, or too-short load times, so their website updates were not included in this issue’s judgments. The 6th RISC-V China Summit ended on 10-20, and verification of changes to the official website and source repositories stops as of this issue.