Research window: Past 24 hours (2026-09-17 05:18 ~ 2026-09-18 05:18, Beijing time) Sources: Hacker News, Google News aggregation (multiple Chinese and English query sets, via proxy), China Science and Technology Network / Science and Technology Daily, ifeng.com, Gasgoo, Ubuntu official blog, EE Times Asia, Yahoo Finance, OSCHINA, openRuyi official website, RISC-V International official website, RISC-V developer community, and GitHub (push and commit searches across organizations and key repositories including XiangShan / GEM5 / NEMU / difftest, revyos, Sophgo, SpacemiT, Sipeed, DAMO XuanTie, Espressif, Radxa Linkr, etc.), RISC-V International member company website inspections (391 companies)

Issue Index

  • Today’s Highlight: The SPMP supervisor-mode physical memory protection standard led by the Shanghai Jiao Tong University IPADS team has been merged into the RISC-V international instruction set standard, becoming the first ISA feature initiated from scratch and fully led by a mainland Chinese team since the foundation’s establishment (09-17)
  • I. Open Source Community and Software Ecosystem
    • Canonical: Evolution roadmap after RVA23, CFI, matrix extensions, and new extensions in RVA23.1 (09-17)
    • XiangShan simulation chain GEM5: three commits including pre-decode alignment and cross-buffer retention of L2 request sources (09-17)
    • XiangShan difftest: disabling Verilator SLP vectorization to avoid LLVM miscompilation (09-17)
    • XiangShan main repo and NEMU: no new commits within the window (09-17 check)
    • revyos/linux: added LinuxBoot and DRM_AST kernel configs, CI adds cross and native builds (09-17)
    • openRuyi: the latest news page on the official site is still the 2026.08 version; the September version has not been released (09-17 check)
  • II. Product and Ecosystem Developments
    • Automotive: the first automotive-domain RISC-V industry standard (QC/T) begins drafting, with 34 companies participating (09-17)
    • DAMO Academy: RISC-V automotive-grade functional safety development cycles are typically 3 to 5 years; STL diagnostic coverage differs between RTL and netlist (09-17)
    • Changan Automobile: RISC-V cores have surpassed ARM in MCU compute power, and the company is exploring AI DSA architectures with custom instruction sets (09-17)
    • The SiFive and AMD ROCm data center demo reaches mainstream financial media, AMD rises 7% that day (09-17)
  • III. Deep Dive on Domestic Teams
    • DAMO XuanTie: damo-rv-priv-ats refactors Hypervisor test suite extension support gating (09-17)
    • SpacemiT: llama.cpp merges the SpacemiT backend into the multimodal mtmd pipeline (09-17)
    • SpacemiT: model-zoo-vision adds a V2D preprocessing backend, K3 clock tree documentation updated (09-17)
    • Sophgo: ZSBL releases SG2044 v3.1.0, sophon-demo completes the CV84X6 rename (09-17)
    • Sipeed: SLogic16U3 flashing toolchain shares a CLI and bundles libusb (09-17)
    • Member website inspection: 391 completed, no substantive developments identifiable as new products or financing found (09-17 check)
  • IV. Embodied Intelligence and Robotics Special Section
    • SpacemiT spacemit-robotics: humanoid common library and Linglong complete periodic motor position normalization (09-17)
    • SpacemiT spacemit-robotics: ROS cmd_vel human-machine interface adds configurable velocity bias (09-17)
    • SpacemiT spacemit-robotics: IMU peripheral repository builds all available drivers by default (09-17)
    • SpacemiT spacemit-robotics: Unitree G1 manual reference trajectory replay and constraint documentation merged (09-17)
  • V. Summary and Trend Observations

Today’s Highlight: A Chinese Proposal Fully Leads a RISC-V International Instruction Set Standard for the First Time

Date: 2026-09-17　Source: China Science and Technology Network / Science and Technology Daily, “Seven Years of Effort Achieve a Breakthrough from Zero! Chinese Proposal Formally Written into the RISC-V International Instruction Set Standard”

The SPMP (Supervisor-mode Physical Memory Protection) instruction set standard led by the Institute of Parallel and Distributed Systems (IPADS) team at Shanghai Jiao Tong University’s School of Computer Science has passed review by the RISC-V International Foundation board and been formally merged into the RISC-V instruction set architecture standard. This is the first ISA standard feature initiated from scratch and fully led by a mainland Chinese team since the RISC-V International Foundation was established. The report notes that the other ISA extensions approved in 2026 all came from overseas teams such as SiFive, Meta, and Qualcomm; domestically, progress at the implementation level, such as XiangShan, had previously been notable, but there was a gap in top-level instruction set standard-setting.

On the technical approach, SPMP addresses the challenge of lightweight security isolation for endpoint devices with a “check only the house number, not the index” scheme: it relies on a set of configuration entries inside the chip to record the start address, length, and access permissions of physical address regions. When the processor accesses memory, a single register check is sufficient to complete the permission decision, without multi-level address translation, achieving memory security isolation with minimal hardware overhead and filling RISC-V’s gap in high-security, low-power endpoint scenarios. The project submitted its first design draft in September 2019, and under the leadership of Professor Chen Haibo, core members including Du Dongdong, Yang Bicheng, and Xia Yubin led the effort for nearly 2,500 days to complete standardization. The proposal was selected as a RISC-V International Foundation 2021 security highlight feature and was also the only China-originated project among the Linux Foundation’s four major RISC-V security advances of 2023.

Deployment-side evidence is already in place: SPMP technology has been deployed on domestic chip platforms including the XiangShan open-source high-performance processor and Nuclei RISC-V IP. Bao Yungang, a board member of the RISC-V International Foundation and deputy director of the Institute of Computing Technology at the Chinese Academy of Sciences, commented that this enables China’s chip sector to achieve “a shift from passively following rules to actively defining rules.” For the industry, the significance of this event lies in the substantive change in standards discourse power: global chipmakers designing RISC-V chips can all choose this China-led security isolation specification, and domestic teams have moved from ecosystem application participants to specification suppliers.

I. Open-Source Community and Software Ecosystem

1.1 Canonical: The Evolution Path After RVA23 — CFI, Matrix Extensions, and RVA23.1

Date: 2026-09-17 (article published 09-15, entered the window via Hacker News on 09-17)　Source: Ubuntu official blog, “Evolution of the RISC-V ISA. What next after RVA23?”

Canonical’s Jon Taylor provides a systematic overview of the directions after RVA23. On the security side, taking CFI as an example, the extension was ratified in 2024 and consists of two independent extensions, Zicfilp and Zicfiss, designed to defend against return-oriented and jump-oriented control-flow attacks; the design aims to be as compatible as possible with existing RVA23 hardware, with the relevant instructions ignored when not implemented in hardware, but on pre-RVA23 hardware lacking Zimop support, Zicfiss instructions will trap — leaving room for compiler toolchains to adapt ahead of time. For matrix extensions, three routes are given: VME reuses the standard vector state, requiring no OS changes; IME extends the vector register file and adds result registers; AME uses an entirely new register file. The latter two require the OS to be aware of the additional register state during context switches, while applications can probe extensions at runtime via sys_riscv_hwprobe() and select an implementation path.

On the RVA23.1 side, three development options and two extension options are added, and the article highlights three of them as closely relevant to distributions: Double Trap Handling lets machine-mode or virtualization-mode handlers safely catch secondary traps under non-reentrant handler state, reducing the risk of system crashes and memory corruption; Supervisor Counter Delegation delegates counters downward; and platform-level capabilities that help the OS and toolchains interoperate. Canonical’s conclusion is that RVA23 provides a baseline for deployment at scale, while innovation remains concentrated in security and control flow, matrix computation, and minor revisions without mandatory extensions — the latter balancing software stability and the introduction of new features through a cadence in which “development options” come first and later profiles make them mandatory.

1.2 XiangShan Simulation Chain GEM5: Three Commits on Predecode Alignment, Cross-Buffer Retention of L2 Request Source, and More

Date: 2026-09-17　Source: OpenXiangShan/GEM5 PR #1150, PR #1156, PR #1123

The XiangShan GEM5 simulation repository landed three commits within the window. First, predecode alignment (Predeocde align, PR #1150, committed 09-17 23:19), correcting the alignment relationship between the predecode stage and front-end instruction fetch. Second, configuration-side support for upstream SE workload resources (PR #1156, 09-17 18:35), allowing upstream workload resource definitions to be referenced directly in syscall emulation mode and reducing local configuration divergence. Third, on the memory access side, retaining the source information of L2 requests across buffer transfers (PR #1123, 09-17 09:57), preventing requests from losing their initiator identity at intermediate buffer stages and thereby affecting subsequent fill and contention decisions. The three belong to the instruction fetch, configuration, and memory access directions respectively, and are small-step improvements in continuous iteration.

1.3 XiangShan difftest: Disabling Verilator SLP Vectorization to Avoid LLVM Miscompilation

Date: 2026-09-17　Source: OpenXiangShan/difftest PR #968

The XiangShan differential testing framework difftest merged a fix on 09-17 20:24: disabling SLP (Superword Level Parallelism) vectorization in Verilator builds. The reason is that this optimization triggers miscompilation under some LLVM versions, causing the simulation model’s behavior to deviate from the reference implementation, thereby producing false failures in differential comparison and interfering with the localization of real defects. Such problems — “toolchain miscompilation polluting verification results” — are not uncommon in open-source processor verification; the approach is to disable the suspect optimization at the build-option level to ensure consistency between simulation and hardware behavior, at the cost of some simulation performance.

1.4 XiangShan Main Repository and NEMU: No New Commits Within the Window

Date: Verified 2026-09-17　Source: OpenXiangShan/XiangShan commit search, OpenXiangShan/NEMU

Verification result: the XiangShan main repository has no new commits within the window; the most recent batch is the 09-16 vector floating-point unit refactor (merging VFALU and VFMul into VFMac) and 13 timing optimizations, already covered in the previous report; NEMU’s most recent commit is the 09-16 unification of log formats on the interrupt throw path, also already covered. The main repository’s branch list shows push records within this window, but the corresponding commits’ authors and commit times fall in earlier windows, so they do not constitute new development output and are not reported again in this issue.

1.5 revyos/linux: New LinuxBoot and DRM_AST Kernel Configs, CI Adds Cross and Native Builds

Date: 2026-09-17　Source: revyos/linux commit history

The revyos kernel repository landed a batch of configuration and CI commits on 09-18 03:42 (Beijing time): adding a linuxboot config item, enabling the DRM_AST display driver (targeting server-class BMC display output scenarios), and enabling SENSORS_LM63 sensor support. On the CI side, two pipelines — cross build and native build — were added to verify consistency of kernel artifacts across different host environments. This batch continues revyos’s main line over the past week of filling out the boot chain and board-level support for the SG2044/SG2042 server platforms.

1.6 openRuyi: Latest News Page Still Shows the 2026.08 Release; September Release Not Yet Out

Date: Verified 2026-09-17　Source: openRuyi news page

A check of the openRuyi official news list shows the latest entry is still “openRuyi 2026.08 released” (2026-08-27), and no September release page exists. Given the distribution’s monthly release cadence, the 2026.09 release is expected in late September and requires continued tracking; after release, the focus should be on verifying toolchain versions, kernel versions, RVA23 integration, and updates to the cloud-native/AI software stack.

II. Product and Ecosystem Developments

2.1 Automotive: First Automotive RISC-V Industry Standard (QC/T) Begins Drafting, 34 Companies Participating

Date: 2026-09-17　Source: Phoenix Auto / Wangtongshe Express “First Automotive RISC-V Industry Standard Begins Drafting, 34 Companies Participating”

At the 2026 6th Intelligent Automotive Chip Ecosystem Conference, Zhongqixin (Shenzhen) Technology Co., Ltd. disclosed that the first RISC-V industry standard in the automotive sector has begun drafting, under the QC/T standard number series, with 34 domestic and international companies currently participating. This marks a key step for RISC-V in China’s automotive industry from enterprise-level practice toward industry specification — previously, organized RISC-V efforts on the domestic automotive chip side were concentrated at the alliance and special committee level (in April 2026, the China Automotive Chip Industry Innovation Strategic Alliance established the RISC-V Automotive-Grade Chip Special Committee; in May, the RISC-V Working Committee Automotive Application Group of CESA was inaugurated). Entering industry standard drafting this time means the technology route is beginning to consolidate into verifiable specification text. At the same conference, companies including Zijin Semiconductor also shared practices in RISC-V-driven automotive chip innovation.

2.2 DAMO Academy: RISC-V Automotive-Grade Functional Safety Development Cycle Typically 3 to 5 Years; STL Diagnostic Coverage Differs Between RTL and Netlist

Date: 2026-09-17 (conference 09-16)　Source: Phoenix Auto “Alibaba DAMO Academy’s Li Weili Shares RISC-V Automotive-Grade Functional Safety Development at the 2026 6th Intelligent Automotive Chip Ecosystem Conference”, Gasgoo report on the same topic

Li Weili, processor architect at Alibaba DAMO Academy, offered a quantitative assessment of RISC-V automotive-grade deployment: domestic and international RISC-V automotive-grade applications have basically reached a usable state across four levels — IP, IC, complete systems, and software ecosystem — but functional safety development requires bidirectional iteration through process certification and product certification, with the full process generally taking 3 to 5 years. On the technical path, ASIL-D generally adopts dual-core lockstep (DCLS), which is logically simple but costs twice the area and twice the power; ASIL-B, for PPA considerations, mostly adopts STL software diagnostics, requiring 90% diagnostic coverage with a 10% to 20% area increase.

Three constraints he highlighted are worth noting: STL single-program-segment runtime must be kept within several thousand cycles to avoid lengthening interrupt response latency; automotive-grade storage is tight, limiting the richness of test cases; and access to Device-type IO devices may produce irreversible states, compressing the space for software diagnostics. A key development finding is that diagnostic coverage differs by more than 5% between RTL simulation and netlist simulation (reaching 7% to 10%), meaning the RTL stage must achieve 95% or even higher to meet the target at the netlist level. Li Weili called on more vendors to enrich ASIL-B/D grade MCU-level IP and to develop high-performance computing cores for intelligent driving.

2.3 Changan Automobile: RISC-V Cores Already Surpass ARM in MCU Compute; Exploring AI DSA Architecture with Custom Instruction Sets

Date: 2026-09-17 (conference 09-16)　Source: Gasgoo “Changan Automobile’s Ding Ke: Cockpit-Driving Integration and RISC-V Open Architecture Are Key to Breaking Through in Automotive Chips”

Ding Ke, Senior Deputy Chief Engineer of Chip Development at Changan Automobile, disclosed the OEM’s RISC-V evaluation conclusions: Changan conducted a detailed evaluation of RISC-V CPU cores as early as 2022, finding that their compute in the MCU domain already surpasses ARM, with real-time performance basically equivalent; based on a five-stage pipeline RISC-V architecture, interrupt response can reach the entry function within 120 clock cycles, with excellent power performance. Changan is also exploring an AI DSA architecture based on RISC-V custom instruction set extensions, balancing precision and cost through BF16 and INT8 mixed-precision acceleration, and has proposed goals of extending chip control down to the IP core level and participating in standard-setting with an open attitude.

On the chip demand side, Ding Ke’s assessment is that automotive chips are evolving toward high compute, high bandwidth, and high integration, with the future centered on a central brain of over 1000 TOPS AI compute plus high bandwidth; 7B models have already achieved in-vehicle deployment, and 30B models are being considered for vehicle installation under MOE architecture; the end-to-end route is iterating from Transformer+BEV toward VLM, VLA, and even world models. He noted that L3 to L4 intelligent driving involves more than 1,400 runnable processes, and traditional architectures are costly for solving redundancy and failure issues, making cockpit-driving integrated “one box” and cockpit-driving fusion trend directions.

2.4 SiFive and AMD’s ROCm Data Center Demonstration Reaches Mainstream Financial Media, AMD Up 7% That Day

Date: 2026-09-17　Source: EE Times Asia “SiFive, AMD Demonstrate ROCm AI Workloads on RISC-V Datacenter Platform”, Yahoo Finance “Advanced Micro Devices (AMD) Expands ROCm Support To RISC V Datacenter Servers”

The event in which SiFive and AMD demonstrated ROCm running AI workloads on a RISC-V data center platform at the Santa Clara AI Infra Summit entered mainstream financial media view near the end of the window: EE Times Asia did a technical-side recap titled “SiFive, AMD Demonstrate ROCm AI Workloads on RISC-V Datacenter Platform,” while Yahoo Finance wrote the matter into the investment narrative from the angle of “AMD Expands ROCm Support To RISC V Datacenter Servers,” with AMD shares rising about 7% that day amid a three-day rally in the semiconductor sector (24/7 Wall St. also recorded the gain and attributed it to data center AI expansion). The same event had already been analyzed by Futurum Group and HPCwire on 09-16 from the perspective of the “neutral head node” positioning; the marginal information this period is that the narrative has spread from industry media to the capital markets, which is of practical significance for the RISC-V data center route in seeking external resources. Boundaries to note: the demonstration remains a validation system with workstation-level GPUs and compact models, and the two companies said they will continue to evaluate ROCm optimization for larger models and more acceleration scenarios.

III. Deep Dive on Domestic Teams

3.1 DAMO XuanTie: damo-rv-priv-ats Refactors Hypervisor Test Suite Extension Support Gating

Date: 2026-09-17　Source: XUANTIE-RV/damo-rv-priv-ats commit history

The damo-rv-priv-ats repository under the DAMO XuanTie (T-Head) organization committed “Refactor on Hypervisor test suites update Extension support gate control” at 18:06 Beijing time on 09-17, refactoring the Hypervisor test suite and reworking the gating logic for extension support. This repository hosts RISC-V privileged-mode conformance tests, and its recent mainline has been continuously adding Hypervisor test cases: on 09-07 it added Hypervisor_Za* atomic extension tests, on 09-09 it wired the Za* atomic suite into the run_case_stats.sh statistics script, on 09-08 it added the Sail model to GitHub Actions, and on 09-14 it updated the Hypervisor test plan. This commit replaces scattered logic for determining extension support with unified gating — an engineering-quality improvement to the test framework.

No other repositories in the same organization saw pushes during the window. Examining the organization’s activity more closely: DAMO XuanTie currently has 73 public repositories, and only this test repository saw commits this period, with no new branches in the toolchain or kernel directions — consistent with its recent cadence of “focusing on automotive-grade and safety testing” (see the automotive functional safety report by Li Weili of the same company in section 2.2 of this issue).

3.2 SpacemiT: llama.cpp Merges SpacemiT Backend into the Multimodal mtmd Pipeline

Date: 2026-09-17　Source: spacemit-com/llama.cpp PR #39

The llama.cpp branch maintained by SpacemiT merged “Merge ggml-spacemit into mtmd-backend” at 11:44 Beijing time on 09-17, wiring its in-house ggml-spacemit backend into the mtmd (multimodal) backend pipeline. Previously, work on this branch centered on speech and media: on 08-15 it added the spert full-graph operator path, on 07-24 it added Qwen3-TTS support, on 07-20 it completed the mtmd media refactor, and between 08-24 and 09-15 it optimized around multi-ASR services, continuous batching, and thread parameter passing. This commit extends the backend from text/speech inference to the multimodal image input path, meaning the K3 platform’s backend coverage for on-device multimodal inference is further filled in.

3.3 SpacemiT: model-zoo-vision Adds a V2D Preprocessing Backend, K3 Clock Tree Docs Updated

Date: 2026-09-17　Source: spacemit-com/model-zoo-vision PR #82, spacemit-com/docs-chip PR #220

model-zoo-vision merged “feat(preprocess): add optional V2D backend” at 19:41 on 09-17, adding an optional V2D preprocessing backend to the vision model example library. Together with the RF-DETR COCO object detection model added on 09-11 and the MobileSAM prompt segmentation example from 09-09, this forms a continuous chain of reinforcement — the example library is expanding from classification/detection toward detection, segmentation, and multimodal semantic alignment. docs-chip updated the K3 clock tree diagram at 15:18 on 09-17 (PR #220), the second consecutive clock tree revision by number (the previous one was on 09-08); revisions on the documentation side to the K3 clock domain structure indicate that the chip’s public technical materials are still being refined. Separately, the ai-sdk repository synced its vision submodule at 19:43 on 09-17 (a submodule pointer update only, with no independent code changes).

3.4 Sophgo: ZSBL Releases SG2044 v3.1.0, sophon-demo Completes CV84X6 Rename

Date: 2026-09-17　Source: sophgo/zsbl commit history, sophgo/sophon-demo commit history

sophgo/zsbl committed “SG2044: v3.1.0 release” at 14:58 on 09-17, while also reworking the version logic and removing the platform version field. ZSBL is the second-stage bootloader for RISC-V platforms; this is the 3.1.0 release for the SG2044 server SoC, a component-level update that downstream distributions can adopt directly. Previously, between 09-07 and 09-08, this repository concentrated on fixing semaphore implementation and libc defects (sem_init ignoring the initial value, list_add_tail argument order, strncpy zero padding) and added a multithreaded stress test suite; this release can be seen as the wrap-up of that batch of fixes. On the sophon-demo side, at 16:38 on 09-17, BM1684X2 was renamed to CV84X6 and the DFSS MLIR wheel for that model was added — a unification of product-line naming and the landing of supporting tooling; the LLM-TPU repository saw no new commits during the window (most recently the Qwen3.5 text-only bmodel support on 09-15).

3.5 Sipeed: SLogic16U3 Flashing Toolchain Shares a CLI and Bundles libusb

Date: 2026-09-17　Source: sipeed/slogic16u3-tools commit history

Sipeed’s SLogic16U3 logic analyzer toolchain made two consecutive commits at 12:06 and 11:14 Beijing time on 09-17: configuring cable, flashing, and eFuse parameters by default in a shared programmer.toml, and having the CLI share the same flashing entry point as the graphical interface; at the same time, it made the libusb DLL vendorable so it can be bundled with the distribution package, resolving device recognition failures caused by missing dependencies on Windows. Previously, on 09-16, it had fixed the process defect whereby “flashing a blank chip requires writing and locking the eFuse first,” and corrected the error that .bin bitstreams should use run 54 rather than run 56. Overall, this toolchain is converging on packaging and default parameters around the Windows delivery experience.

3.6 Member Website Inspection: 391 Companies Completed, No Substantive Developments Confirmable as New Products or Fundraising

Date: 2026-09-17 inspection　Source: RISC-V International member company websites (391 companies, Premier 20 / Strategic 169 / Community 202)

This window completed an inspection of all 391 member company websites: 232 unchanged, 93 with body-text changes, and 66 failed to crawl. Most changes were homepage marketing carousels and news ticker updates (e.g., homepage body-text hash changes at SiFive, Phytium, Renesas, Infineon, NXP, Lattice, and others); after checking each one, no substantive developments confirmable as new product launches, fundraising, architecture releases, or partnerships were found, so no items are included from the member website channel in this issue. Crawl failures were mainly domestic sites and anti-scraping sites (Institute of Software, Chinese Academy of Sciences; Beijing Institute of Open Source Chip; Nuclei; Andes; Tencent; ADI; DENSO; etc.); failures do not block the inspection process. DAMO XuanTie, Espressif, Radxa Linkr, and ESWIN also had no pushes on the organization repository side during the window (ESWIN’s most recent push was 07-14, and Radxa Linkr’s trademark repository most recently released v1.4.2 on 09-03).

IV. Embodied Intelligence and Robotics Special Section

4.1 SpacemiT spacemit-robotics: Humanoid Common Library and LingLong Complete Periodic Motor Position Normalization

Date: 2026-09-17　Source: Whole-Body Control Library PR #5, LingLong Humanoid Repository PR #12

On 09-17, spacemit-robotics landed the same class of fix in both the whole-body control library and the LingLong humanoid repository on the same day: control_whole_body submitted “normalize periodic motor positions” (09-17 19:23), and humanoid_linglong submitted “configure periodic leg motor positions” (09-17 16:14). Both address the calibration issue of periodic motor positions—motor feedback positions near the wraparound boundary need normalization, otherwise joint angles will jump when crossing cycles, directly affecting motion control interpolation and safety threshold judgment. This kind of cross-repository synchronized fix indicates that the team has abstracted motor feedback handling into a common library, with specific robot model repositories only configuring parameters—a sign of layered convergence in motion control software. The earlier “preserve motor link dependencies” on 09-14 and “report per-motor command write failures” on 09-08 belong to the same mainline of safety hardening.

4.2 SpacemiT spacemit-robotics: ROS cmd_vel Human-Machine Interface Adds Configurable Velocity Biases

Date: 2026-09-17　Source: ROS Humanoid Repository Commit History

ros2_humanoid submitted “feat(humanoid): add configurable velocity biases to ROS cmd_vel HMI” on 09-17 14:29, adding configurable velocity biases to the ROS-side cmd_vel human-machine interaction node. The repository’s mainline since September has been connecting ROS 2 with the in-house motion control stack: starting 09-08 with publishing LingLong head TF transforms and clarifying coordinate system documentation, 09-08 supporting reception of ROS 2 velocity commands, and 09-16 migrating the HMI node to V2 transport. With the addition of velocity biases in this issue, upper-layer applications can make on-site fine adjustments to linear and angular velocities without modifying body parameters, facilitating debugging and adaptation to different ground conditions.

4.3 SpacemiT spacemit-robotics: IMU Peripheral Repository Builds All Available Drivers by Default

Date: 2026-09-17　Source: spacemit-robotics/peripherals-imu PR #18

peripherals-imu merged “fix(imu): build available drivers by default” on 09-17 17:45, changing available IMU drivers to be built by default. Previously, drivers in this repository required explicit selection; 08-10 added the Forsense UART driver, 08-20 corrected its body-frame attitude, and 09-09 exposed reception timing and parsing diagnostic information. After this issue’s adjustment of build defaults, developers can obtain drivers for all supported devices simply by pulling the repository, lowering the barrier to first integration. IMU is the entry point for state estimation in humanoid and quadruped motion control, and its driver completeness directly affects gait stability. The repository’s commits over the past month indicate the team is filling in device coverage and diagnostic capabilities.

4.4 SpacemiT spacemit-robotics: Unitree G1 Manual Reference Trajectory Playback and Constraint Documentation Merged

Date: 2026-09-17　Source: spacemit-robotics/humanoid_unitree_g1 PR #12

The humanoid_unitree_g1 repository merged “support manual reference playback” on 09-17 10:13, along with constraint documentation (“clarify manual playback constraints”). This repository targets adaptation for the Unitree G1 model, having previously added MjLab motion policies (08-31) and SONIC motion tracking policies (08-31), as well as safety hardening for the accompanying hardware runtime. This issue’s manual reference trajectory playback capability brings the reference playback mechanism introduced by the humanoid common library on 09-16 down to the specific G1 model and clarifies usage boundaries; combined with the “upper-body motion takeover” merged into LingLong and the common library on 09-16, spacemit-robotics is forming a three-stage implementation path for humanoid motion control: “common library capabilities—model configuration—constraint documentation.”

V. Summary and Trend Observations

  • A landmark event at the standards discourse level: Shanghai Jiao Tong University’s SPMP was merged into the RISC-V international instruction set standard—the first time a domestic team has initiated and fully led an ISA feature from scratch, and it has already been implemented in XiangShan and Nuclei IP. Echoing this issue’s launch of QC/T industry standard drafting on the automotive side, this indicates that China’s approach to RISC-V participation is shifting from “implementation and adaptation” to “definition and specification”—a more structural change than any single product release.
  • The RISC-V data center narrative has entered capital market view: The SiFive and AMD ROCm demonstration spread from industry media to financial channels such as Yahoo Finance, and was reflected in AMD’s stock price. Compared with the previous “release—third-party analysis” evolution path, the marginal change in this issue is that external capital has begun pricing the RISC-V host route, which will affect subsequent customer evaluation and supply chain investment pacing.
  • Automotive-grade is this issue’s densest landing point: Industry standard drafting launched (34 companies), DAMO Academy provided 3-to-5-year functional safety cycles and STL coverage quantification experience, and Changan disclosed that RISC-V cores exceed ARM in MCU compute power and is exploring custom instruction AI DSA. These three pieces of information correspond to three levels—specification, methodology, and full-system evaluation—jointly pointing to domestic automotive-side RISC-V moving from point validation toward systematic engineering.
  • Open-source software maintains small-step iteration: The XiangShan simulation chain (three GEM5 items, one difftest item), revyos kernel configuration and CI, and the pending openRuyi monthly release are all engineering-hardening progress; there are no new architecture-level releases in this issue, consistent with the rhythm observed in previous issues.
  • Domestic vendors’ engineering mainlines concentrate on “AI stack completion + motion control layering”: SpacemiT has continuously strengthened the llama.cpp multimodal backend and vision example library preprocessing backend, while spacemit-robotics uses the common library to carry motor feedback normalization and motion takeover, with model repositories only doing configuration—the motion control software layered architecture is already relatively clear; Sophgo is preparing for downstream integration through ZSBL 3.1.0 and product line renaming.
  • Limitations note: This issue’s data comes from public web pages and public GitHub commits, with no non-public channels used. The GitHub API hit the unauthenticated rate limit (60/hour) at the end of collection; some organizations’ (such as Espressif’s) commit details rely on cross-verification between organization push times and repository commit atomic sources, and commit contents were not expanded item by item. The RISC-V International Foundation membership website inspection had 66 fetch failures (mainly domestic sites and anti-scraping sites); dynamics from these sites were not included in this issue’s lead pool. The three automotive-side items originated from the 09-16 meeting and entered the window through aggregation channels on 09-17; the report has annotated the meeting date.
  • Next issue’s focus points: Whether the openRuyi 2026.09 release ships on schedule (including RVA23 and cloud-native/AI stack updates); whether subsequent batches from the XiangShan main repository after the vector floating-point refactoring will bring performance data; whether the DAMO XuanTie toolchain and kernel repositories resume pushing; real-device performance feedback on SpacemiT’s llama.cpp multimodal backend.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Hacker News Hit Ubuntu RVA23 follow-up evolution blog post, Epic Semi Contrail AIX platform page; the latter’s press release was published 09-01, not an in-window event, not included
Google News aggregation (Chinese and English) English side hit multiple SiFive/AMD ROCm reports; Chinese side hit three items on the automotive chip ecosystem conference, the SPMP standard report, deepin K3 adaptation (already covered in the previous issue); gambling and stock market noise removed by semantics
China Science and Technology Network / Science and Technology Daily Hit SPMP inclusion in international standard report (this issue’s highlight)
Ubuntu Official Blog Hit RVA23 follow-up evolution long-form article, including CFI, matrix extensions, and RVA23.1 details
GitHub organizations and key repositories In-window pushes: XUANTIE-RV 1 repo, sophgo 4 repos, spacemit-com 8 repos, spacemit-robotics 6 repos, sipeed 3 repos, revyos 2 repos, espressif 42 repos (mostly Xtensa platforms outside the ESP32-C series, not included as RISC-V), XiangShan family 5 repos; eswincomputing, Nuclei-Software, radxa-linkr no pushes
RISC-V International official website / member websites No new in-window entries on the official News page; 391 member websites swept (232 unchanged / 93 changed / 66 failed), no substantive developments found
openRuyi official website News page latest is still the 2026.08 release, September version not yet released
OSChina / RISC-V Developer Community In-window entries mainly consist of already-covered content, no new substantive developments