Research window: 2026-10-23 05:00 ~ 2026-10-26 05:00 (Beijing time, 72 hours; continuing from the previous daily report’s cutoff, covering the two weekend days).

Sources: Google News aggregation (22 supplementary queries in Chinese and English, via proxy), Hacker News, Phoronix, CNX Software, LinuxGizmos, riscv.org, the openRuyi official news page and main repository, website inspections of RISC-V International member companies (391 companies), and GitHub (pushes, commits, and release searches across organizations and key repositories including XiangShan/NEMU/difftest/GEM5/XSCache, DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT and spacemit-robotics, Sipeed, revyos, openRuyi-Project, Radxa Linkr, and OpenHW).

In This Issue

  • Today’s Highlights: Claude pushes formal verification down to RISC-V machine code, securing 180 million lines of proof across 123 open-source libraries (10-23)
  • I. Open-Source Community and Software Ecosystem
    • openRuyi: 20 commits, batch import of Go server-side software packages (10-23)
    • XiangShan: NEMU releases two tags in a row, difftest uses Tensor Cores to run MMA comparisons (10-23)
    • CVA6’s master becomes read-only, CVW merges Sail 0.16 (10-23)
  • II. Product and Ecosystem News
    • Tenstorrent opens beta of Chiplet design framework OCA Harness (10-23)
    • LILYGO T-Halow P4: an M.2 board with dual RISC-V cores, ESP32-P4 and C6 (10-23)
  • III. In-Depth on Domestic Teams
    • Youzhi Chuangxin raises nearly RMB 100 million in Pre-A funding; “Quanyingxin” RISC-V GPGPU lands in Changsha Jinxia (10-22)
    • Ewash Intelligence becomes a founding member of the RVAI working group; RISC-V supernode already live in a carrier data center (10-23)
    • UniVista: RISC-V’s “watershed” moment, domestic EDA must become an ecosystem co-builder (10-23)
    • Tan Zhangxi of Rivos Core: twenty to thirty high-performance RISC-V players will consolidate, ecosystem weight matters more than core performance (10-23)
    • Sophgo refactors zsbl into the eboot framework, supporting external device trees and application trees (10-23)
  • IV. Special Chapter on Embodied Intelligence and Robotics
    • SpacemiT open-sources an on-device Agent memory subsystem, BiBit releases a matching memory plugin (10-23)
    • The academic underpinnings of Ruixin Gaoguang D35: ISCA 2026 Best Paper nomination and over 80 dataflow patents (10-23)
  • V. Summary and Trend Observations

Today’s Focus: Claude Pushes Formal Verification Down to RISC-V Machine Code, Securing 180 Million Lines of Proof Across 123 Open-Source Libraries

Date: 2026-10-23　Sources: 36Kr: Claude Writes 180 Million Lines of Proof, Bugs Missed by Trillions of Tests Caught by AI in One Sweep (10-25), Tencent News (AI Era): Claude Writes 180 Million Lines of Proof (10-23), Sohu (DoNews): Claude Produces 180 Million Lines of Mathematical Proof (10-23)

Anthropic’s Frontier Red Team, in collaboration with Theorem Labs, released a report: Claude was tasked with formally verifying 123 open-source codebases and 239 test entry points from Google’s OSS-Fuzz corpus. The object of proof was not the source code, but the compiled RISC-V machine code that actually runs on the CPU.

  • Scale and cost: The project generated approximately 1 billion lines of proof in total, of which 180 million lines passed the Rocq proof checker; machine-checking a single proof takes from 30 minutes to several hours. For cJSON, a 391-line C parsing entry point, the accompanying proof reached 630,000 lines—because it must also prove process startup, the memory allocator, printf, and the runtime, with only about one-tenth directly related to the business logic.
  • Detection capability: The research team planted 7 bugs in a self-developed Rust-based Python interpreter; random testing missed 5, while formal verification caught all of them. Some vulnerabilities trigger only under rare inputs of about 20MB, paths that fuzzing struggles to cover.
  • Progress and cost: Theorem tested 7 frontier models released between May and September 2026, with verification speed roughly doubling every two months; at current unit prices, an investment of $134 million could cover 95% of the machine code in the Nix ecosystem by the end of 2027, amortizing to about $14 per downstream software package.
  • Spillover effects: To build a zlib control case, Claude autonomously wrote a mathematical model of the x86 instruction set, capable of single-stepping through Ubuntu user-space boot within the model, and in the process found hundreds of errors in the official x86 reference documentation plus a small number of CPU hardware defects. Proofs for the first batch of 25 libraries and 60 entry points have been open-sourced.

For RISC-V, the significance of this news lies in the level at which verification is performed. Previously, machine-code-level formal verification appeared only in projects like seL4 (2 person-years to encode, 20 person-years to verify), and the cost kept it out of ordinary open-source libraries; this time the unit cost has been pushed down to an amortizable level, and the entire proof suite is built on a mathematical model of the RISC-V instruction set and Linux process behavior written by Theorem—effectively leaving the RISC-V ecosystem a reusable semantic foundation. What calls for restraint: the proofs are currently limited to single-threaded, statically linked, fixed memory budget settings; the correspondence between the model and real hardware still requires manual review; and the checker only guarantees that the proof conforms to the specification, not that the specification meets the requirements.

I. Open-Source Community and Software Ecosystem

1.1 openRuyi: 20 commits, batch import of Go server-side packages

Date: 2026-10-23　Source: openRuyi main repo commit log (10-23), openRuyi official news page

The openRuyi main repo recorded 20 commits in the window, all in the SPECS directory, and all of them adding Go language packages.

  • Web framework dependency chain: added the gobuffalo family — packr, packd, logger, envy — plus emicklei’s go-restful; this is the most common routing and packaging combination for Go server-side work.
  • Container and database drivers: docker’s libtrust and spdystream, gopkg’s gorp v1, ziutek’s mymysql, denisenkom’s go-mssqldb, jaypipes’s pcidb, howett’s plist, and golang-sql’s civil.
  • Connection to prior context: the 2026.09 release had just bumped the Go build environment to 1.27, so this batch of packages effectively moves “toolchain is usable” forward to “application dependencies are complete”; the latest announcement on the official news page is still the 2026.09 release, with no new version in the window.

These 20 commits point to one thing: among the server-side workloads a RISC-V distribution must support, Go-written cloud-native components account for a very high share, and the pain point of the Go ecosystem has never been the compiler — it is those third-party packages nobody builds for you. Adding mysql and mssql drivers and docker low-level libraries one by one is classic “no release, but determines usability” work.

1.2 XiangShan: NEMU ships two tags in a row, difftest runs MMA comparison on Tensor Cores

Date: 2026-10-23　Source: NEMU release log (10-23, 10-24), difftest commit log (10-23 to 10-25), XiangShan commit log (10-23)

The XiangShan project advanced three lines simultaneously in the window: the reference model, the differential verification framework, and the processor core itself.

  • NEMU: released two tags back to back on 10-23 and 10-24, v2026.10.r8 and v2026.10.r9, alongside a change for “difftest support for fast shared reference execution” (#1247), and removed the Copilot review workflow from CI (#1260).
  • difftest: 9 commits in the window, 6 of them focused on CUDA performance optimization for MMA verification — format-specialized floating-point kernels (#1000), running INT8 comparison on Tensor Cores (#1001), switching to native-bit-width operand loads (#1002), and removing redundant operand and DUT result copies (#996, #999); plus fast reference and fork checks (#980), hashing for concurrent register writes (#991), and documenting BOOM’s DiffTest integration (#995).
  • Processor core: 3 commits on the Kunminghu V3 branch, including a fix for the address reported by StoreUnit after pointer masking (#6742), a checkpoint update (#6756), and CI unification of simulation environment variables (#6701).

The real change is in difftest: moving the matrix extension’s reference model onto the GPU to run on Tensor Cores shows that the bottleneck in differential verification has shifted from “the model can’t be written” to “comparison throughput is insufficient.” Once verification infrastructure starts being optimized for performance, it usually means the core under verification has grown complex enough that cycle-by-cycle simulation can no longer keep up.

1.3 CVA6 master goes read-only, CVW merges Sail 0.16

Date: 2026-10-23　Source: cva6 commit log (10-23), cvw commit log (10-23)

OpenHW’s two core projects each had one governance- or model-level change in the window.

  • CVA6: commit #3664 was merged into the master branch, titled “Note: master made read-only.” The previous code commit on that branch dates to 09-15, with no functional changes for a month since; this change directly marks it read-only, and the default branch name has not yet been switched.
  • CVW: merged PR #1995, upgrading the Sail model to 0.16. CVW uses Sail to maintain the RISC-V golden reference model, and following the version means the reference implementation of instruction semantics stays in sync with the upstream specification.

Taken together, these are two moves in the same direction: one freezes the mainline to make room for a branch-strategy adjustment (the migration plan has not yet been announced), while the other pushes the ISA reference model forward. For teams using CVA6, the near-term task is to confirm where the code baseline is moving; for teams doing formal and differential verification, Sail 0.16 is an update more worth following than the core itself.

II. Product and Ecosystem Updates

2.1 Tenstorrent Opens Beta of Chiplet Design Framework OCA Harness

Date: 2026-10-23　Source: Unite.AI: Tenstorrent Opens OCA Chiplet Harness Beta Under Apache 2.0 (10-23), GitHub: tenstorrent/tt-oca-harness

On 10-22, Tenstorrent released the open-source beta of the Open Chiplet Atlas (OCA) Harness, turning OCA’s interoperability architecture into a reusable, deployable implementation.

  • License: Code under Apache 2.0, documentation and images under CC-BY-4.0, contributions also accepted under Apache 2.0; the official release is targeted for January 2027.
  • Three-layer structure: Architecture defines chiplet interoperability across five layers—physical, transport, protocol, system, and software; Harness provides all the “non-application logic” a chiplet requires, so designers only write their own value-added portion; Compliance handles pre-silicon verification and post-silicon validation, including the Golden Chiplet concept and community plugfests.
  • Positioning: The beta targets early adopters, integrators, and contributors; the repository is already public under the tenstorrent organization.

Tenstorrent is one of the few vendors in the RISC-V camp to extend “openness” from the instruction set to packaging and interconnect. The real obstacle to chiplets has never been feasibility, but that each vendor’s die-to-die interface refuses to recognize the others’. Turning non-application logic into an open-source scaffold essentially shifts interoperability costs from each design team onto the community. For domestic teams working on multi-die solutions, this is a reference implementation they can directly benchmark against.

2.2 LILYGO T-Halow P4: An M.2 Board with Dual RISC-V Cores, ESP32-P4 and C6

Date: 2026-10-23　Source: CNX Software: LILYGO T-Halow P4 (10-23), GitHub: Xinyuan-LilyGO/T-Halow-P4

LILYGO has launched the T-Halow P4: an 80 × 22mm M.2 2280 development board that packs a Wi-Fi HaLow long-range link into the standard M.2 form factor.

  • Main controller: Espressif ESP32-P4NRW32X, dual-core RISC-V at 400MHz (with AI instruction extensions and a single-precision FPU) plus a 40MHz low-power RISC-V core; 2D PPA, H.264 and JPEG codecs, one MIPI CSI and one DSI lane each, with hardware encoding up to 1080p30.
  • Wireless: ESP32-C6-MINI-1U provides Wi-Fi 6, Bluetooth 5, and 802.15.4 (Zigbee/Thread/Matter), connected to the P4 via SDIO; a Taixin TX-AH module handles 802.11ah HaLow, with two frequency bands (859–894MHz or 902–928MHz), 1–8MHz channels, 150Kbps to 32.5Mbps, and up to 1.2km line-of-sight.
  • Pricing and development: Starting at $26.57 on the official store ($31.07 for the 915MHz version), $36.98 on AliExpress; examples are based on ESP-IDF 5.4.1 or later, with HaLow transferring data over SPI and receiving AT commands over UART, plus a browser-based configuration tool.

The M.2 form factor is the board’s most practical aspect: it is no longer “a development board that needs wiring” but a communication module that plugs into an off-the-shelf carrier board. The ESP32-P4 adds compute and a video path, the C6 adds Wi-Fi 6 and Matter, and the TX-AH adds a kilometer-range low-power link—three chips with clear division of labor, precisely matching the two hardest-to-wire scenarios: industrial monitoring and remote cameras.

III. In-depth Look at Domestic Teams

3.1 Youzhi Chuangxin Completes Nearly RMB 100 Million Pre-A Round; “Quanyingxin” RISC-V GPGPU Project Lands in Changsha Jinxia

Date: 2026-10-22　Source: Zhangshang Changsha (Changsha Evening News): Why Did a “Chip” Choose Changsha? (10-22)

Changsha Evening News reported on October 22 that Tsinghua-affiliated neuromorphic intelligence company Changsha Youzhi Chuangxin Technology Co., Ltd. has completed a nearly RMB 100 million Pre-A round, led by Liyou Chuangtou, a special fund formed by Lihui Fund together with Changsha Investment Holding Group and Jinxia Shengshi Fund, with existing shareholder Qifu Capital following on; the company has also landed its incubated “Quanyingxin” RISC-V GPGPU project in the Changsha Jinxia Economic Development Zone.

  • Technology origin: Youzhi Chuangxin is led by He Hu, associate professor at Tsinghua University’s School of Integrated Circuits, and holds the SNNGrow neuromorphic simulation training framework and the CLAS causal learning algorithm; the technical origin of “Quanyingxin” can be traced back to “Ventus”, China’s first open-source RISC-V vector-extension GPGPU, launched in 2022 by the integrated circuit research platform of the Shanghai Tsinghua International Innovation Center, with a route of triple autonomy in instruction set, architecture, and ecosystem.
  • Industrialization milestones: In June 2025, the Youzhi Chuangxin project with total investment of about RMB 1.5 billion was signed and settled in Jinxia, building a headquarters and GPGPU R&D and production base in three phases, focusing on the “Quanyingxin” series GPGPU and the “Sibianxin” neuromorphic AI chip; after the first phase goes into production, annual output value is expected to exceed RMB 300 million; in November 2025, Changsha Quanying Semiconductor was registered and established, and at the same time the “Changsha High Performance Computing Research Center (under preparation)”, jointly initiated by eight entities including Tsinghua University, Jingjia Micro, Quanying Semiconductor, and CSDN, was signed and settled.
  • Operator library co-building: At the “AI+OpenCL Heterogeneous Computing” forum of the 2026 Yuelu Conference, Changsha Quanying Semiconductor, the Hunan Integrated Circuit Industry Technology Innovation Strategic Alliance, CSDN, Changsha Jingjia Micro, and Changsha Shouzhao Technology signed a strategic cooperation agreement on an OpenCL operator library, aiming to eliminate the ecosystem fragmentation of operator adaptation and make it possible for “one set of code to run across domestic chips”; the subsidiary is simultaneously promoting the rooting of the “OpenKusuan” AI software stack platform in Changsha.
  • Changsha’s computing foundation: The National Supercomputing Center in Changsha has total computing power exceeding 5000 PFlops, and World Computing · Changsha Zhigu has deployed 200P of full-stack domestically produced computing power; in 2025, Hunan province’s total computing power was 13500P, intelligent computing power 5200P, and the AI industry scale RMB 85 billion, with the autonomous and secure computing cluster comprising more than 1400 enterprises and total cluster output value exceeding RMB 230 billion.

This is a domestic implementation sample of RISC-V extending into high-performance computing (GPGPU): starting from an open-source vector-extension GPGPU, to an industrialization entity, and then to open co-building at the operator library level, it fills precisely the “strong hardware, weak software” gap. GPGPU on RISC-V means building a complete parallel programming stack from scratch; whether the OpenCL operator library co-building can produce genuinely reusable code is the most worthwhile metric to track going forward; the timing of chip tape-out and silicon return and of the first-phase production line also remains to be clarified.

3.2 Eswin Smart Becomes One of the First Initiating Units of the RVAI Working Group; RISC-V Super Node Already Online in an Operator’s Data Center

Date: 2026-10-23　Source: Jiwei: Intelligent Computing Toward the New, Open Source Casting Roots—Eswin Smart Appears at the 2026 RISC-V China Summit and Xiangshan Ruyi Ecosystem Conference (10-23), C114: Eswin Smart Appears at the Summit (10-23), EqualOcean: Eswin Smart Secures Another RMB 2 Billion in Financing (09-18)

On the afternoon of October 20, the Xiangshan Ruyi Ecosystem Conference was held in Shenzhen as a side event of the RISC-V China Summit, where Eswin Smart took on two roles: one of the eight first initiating units of the open-source chip community RVAI Working Group, and a co-building unit of the Ruyi community.

  • Organizational positioning: The RVAI Working Group focuses on the integration of RISC-V and AI, pooling chip, IP, and software ecosystem forces through open-source collaboration; the Ruyi community is led by the Institute of Software of the Chinese Academy of Sciences, targeting a RISC-V native basic software ecosystem. Eswin Smart says it will participate in upstream co-building with real product requirements and engineering experience.
  • Technical stance: The keynote “Eswin Smart’s RISC-V AI Innovation Practice from an AI System Perspective” was delivered by Huang Chao, with the core judgment that Agentic AI expands the measurement of computing value from a single model invocation to the complete task chain, so chips, interconnect, software, and systems must be co-designed around end-to-end task efficiency.
  • Product foundation: The first-generation Epoch series RISC-V cloud AI chips have entered volume production, based on RISC-V and a TPU-like architecture with native support for block-wise quantized FP8; a 64-node E200-L liquid-cooled OAM super node cluster has been brought online in an operator’s data center, which the company calls the industry’s first RISC-V super node delivered in volume, achieving hundred-nanosecond-level interconnect across 64 chips for expert routing coordination in MoE models.
  • Capital and ecosystem: In the first half of 2026 it completed a RMB 1.5 billion B round and received strategic investment from China Mobile, and in September secured another nearly RMB 2 billion, bringing post-money valuation to close to RMB 15 billion; on the software side it is advancing open-sourcing of the VISA virtual instruction set, and the EVACA software stack has been adapted with domestic AI ecosystems such as FlagOS.

Eswin Smart follows the sequence of “chip volume production—super node delivery—open-source community co-building,” the opposite of most RISC-V companies that do IP first and look for scenarios later. This is also the significance of its joining the Ruyi community: the weakness of RISC-V cloud AI lies not in the instruction set but in upper-layer frameworks and operators, and a willingness to feed the pitfalls encountered on production machines back upstream says more about this stack moving toward production environments than another round of financing would.

3.3 UniVista: RISC-V’s “Watershed” Moment, Domestic EDA Must Be an Ecosystem Co-builder

Date: 2026-10-23　Source: SEMI Semiconductor Industry Network: UniVista’s Wu Xiaozhong—RISC-V’s “Watershed” Moment (10-23)

Semiconductor Manufacturing interviewed UniVista vice president Wu Xiaozhong, with the core question being what role domestic EDA plays in the RISC-V ecosystem.

  • Difference from the Arm era: The Arm era was “architecture standardized first, tool adaptation afterward,” with EDA tuning based on a fixed core baseline; the RISC-V era has become a “symbiotic model in which architecture, IP, and tools grow in parallel,” with EDA deeply involved in architecture iteration and working with IP vendors and open-source organizations to solve fragmentation and multi-core heterogeneous challenges.
  • Projects already invested in: In the real R&D projects of Xiangshan Kunminghu and the XuanTie C900 series, it has invested simulation, hardware emulation, and hybrid emulation capabilities, turning industry pain points into tool capabilities, and jointly released standardized verification solutions with partners.
  • Judgment on RVA23: The value of RVA23 is to give operating systems, compilers, and application developers a stable instruction set baseline, but it only addresses consistency of the “software-visible instruction set,” does not constrain microarchitecture, does not cover firmware, boot flow, and interrupt architecture, and does not prohibit custom extensions—fragmentation will not disappear because of it.
  • The real difficulty of verification: RISC-V is not inherently more complex than Arm/x86, but its high modularity and allowance for custom extensions greatly expand the configuration combinations that need verification and maintenance; the challenge is not inventing new methodologies but the workload of configuration management and hardware-software co-design. UniVista lists four directions: hardware verification platform performance and cascading, memory consistency and vector/AI acceleration verification, pre-silicon system verification environments, and FPGA-based runnable reference solutions.

What is worth noting in this interview is not the statements but the fact it acknowledges: the cost center of RISC-V is shifting from “design” to “verification.” When an EDA company appears in the verification chains of both flagship projects, Xiangshan and XuanTie, it shows that the iteration pace of domestic high-performance cores is already constrained by the throughput of the toolchain; and the line “using tool capabilities to constrain disorderly customization” also points to the real lever of ecosystem governance.

3.4 Ruisixin’s Tan Zhangxi: Twenty to Thirty High-Performance RISC-V Players Will Consolidate; Ecosystem Weight Exceeds Core Performance

Date: 2026-10-23　Source: 21st Century Business Herald: Interview with Tan Zhangxi—RISC-V Moves Toward Large-Scale Commercialization, the Next Hard Battle Is in the Data Center (10-23)

Summit chair and Ruisixin founder and CEO Tan Zhangxi gave an interview to 21st Century Business Herald after the event, offering several judgments on the industry stage.

  • Identity and background: Tan Zhangxi studied under RISC-V founder David Patterson and is the only mainland Chinese student in the original Berkeley team; Ruisixin focuses on high-performance server CPUs and AI data center processors, and the company just completed a strategic financing round on 10-16.
  • Competitive logic: Processor competition is not about “how fast the core is”; end users care about whether applications and the entire software stack can run on the new architecture and whether porting is smooth, so ecosystem building matters even more than the pursuit of core performance; the rise of AI programming over the past two years is helping RISC-V accelerate replacement of existing architectures.
  • Consolidation forecast: There are currently about twenty to thirty companies claiming to do high-performance RISC-V, but few truly have self-developed cores and can complete a full product cycle; he draws an analogy to the twenty to thirty GPU companies in Silicon Valley that ultimately left only two or three, and believes the Chinese market is entering the same stage, with the ability to survive the AI bubble and correction determining the ultimate winners.
  • Where the gaps are: Supply chain security and AI computing demand are clear industry drivers, but the gap in talent and fundamentals remains large, and international giants’ current position rests on decades of accumulation. The seventh summit received 239 submissions, up nearly 20% year on year, with more than thirty sponsors, all of which have direct RISC-V products.

Read alongside the UniVista item, this shows two sides of the same thing: one says verification and tools determine iteration speed, the other says ecosystem and porting determine commercial success—both move “core performance” away from the center of competition. For chip teams, this means the window for route selection is narrowing: either drive the software stack all the way through in some scenario, or be acquired in the consolidation.

3.5 Sophgo’s zsbl Refactored into the eboot Framework, Supporting External Device Trees and Application Trees

Date: 2026-10-23　Source: sophgo/zsbl commit history (10-23)

Sophgo’s zero-stage bootloader repository zsbl recorded 8 commits in the window, the actual content of which was a framework-level refactor.

  • Renaming and positioning: zsbl references in comments and test strings were cleaned up, the framework was renamed eboot, and image names are now derived from application names—moving from “a zero-stage boot for a specific chip” to “a boot framework that can host multiple applications.”
  • External tree support: Added support for out-of-tree application trees, with external tree objects output to objtree/ext; added a path to build external device trees with dtb rules, and made dts and defconfig named according to the actual build target.
  • Engineering fixes: Fixed the issue of image files remaining after distclean, and replaced the TARGET comment with a neutral example.

A bootloader rename looks like a small matter, but what it actually affects is downstream reuse cost. With support for out-of-tree application trees and external device trees, third-party boards and different product lines on the same chip no longer need to modify the main repository but can each carry their own configuration; compared with solutions that still hard-code board-level configuration in the bootloader, this is an engineering threshold that must be crossed in the volume production stage.

IV. Special Chapter on Embodied Intelligence and Robotics

4.1 SpacemiT Open-Sources On-Device Agent Memory Subsystem; BiBit Releases Matching Memory Plugin

Date: 2026-10-23　Source: GitHub: spacemit-com/bianbu-agent-memory, GitHub: spacemit-com/bibit-memory-plugin

SpacemiT pushed two new repositories related to Bianbu Agent OS within the window, turning “Agent memory” into an independent subsystem.

  • Main repository: bianbu-agent-memory is the memory subsystem of Bianbu Agent OS — a Rust workspace plus a Python SDK, Apache-2.0, with debian packaging. The README summarizes it as “three drawers”: basic storage, full-text search, and optional vector recall / model summarization; the basic capabilities do not depend on model services, and authoritative data stays local on the device.
  • Interfaces and boundaries: It exposes four tool categories — memory_search, memory_save, memory_update, memory_remove; updates use memory_id plus expected_revision for optimistic concurrency control, with stale versions rejected outright; deletion requires a preview first, then user confirmation before execution. On security design, recalled content is injected as untrusted context, messages from plugin sources are not written into memory, and sub-agents are read-only.
  • Hosts and plugins: The README names supported hosts including Hermes, DeepSeek Harness, and BiBit; the bibit-memory-plugin pushed in the same period is a BiBit feature plugin that adds a “Memory” page in settings, handling toggles, retention duration, session clearing, full wipe, and JSON import/export, invoking the memory subsystem through the service:memory capability.

The competitive focus for on-device AI terminals is shifting from “can it run a model” to “can it remember, and can it be trusted.” The two most noteworthy points in this design: memory lands locally on the device by default rather than in the cloud, and write permissions are isolated for sub-agents and plugin sources. For long-running, multi-user devices like robots, the memory permission model becomes a product constraint earlier than capacity does.

4.2 The Academic Pedigree Behind Ruixin’s Gaoguang D35: ISCA 2026 Best Paper Nomination and 80-Plus Dataflow Patents (10-23)

Date: 2026-10-23　Source: Shanghai Securities News (Sina Finance): Ruixin Showcases Gaoguang D35 Chip at 2026 Physical AI and World Models Conference (10-23), Phoenix Net: Ruixin Showcases Gaoguang D35 (10-23)

The 10-21 daily already covered Suzhou Ruixin’s Gaoguang D35 exhibit at the RISC-V China Summit; this issue adds its industry-side progress at the “2026 Physical AI and World Models Conference” in Nanjing from 10-20 to 22.

  • Technical path: The dataflow architecture makes computation happen where data arrives, avoiding instruction scheduling and repeated data movement; the company says this bypasses the “memory wall” at the root, with energy efficiency several times higher than comparable competitors. At the instruction set level it uses fully in-house RISC-V CPU core IP, forming a full-stack route of “instruction set autonomy plus architectural innovation.”
  • Academia and patents: The team has accumulated more than 20 years in the dataflow direction, holds 80-plus dataflow architecture technology patents, and its core research received a Best Paper Nomination at ISCA 2026, a top international computer architecture conference; team lead Fan Dongrui previously participated in the architecture design of Godson-1 through Godson-3 and led development of Godson-X and the 64-core Godson-T.
  • Deployment and operations: Gaoguang D35 has been deployed in embodied intelligence, video intelligence, smart campuses, cockpit-driving integration, satellites, and communications, and reached break-even in 2025; on-site customers focused on hard metrics such as energy efficiency, latency, compute density, power consumption, and software stack compatibility.
  • Caveats on claims: “Core IP recognized through Intel global procurement” and “world’s first mass-produced RISC-V dataflow physical AI chip” are both company claims without third-party confirmation; this conference focused on matchmaking and sample evaluation, with no new shipment figures announced.

This fills in an easily overlooked dimension: the dataflow architecture is not a new concept in China, but bringing it to mass production and being willing to submit it to peer review at a top conference is another matter. Physical AI scenarios’ demands for real-time performance and on-device deployment happen to amplify the advantage window of dataflow over von Neumann architectures; the real test remains the software stack — whether operators and frameworks can keep up determines whether this chip exists only on a showroom floor or in customer racks.

V. Summary and Trend Observations

  • The barrier to formal verification is falling, and RISC-V is among the first beneficiaries: Proofs are done directly on RISC-V machine code, and the accompanying RISC-V instruction and process behavior models are reusable; once unit costs are compressed enough to be amortized, the economics of security certification and high-assurance software may finally work. The caveat is that current work is still limited to single-threaded, statically linked code with fixed memory budgets.
  • Distro gap-filling is shifting from “language runtimes” to “application dependencies”: All 20 openRuyi commits this issue are Go packages, dovetailing with the 2026.09 release raising the Go build environment to 1.27. Whether RISC-V servers can handle real business workloads increasingly depends on this kind of unversioned packaging work.
  • Verification infrastructure is starting to optimize for throughput: XiangShan difftest saw 6 MMA/CUDA optimizations in one week, moving reference models onto Tensor Cores. Differential verification is moving from “can compare” to “compares fast,” indicating the cores under verification are already too complex for cycle-by-cycle simulation.
  • Open-source cores are entering a governance adjustment period: CVA6 freezes master and CVW follows with Sail 0.16 — one is a leading move in branch strategy migration, the other a version sync of the ISA reference model; both point to the common goal of “verifiability.”
  • Both expansion paths of domestic teams have reached the “ecosystem” stage: ESWIN is chip mass production, supernode delivery, then co-building the Ruyi community; Youzhi Chuangxin is financing, deployment, then co-building an OpenCL operator library. Hardware is only the entry ticket — software and community are where they are truly placing their bets.
  • On-device software gap-filling is denser than compute: SpacemiT had no new chip this issue but open-sourced an Agent memory subsystem and matching plugin, making memory, permissions, and tool invocation product boundaries. For embodied intelligence devices, this kind of “invisible middleware” becomes a constraint earlier than peak compute.
  • Limitations note: Content on Anthropic and Theorem Labs is relayed via secondary reporting by 36Kr and Xinzhiyuan; the full original reports were not obtained, and the scale of x86 documentation errors and CPU hardware defects are the reporting parties’ claims; the Youzhi Chuangxin item comes from a user-specified queue and Changsha Evening News reporting, with funding amount, output value, and compute figures being the reporting parties’ claims; ESWIN’s “industry-first mass-produced and delivered RISC-V supernode” and “post-investment valuation near RMB 15 billion” are company and media claims without financial-report corroboration; content on UniVista and Ruisi Core is interviewee opinion in media interviews and does not represent industry consensus; no project announcement was seen for the specific migration plan after CVA6 froze master, and this issue states only what the commit titles say; commit content for openRuyi, Sophgo, and SpacemiT is judged from commit titles and READMEs without patch-by-patch verification; the 45 changes detected in the member website sweep are all routine homepage updates by universities, institutions, and vendors, with no substantive product, funding, or architecture releases found; the RoboParty RP1 humanoid robot reported by CNX was verified to use RK3588, A733, and Jetson Orin NX and is not a RISC-V solution, so it has been excluded.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Google News aggregation (22 supplementary queries in Chinese and English, 72-hour window) About 90 items after deduplication: 10-23 was a dense day of post-summit coverage (XuanTie 6 billion units, Eswin IPO, V100, Ruixin D35, Zhongke Tongliang, Akeana acquisition, etc.), with a marked decline from 10-24 to 10-25; events already covered in the previous three issues were used only for background verification and are not repeated in this issue; Chinese queries for “Sophgo” and “Eswin” still mixed in stock market updates and lock-up release articles, which were excluded by title
Hacker News, Phoronix, CNX Software, LinuxGizmos, riscv.org Two valid items from CNX: LILYGO T-Halow P4 included; RoboParty RP1 verified to use RK3588, A733, and Jetson Orin NX, a non-RISC-V solution, excluded; no new RISC-V entries from Phoronix, LinuxGizmos, or riscv.org within the window
GitHub organizations and key repositories check (72-hour window) Pushes within the window: espressif 31, sipeed 8, spacemit-com 7, sophgo 2, Nuclei-Software 2, openhwfoundation 2, XUANTIE-RV 1, spacemit-robotics 1, openRuyi-Project 1; eswincomputing (last push 10-19), revyos (10-21), radxa-linkr (10-21) had no pushes within the window. XiangShan-family projects XiangShan, NEMU, difftest, GEM5, and XSCache all had activity and were included as entries
openRuyi dual-source 20 commits in the main repo, all Go package additions; the latest announcement on the official website news page remains the 2026.09 version, with no new release within the window
DAMO XuanTie, Sophgo, SpacemiT key repositories CubeSandbox’s default branch is add_riscv_support; no new commits on the default branch within the window, only CI binary asset images released on 10-23; zsbl 8 commits (framework renamed eboot), first pushes of bianbu-agent-memory and bibit-memory-plugin, 1 ai-sdk submodule update, 1 model-zoo-tts documentation fix
Member website inspection (391 sites) Took 190 seconds: 277 unchanged, 45 with page content changes, 69 failed to crawl; changed items were routine updates to university, institution, and vendor homepages (SC26 exhibition notices from Google, Samsung, MIT, Inspire Semiconductor, etc.), with no substantive product, funding, or architecture announcements detected
RISC-V International member list 391 members (Premier 20 / Strategic 169 / Community 202); the list is refreshed by an automated task on the 5th of each month, not due this issue
6th RISC-V China Summit official website The main summit (10-18 to 20) and Bay Area/Hong Kong Day (10-21) have concluded; the website change monitoring window has expired, and this will no longer be listed separately from this issue
Pending inclusion queue 1 user-specified item (Youzhi Chuangxin / Quanyingxin RISC-V GPGPU), included in Chapter 3 per the suggested section and archived