Research window: Past 3 days (2026-09-11 08:18 ~ 2026-09-14 08:18, Beijing time; Monday window covers Saturday and Sunday) Sources: Hacker News, Google News aggregation, CNX Software / LinuxGizmos / Phoronix / RISC-V International RSS, ServeTheHome, Tom’s Hardware, China Daily, Shanghai Jiao Tong University official website, Phoenix Finance, East Money, and GitHub API (pushes and commit searches for organization repositories including XiangShan, CVA6, SpacemiT, Sophgo, Nuclei, Sipeed, DAMO XuanTie, etc.) (see appendix source verification table for details)

Index

  • Today’s Highlights: RISC-V Open Computing Forum agenda released — IC WORLD conference sets up “Embodied Intelligence · Large Models · Data Centers” track, to be held in Beijing on September 18 (user queue specified)
  • I. Open Source Community and Software Ecosystem
    • XiangShan: RVV vector division instructions merged, Smmtt extension decoding reopened, multiple Bpu/FMA/CSR fixes (09-11 ~ 09-13)
    • CVA6: Eight commits within the window, PMP and trigger rules, Zcmp IDLE gating, xRET fixes landed in a concentrated batch (09-11 ~ 09-13)
    • openRuyi: No new version within the window, September release page does not exist, latest official version remains 2026.08
  • II. Product and Ecosystem Updates
    • 2026 IICIE International Integrated Circuit Innovation Expo concluded in Shenzhen: featured RISC-V Industry Ecosystem Innovation Conference and ecosystem application showcase area (09-12)
    • Infineon discusses RISC-V automotive at Hot Chips 2026: next-generation automotive-grade MCUs take the RISC-V route, the decisive factor lies in automotive-grade toolchains (09-13)
    • Espressif ESP32-P4 runs “Tomb Raider”: dual-core 400 MHz RISC-V software rendering at 30 FPS, on a $25-class development board (09-13)
  • III. Domestic Team Updates and Deep Dives
    • Shanghai Jiao Tong University SPMP standard follow-up: SJTU official website publishes in-depth article, confirms deployment on XiangShan and Nuclei chips (09-11)
    • Nuclei IPO follow-up: Ninety percent of revenue comes from RISC-V IP licensing, China Merchants Securities as advisor, H1 revenue up 41% but not yet profitable (09-12 ~ 09-13)
    • Sophgo SG2044: UEFI firmware adjusts boot entry ordering, sophgo-edk2 follows suit (09-11)
    • SpacemiT: Vision model library adds RF-DETR object detection, SigLIP2 defaults to in-house execution backend (09-11)
    • Sipeed: NanoKVM-Pro adds web display policy control, wiki adds NanoKVM Go two-factor authentication guide (09-11)
  • IV. Embodied Intelligence and Robotics Special Section
    • SpacemiT spacemit-robotics: MuJoCo simulation adds headless mode, robot simulation moves toward CI (09-11)
    • Kaihong M-Robots OS 3.0 Beta: Robot operating system digital foundation adapts to ARM/RISC-V/LoongArch/x86 four architectures (released 08-28, media reposted 09-13)
  • V. Summary and Trend Observations

Today’s Highlight: RISC-V Open Computing Forum Agenda Released — IC WORLD Conference Sets Up “Embodied Intelligence · Large Models · Data Centers” Track, Held September 18 in Beijing

Date: Early September 2026 (agenda release)　Source: Official WeChat account of the Beijing RISC-V Digital Infrastructure Innovation Center, “RISC-V Open Computing Forum Agenda Released”

The 2026 Beijing Microelectronics International Symposium and IC WORLD Conference will be held from September 16 to 18 at the Beiren Yichuang International Convention and Exhibition Center in Beijing Economic-Technological Development Area, under the theme “Harnessing Intelligence to Forge the Chip Path, Strengthening the Core to Write a New Chapter.” Among the events, the “RISC-V Open Computing Forum: Embodied Intelligence · Large Models · Data Centers,” hosted by the Beijing RISC-V Digital Infrastructure Innovation Center, is Special Forum Eight of the conference and will take place on September 18 (Friday) from 09:00 to 11:50 in Meeting Room S201A, Second Floor, Conference Center (South). The forum is organized by the Beijing Integrated Circuit Society and the RDI Alliance, and hosted by the Beijing RISC-V Digital Infrastructure Innovation Center, with moderator Liu Weiwei (Chairman of the Beijing RISC-V Digital Infrastructure Innovation Center).

The agenda features eight talks spanning three main threads: RISC-V AI computing power, data centers, industry scenarios, and ecosystem development: Liu Shuai (Vice President and Chief Marketing Officer, Beijing ESWIN Computing) — “Transcendence and Reshaping: RISC-V Redefines AI Computing”; Lu Gang (Deputy Director, Cloud-Network Integration Technology Research Institute, China Telecom Research Institute) — “Development of the RISC-V AI Computing Power System and China Telecom’s Innovative Practices”; Xi Honghai (CTO, Wuhan Yuanshi Intelligent Computing) — “Breaking Through with an Open Architecture: RISC-V Enters a New Journey in Data Centers”; Liu Huanbin (Technical Director, Qingdao Guoshi Information Technology) — “Trusted Data, Autonomous Computing Power — RISC-V AI + Security Foundation in Marine Data Element Scenarios”; Wang Wenzhu (Member of the Technical Committee, openKylin Community) — “Ecosystem Development and Technological Innovation: openKylin Empowers the RISC-V Computing Ecosystem”; Zhang Lei (Director of the Computing Platform Department, Beijing Lirui Microelectronics) — “Open · Integrated · Efficient: Building a RISC-V Intelligent Computing Industry Ecosystem Together”; Kang Xiaoxiao (Vice President of RISC-V Products, Beijing Sophgo Technology) — “Embracing a New Era of Open Computing — Industrial Application Practices of High-Performance RISC-V”; Chen Jingwei (General Manager, Beijing RISC-V Digital Infrastructure Innovation Center) — “Toward Diverse AI Workloads: RISC-V Digital Infrastructure, from Intelligent Computing Centers to Embodied Intelligence Device-Edge Collaboration.”

Three highlights stand out: First, the lineup covers IP (ESWIN Computing), operators (China Telecom Research Institute), intelligent computing and storage (Yuanshi Intelligent Computing, Lirui Microelectronics), industry scenarios (Qingdao Guoshi marine data), operating system communities (openKylin), chip vendors (Sophgo), and industry platforms (RDI Innovation Center) — a rare September agenda in China bringing the full chain of “RISC-V × Embodied Intelligence × Large Models × Data Centers” onto the same stage; second, the topics extend from “computing power supply” to “device-edge collaboration and embodied intelligence,” consistent with the Beijing RISC-V Digital Infrastructure Innovation Center’s recent positioning in data centers and device-edge collaboration; third, the conference’s academic sessions and expo are open free of charge with real-name entry, and the on-site outcomes of the September 18 forum can serve as follow-up leads for the next daily briefing. This item was designated as required for the user queue and has been prioritized for inclusion.

I. Open-Source Community and Software Ecosystem

1.1 XiangShan: RVV Vector Divide Instruction Merged, Smmtt Extension Decode Re-enabled, Multiple Fixes Across Bpu/FMA/CSR

Date: 2026-09-11 ~ 2026-09-13　Source: OpenXiangShan/XiangShan commit log

The main XiangShan repository saw 9 commits in this window, continuing the pattern of “convergence after vector datapath refactoring.” On the feature side: zhaozukang merged feat(vector): support vector divide instruction on 09-12, landing vector divide support; Xuan Hu submitted feat(decode): add back conditional Smmtt extension support on 09-11, re-adding the previously removed Smmtt (Supervisor domain and trusted execution environment memory management) extension support via conditional decode, alongside a refactor of pass extensions to decode fields for decode parameter passing; HuSipeng added the branch prediction unit s2_override on 09-11. Bug fixes centered on floating point and CSR: Guanghui Cheng corrected the NaN-boxing check for FMA addends on 09-11 (#6532) and fixed LCOFIP bit loss during CSR read-modify-write (#6522); Zhihao Xu fixed the touch behavior of the two-fetch replacer in ICache on 09-11 (#6416). On the cleanup side, Xuan Hu removed the outdated backend VL non-zero state and cleaned up unused vector classes and methods on 09-13. Among companion repositories, XSAI (the AI-oriented XiangShan branch) submitted a difftest submodule upgrade on 09-11 (#128); XSCache (open-source L2/LLC cache) and YunSuan (functional unit library) had no new commits in the window (most recent on 08-31 and 09-10, respectively).

1.2 CVA6: Eight Commits in the Window, Focused on PMP and Trigger Rules, Zcmp IDLE Gating, and xRET Fixes

Date: 2026-09-11 ~ 2026-09-13　Source: openhwgroup/cva6 commit log

The open-source six-issue application-class RISC-V core CVA6 recorded 8 commits in the window, mainly targeting privileged-state and debug correctness: Maanvi212006 required HLVX accesses to have execute permission on 09-13 (#3413, correcting the combination of PMP and Hypervisor memory access permissions); Flavien Solt concentrated on fixing debug trigger semantics on 09-11, including NAPOT address matching (#3488), dmode trigger write rules (#3487), and preservation of LoadAddr trigger actions (#3491); Keerthivasan Palani fixed MPRV handling in xRET when RVH is absent on 09-11 (#3551) and WFI stalls under single-step execution (#3525), and changed the Zcmp IDLE state transition to be gated on issue acknowledgment (#3543); Téo Biton added valid bits to the branch prediction structures on 09-11 (#3550). Overall, this week’s commits centered on “privileged/debug boundary-condition correctness,” a typical pattern of functional-verification-driven progress; CVA6 is also cited by riscv.org as a case study of a performance-model-driven superscalar open-source core.

1.3 openRuyi: No New Release in the Window, September Release Page Does Not Exist, Latest Stable Remains 2026.08

Date: 2026-09-14 verification　Source: openRuyi news and release list

Per routine source verification, the openRuyi news list shows no new entries in the window, its September release page (2026-09/release) returns 404, and the latest stable release remains 2026.08 (GCC 16.2.0, glibc 2.44, Rust 1.97.1, mainline kernel 7.2, LTS 6.18.46, with newly added ROCm 7.2.4 and vLLM in both CPU and ROCm builds, KDE Plasma 6.7.4, GIMP 3.2.0), which was already covered in our 2026-09-11 issue. No new openRuyi ecosystem activity was made public during the same period, so it is not repeated in this issue. The distribution is led by the Institute of Software, Chinese Academy of Sciences; its rolling release tracks the latest upstream baseline, and it remains a key domestic RISC-V distribution to watch, to be tracked monthly going forward.

II. Product and Ecosystem Updates

Date: 2026-09-12　Source: China Daily Shenzhen, IICIE Conference List

From September 9 to 11, 2026, the 2026 IICIE International Integrated Circuit Innovation Expo, themed “Cross-Boundary Integration · Full-Chain Collaboration, Building a Distinctive Chip Ecosystem Together,” was held at the Shenzhen World Exhibition & Convention Center (Bao’an). The expo ran concurrently and on the same site as CIOE (China International Optoelectronic Exposition) and elexcon (Shenzhen International Electronics & Embedded Exhibition), with the three shows totaling 320,000 square meters of exhibition space, gathering over 5,000 exhibitors and more than 240,000 professional visitors, and fully linking the chain from “computing chips—high-speed interconnect optical components—electronic hardware—end applications.” More than 20 industry summits were held alongside the expo, covering silicon photonics manufacturing, advanced packaging, wide-bandgap semiconductors, RISC-V architecture, automotive chips, embodied intelligence, and other directions. Among them, the “2026 RISC-V Industry Ecosystem Innovation Conference” on the afternoon of September 9 was a key conference in the chip and chip application category; among the five featured showcase areas, a dedicated “RISC-V Ecosystem Application Showcase Area” was set up to display benchmark open-source architecture products including the DAMO XuanTie series chips. Hall 16 also hosted a university and research institute showcase area, with more than ten institutions including the School of Integrated Circuits at Tsinghua University and the School of Integrated Circuits at Sun Yat-sen University participating. The RISC-V forum agenda of this expo was previewed in our 2026-09-09 issue; this item is a supplementary report on the expo’s conclusion and the implementation of the showcase areas.

2.2 Infineon Discusses RISC-V for Automotive at Hot Chips 2026: Next-Generation Automotive-Grade MCUs Take the RISC-V Route, with the Decisive Factor Being the Automotive-Grade Toolchain

Date: 2026-09-13　Source: ServeTheHome

The transcript of Infineon’s presentation at Hot Chips 2026 was published within the window, with the core focus on the computing requirements of automotive-grade MCUs and the positioning of RISC-V. Infineon’s requirement profile is as follows: the convergence of chassis, powertrain, and ADAS demands real-time low latency, high energy efficiency, and safety coexisting, compounded by the highest integrity levels and functional safety; fast control loops such as motor control require deadlines within 10 milliseconds and interrupt latency on the order of tens of nanoseconds, while vehicle management policy functions can tolerate seconds and 10-millisecond-level interrupt latency. Infineon emphasized that RISC-V specifies an instruction set architecture rather than implementation details; instruction latency, memory hierarchy, cache coherency and lockstep, error tracking, and other functional safety features are still determined by the chip designer, which is precisely where automotive differentiation lies. In MCU scenarios, the attributes that truly determine victory are memory, connectivity, dedicated hardware, supply, and final BOM cost, while “whether an automotive-grade certified toolchain exists” determines who wins. At the conclusion level, Infineon directly binds RISC-V to the zonal controller role: RISC-V can accelerate the deployment of zonal control units, but application adaptation and cost are jointly determined by SoC architecture, ecosystem momentum, and deployment convenience, with long-term adoption depending on standardized software and hardware interfaces and toolchain support. The vendor had previously made clear that its next-generation AURIX automotive-grade MCUs are based on RISC-V.

2.3 Espressif ESP32-P4 Runs Tomb Raider: Dual-Core 400 MHz RISC-V Software Rendering at 30 FPS, on a $25-Class Development Board

Date: 2026-09-13　Source: Tom’s Hardware, GitHub openlara_esp32p4

Developer alexkid77 has ported the open-source engine OpenLara (a reimplementation of the original Tomb Raider engine) to the Espressif ESP32-P4: the SoC is a dual-core 400 MHz RISC-V (with AI instruction extensions), paired with 16 MB Flash and 32 MB PSRAM. The project uses 320x240 software rendering combined with the chip’s built-in Pixel Processing Accelerator (PPA) for hardware upscaling to a 1024x600 display, achieving 30 FPS, and incorporates I2S with ES8311 audio, a USB HID keyboard, GT911 touch, and microSD storage, plus support for MP3/OGG decoding and an on-screen FPS counter. The hardware platform is the ESP32-P4-Function-EV-Board, with the full board priced in the $25 range and power consumption of about 1 watt. The technical significance lies not in the game itself but in demonstrating the compute power and display/audio-video peripheral integration capabilities of RISC-V application-class MCUs: microcontrollers that previously required meticulous resource budgeting can now carry real-time software rendering workloads on the scale of last-century game consoles. This item is a fun R&D-oriented product update and can serve as an intuitive footnote to the upward trajectory of RISC-V edge compute power.

III. Domestic Team Updates and Deep Dives

3.1 Follow-up on Shanghai Jiao Tong University’s SPMP Standard: SJTU Official Website Publishes In-Depth Article, Confirms Deployment on XiangShan and Nuclei Chips

Date: 2026-09-11 (standard approved 08-31)　Source: Shanghai Jiao Tong University News, Shanghai Education Media Network

This is a follow-up to the standard event (approved 2026-08-31, covered by mainstream media starting 09-08; the event itself was included in our 09-09 issue). SJTU’s official website published an in-depth article on 09-10 to 09-11, adding detail on the specific significance and deployment evidence of China’s first “from-scratch, fully led” effort: First, technical positioning — SPMP (Supervisor-mode Physical Memory Protection) targets “fixed-layout” scenarios such as AI chips, automotive chips, smart terminals, and industrial controllers, using supervisor-mode physical memory isolation to replace multi-level page tables, avoiding the high latency of layer-by-layer table lookups and the hardware area/power overhead of page tables. Second, deployment status — SPMP has been deployed and applied on domestic chips including XiangShan (the Chinese Academy of Sciences’ open-source high-performance RISC-V processor) and Nuclei (a domestic RISC-V IP vendor). Third, community track record — SPMP was selected as a RISC-V International 2021 security highlight feature and listed by the Linux Foundation as one of the four major RISC-V security advances of 2023, the only Chinese project selected that year. Fourth, recognition — Bao Yungang, a board member of RISC-V International and deputy director of the Institute of Computing Technology at the Chinese Academy of Sciences, offered congratulations, calling this the first time a Chinese institution has initiated and fully led the development of a RISC-V extension standard from scratch, which both improves the RISC-V security architecture and sets an example for domestic institutions participating in international standard-setting. On the team side, the work was led by IPADS (Du Dongdong, Yang Bicheng, Xia Yubin, Chen Haibo, and others), with the initial architecture draft submitted on 2019-09-23, spanning nearly seven years; at the time of approval, the SPMP working group chair was IPADS PhD Yang Bicheng. The direct implication for the domestic ecosystem: XiangShan and Nuclei already have an implementable path for this isolation capability, and the “standard-to-implementation” loop for domestic RISC-V security features is taking initial shape.

3.2 Follow-up on Nuclei Technology’s IPO: Ninety Percent of Revenue from RISC-V IP Licensing, China Merchants Securities as Advisor, First-Half Revenue Up 41% but Not Yet Profitable

Date: 2026-09-12 ~ 2026-09-13　Source: Phoenix Finance, East Money

Follow-up on Nuclei Technology’s filing for IPO advisory at the Beijing Stock Exchange (the advisory filing event was included in our 09-10 issue). During the window, media added three financial and business details: First, revenue structure — ninety percent of the company’s revenue comes from RISC-V IP licensing, making it one of the few domestic vendors whose core business is pure RISC-V CPU IP licensing, directly comparable to the IP licensing business under the ARM model. Second, the advisor is China Merchants Securities. Third, performance overview — first-half revenue grew about 41% year-on-year, but the company is not yet profitable. Combined with prior information, Nuclei launched its Beijing Stock Exchange IPO advisory filing around 09-10; if it proceeds smoothly, it will become the first company among China’s top-tier RISC-V IP players to enter the capital markets. The industry observation value lies in two points: First, the profitability model for pure IP licensing in the RISC-V context remains unproven (high growth, not yet profitable), which corroborates Bao Yungang’s earlier argument about the “open-source IP kill line.” Second, if the Beijing Stock Exchange path works, it could provide a new financing paradigm reference for domestic RISC-V IP and toolchain companies.

3.3 SOPHGO SG2044: UEFI Firmware Adjusts Boot Option Ordering, sophgo-edk2 Follows Suit

Date: 2026-09-11　Source: sophgo/edk2-platforms, sophgo/sophgo-edk2

SOPHGO advanced UEFI firmware for the SG2044 platform during the window: Chao Wei submitted Sophgo/SG2044: Order freshly enumerated boot options ahead of inherited ones on 09-11, placing newly enumerated boot options ahead of inherited ones and correcting the priority order of multiple boot entries — a typical experience fix for multi-boot-media (NVMe/SD/USB/PXE) scenarios; the sophgo-edk2 main repo updated the edk2 and edk2-platforms submodules the same day, and pushed concentrated updates across four repositories — edk2, edk2-platforms, MultiArchUefiPkg, and sophgo-edk2 — between 08:56 and 09:27. Combined with the “MultiArchUefiPkg memory allocation strategy adjustment” covered in our 09-11 issue, it is clear that SOPHGO is continuously refining the standard firmware boot chain for RISC-V servers around the SG2044, a direct indicator of the productization level of its data center direction.

3.4 SpacemiT: Vision Model Zoo Adds RF-DETR Object Detection, SigLIP2 Defaults to In-House Execution Backend

Date: 2026-09-11　Source: spacemit-com/model-zoo-vision, spacemit-com/docs-openharmony

SpacemiT advanced two lines in parallel during the window: edge AI and OpenHarmony documentation. The vision model zoo model-zoo-vision merged #81 on 09-11, adding the RF-DETR COCO object detection model (RF-DETR is a currently popular solution in real-time detection), and submitted #80 to switch the SigLIP2 vision-language model by default to the in-house SpaceMITExecutionProvider execution backend, meaning its inference stack is shifting from reusing generic backends to its own optimized path; the ai-sdk main repo updated the vision submodule twice on the same day. On the documentation side, docs-openharmony merged #66 and #67 on 09-11, adding OpenHarmony WebView-related documentation and fixing defects; docs-ai submitted an English File2MD guide the same day, corrected the vLLM placeholder documentation, and aligned sidebar hierarchy. Overall, SpacemiT is running three lines in parallel — in-house execution backend, model zoo expansion, and documentation completion — and its edge multimodal inference and deployment support for its K1/K3 series chips continue to intensify.

3.5 Sipeed: NanoKVM-Pro Adds Web Display Policy Control, Wiki Adds NanoKVM Go Two-Factor Authentication Guide

Date: 2026-09-11　Source: sipeed/NanoKVM-Pro, sipeed/sipeed_wiki

Both Sipeed product lines saw updates during the window. NanoKVM-Pro (a high-performance 4K IP-KVM, a RISC-V-based remote management device) merged #151 on 09-11, adding web display policy control, and used #140 to improve the reliability of web-side mouse input, pointing to continuous refinement of its remote operation experience; the official wiki made three consecutive commits on 09-11, adding a two-factor authentication guide for NanoKVM Go, syncing main-screen operation instructions, and providing tutorials for two intranet penetration methods — Cloudflare Tunnel and phtunnel — indicating that the product is converging from an open-source hardware project toward a “deliverable, operable” form. Sipeed is one of the most actively iterating domestic teams in the RISC-V board and companion software ecosystem, with its recent high-frequency commits concentrated in the IP-KVM product line.

IV. Embodied Intelligence and Robotics Special Chapter

4.1 SpacemiT spacemit-robotics: MuJoCo simulation adds headless mode, robot simulation moves toward CI

Date: 2026-09-11　Source: spacemit-robotics/simulation_mujoco

The SpacemiT robotics software stack (spacemit-robotics) continued to advance during the window: simulation_mujoco merged #8 on 09-11, adding a headless simulation mode. This repository is the MuJoCo simulation environment for its robotics SDK, and headless mode is a key capability for shifting simulation from “manually watching in a GUI” to “batch/automated execution on servers,” typically used for regression testing, parameter sweeps, and continuous integration (CI). Combined with the organization’s batch pushes from 09-08 to 09-09 across repositories including IMU and motor drivers (peripherals-imu, peripherals-motor), whole-body control (control_whole_body), the Linglong humanoid (humanoid_linglong), the ROS 2 humanoid (ros2_humanoid), and perception (perception), its robotics SDK has formed a complete layered stack of “peripheral drivers—whole-body control—simulation—perception,” and it is continuously filling in engineering capabilities rather than merely doing demos. This thread is consistent with SpacemiT’s pace on the main chip side in advancing its in-house inference backend and vision model library, pointing to an embodied intelligence software stack on the RISC-V platform that is moving from “it runs” to “testable and deliverable.”

4.2 Kaihong M-Robots OS 3.0 Beta: robot operating system digital foundation adapts to four architectures—ARM/RISC-V/LoongArch/x86

Date: released 2026-08-28, media reposted 2026-09-13　Source: Kaihong official website, ifeng repost of Kuai Technology

Kaihong (Shenzhen Kaihong Digital Industry Development) released M-Robots OS 3.0 Beta at the 2026 China International Big Data Industry Expo (Guiyang, opening August 28), with media reposts falling within this window, so it is included here with the original release date noted. Built on OpenHarmony as its foundation, the system is a distributed heterogeneous multi-robot collaborative operating system for multiple robot forms. Version 1.0 (2025-04) addressed multi-hardware-form compatibility and low-latency communication; 2.0 (2026-05) filled in six major capabilities including a building-block framework, hybrid deployment, and M-DDS low-latency collaboration; and 3.0 Beta shifts its focus from single-machine capabilities to swarm intelligence, upgrading along four main lines: security (VAA unified digital identity, KGSI secure boot, swarm security state sharing), real-time performance (in-house single-chip multi-kernel hybrid deployment, with interrupt response and task switching latency of 1 microsecond or less, 2-second recovery for critical services and 4-second recovery for the whole machine), swarm intelligence (Agent Native framework and M-Claw distributed autonomous cluster), and the digital foundation. Directly relevant to this publication’s theme is the digital foundation item: it explicitly adapts to the four major architectures ARM, RISC-V, LoongArch, and x86, and is compatible with the three major ecosystems ROS, Dora-rs, and OpenHarmony, covering four categories of compute—CPU/NPU/GPU/BPU. The event also demonstrated three swarm collaboration scenarios—unmanned retail, campus inspection, and water quality testing—and jointly released with Digital Huaxia the fully domestic humanoid robot Xingxingxia P02 based on this system. The project was donated to the OpenAtom Foundation in November 2025, and community operations began in June 2026, with 13 SIG technical groups and an independent PMC. The implication for the RISC-V ecosystem is that a leading domestic robot operating system lists RISC-V alongside ARM as a first-tier support target at the architecture level, providing an upper-layer software entry point for RISC-V chips to enter embodied intelligence complete machines.

V. Summary and Trend Observations

  • China enters a dense period of RISC-V industry events in September. From September 9 to 11, IICIE concluded in Shenzhen with a dedicated RISC-V Industry Ecosystem Innovation Conference and an ecosystem application showcase area; from September 16 to 18, IC WORLD in Beijing features a special track titled “RISC-V Open Computing Forum: Embodied Intelligence · Large Models · Data Centers,” with an agenda covering IP, carriers, intelligent computing storage, industry data, operating system communities, and chip vendors. The center of gravity of RISC-V discussions is clearly shifting from “chips/instruction sets” toward “AI computing power and device-edge collaboration.”

  • The “dual-track breakthrough” in standards and capital has entered a follow-up reporting phase. SPMP from Shanghai Jiao Tong University, as the first ISA feature fully led from scratch domestically, has had its deployment evidence supplemented down to specific chips (XiangShan, Nuclei), and the “standard—implementation” loop is taking initial shape. Meanwhile, Nuclei is sprinting toward a Beijing Stock Exchange listing, with 90% of revenue from RISC-V IP licensing but not yet profitable—a reality that stands in contrast to Bao Yungang’s judgment on the “open-source IP kill line.” The profitability model of pure IP licensing remains an unresolved issue in China.

  • Functional verification of open-source cores has entered deep waters. Within the window, XiangShan merged vector division instructions and reopened conditional support for Smmtt (Trusted Execution Environment memory management), while CVA6’s eight commits concentrated on privileged-state boundary conditions such as PMP, debug triggers, Zcmp, and xRET—the advancement focus of both high-performance open-source cores falls on “security and privilege correctness,” echoing the domestic security feature mainline represented by SPMP.

  • The upward trajectory of edge computing power continues to be corroborated by hardware facts. Espressif ESP32-P4, with dual-core 400 MHz RISC-V plus a built-in pixel processing accelerator, achieved 30 FPS software rendering of the Tomb Raider engine on a ~$25, ~1-watt development board, demonstrating that the capability boundary of RISC-V application-class MCUs has moved beyond the traditional microcontroller category, with direct implications for localized computing solutions in robotics, industrial, and consumer edge applications.

  • The embodied intelligence software stack is converging toward engineering maturity. SpacemiT’s spacemit-robotics added headless mode for MuJoCo simulation, giving it server-side batch regression and CI capabilities; Kaihong’s M-Robots OS 3.0 Beta lists RISC-V and ARM side by side as two of the four supported architectures in its digital foundation. The two respectively pave the way for RISC-V’s entry into embodied intelligence complete machines from the directions of “testability” and “carryability.”

  • Limitations note: This report window covers 3 days of the week (09-11 08:18 to 09-14 08:18). Google News aggregation of Chinese tech news is severely polluted by gambling-related SEO articles (this issue removed entire batches of entries containing “sports/login/entry/official website/download/entertainment platform” keywords), and Chinese-language entries are based on official channels and mainstream media original sites. The unauthenticated GitHub API has a rate limit of 60 requests per hour; organization checks use pushed sorting to spot-check recently active repositories, and pushes to non-default branches may be missed: DAMO XuanTie (XUANTIE-RV)’s gcc and binutils-gdb repositories had pushed_at updated to 09-13 within the window, but no retrievable new commits were found on the default branch or major upstream branches within the window, and org-level commit searches returned 0 results, so no entry was established on this basis in this issue; ESWIN Computing (eswincomputing)’s most recent push was 07-14, and StarFive (starfive-tech) was 09-02, with zero pushes within the window. Shanghai Jiao Tong University’s SPMP is from the same source as the event covered in our 09-09 issue (approval date 08-31); this issue provides a follow-up based on the “SJTU official website 09-11 in-depth article” and has been annotated accordingly; the IICIE RISC-V forum agenda was previewed in our 09-09 issue, and this issue serves as a post-event supplement; Kaihong’s M-Robots OS 3.0 Beta had an original release date of 08-28, and this issue covers a 09-13 media reprint and has been noted accordingly. Today’s highlights are user-queue-specified entries, which have been prioritized for inclusion and the queue file cleared after inclusion.

Appendix: Source Verification Table and Complete Source List

Source Verification Table

Source Verification Result
fetch_news.py 3-day candidates (47 items) 3 valid: Infineon automotive RISC-V (ServeTheHome, included as 2.2), Debian 13.7 (general distro update, no RISC-V-specific content, excluded), TinyEMU emulator HN post (4 points, personal project, excluded); low-value noise excluded: 30+ personal learning repos (five-stage pipeline cores, teaching kernels, FPGA SoCs, assembly experiments, etc.), 4 cryptocurrency items (Yellow.com Ethereum articles, unrelated to RISC-V), ESP32-S3 LoRa terminal (Xtensa core, not RISC-V), general-purpose projects such as wireguard-fpga and iPXE
gnews English queries (RISC-V when:1d/3d, RISC-V Summit/SiFive/Andes/StarFive/Milk-V/SpacemiT/SOPHGO when:7d, RISC-V AI chip/automotive/robot/data center when:3d/7d) Valid: Infineon automotive RISC-V (Hot Chips transcript, included as 2.2), ESP32-P4 running OpenLara (Tom’s Hardware, included as 2.3); out-of-window exclusions: Quintauris ecosystem collaboration (09-09), Canonical enterprise RISC-V Hot Chips transcript (09-07), SiFive RVA23/RVB23 spec transcript (09-07), YuzukiNeko Allwinner F101 SBC (09-07), Microcontroller market forecast (09-07); irrelevant noise: dairy/food e-commerce articles matched by Milk-V (44 items, all excluded), Colombian poultry industry and Chilean stock market articles matched by Andes, UK entertainment articles matched by StarFive; zero hits within window for SpacemiT and SOPHGO
gnews Chinese queries (RISC-V when:3d, RISC-V chip/ecosystem/robot when:3d/7d, open-source instruction set when:3d, XuanTie/DAMO, XiangShan, SpacemiT/StarFive/Nuclei, Sophgo/ESWIN/GigaDevice, Espressif when:3d/7d) Valid: Nuclei IPO (ifeng Finance 09-12, East Money 09-13, included as 3.2), 2026 IICIE Shenzhen concludes (China Daily 09-12, included as 2.1), Kaihong M-Robots OS 3.0 Beta (09-13 reprint, included as 4.2); noise excluded: 100+ gambling SEO articles on ttplus.cn (containing “official download/login portal/entertainment platform/sports” etc.), Beijing Xiangshan Forum and Xiangshan Co. shareholder reduction (unrelated to open-source processors), wuxia and tourism “XuanTie/XiangShan” hits, all GigaDevice/Espressif hits were stock price, buyback, and fund holdings articles (no RISC-V events)
RSS (CNX Software / LinuxGizmos / Phoronix / riscv.org) RISC-V keyword hits within window: no new posts on riscv.org within window (most recent was 09-10 MIPS automotive feature, already reported in the 09-11 issue); Phoronix within window covered Linux 7.3-rc3, Debian 13.7, GTK 4.24, Mold rewrite and other general open-source items, no RISC-V-specific items; CNX within window covered M5Stack LoRa, NeoEyes NE302 (STM32N6), Renesas RZ/G3L, Amlogic Cortex-A320 and other non-RISC-V items; no RISC-V items on LinuxGizmos within window
HN (Algolia) Only one post within window: TinyEMU (RISC-V and x86 system emulator), 4 points, 0 comments, not event-level, excluded
GitHub organization scan (OpenXiangShan, XUANTIE-RV, spacemit-com, spacemit-robotics, sophgo, Nuclei-Software, sipeed, eswincomputing, starfive-tech, openhwgroup, espressif) Active: XiangShan family (XiangShan 9 commits, XSAI 1, included as 1.1), openhwgroup/cva6 (8 commits, included as 1.2), sophgo (4 pushes, included as 3.3), spacemit-com (including model-zoo-vision, docs-openharmony, etc., included as 3.4), spacemit-robotics (included as 4.1), sipeed (included as 3.5); quiet or no item: XUANTIE-RV (pushed updates but no retrievable commits within window), Nuclei-Software (mirror branch sync only, no commits within window), revyos (most recent 09-07), eswincomputing (most recent 07-14), starfive-tech (most recent 09-02), espressif (commits are ESP32 Xtensa and general component lines, not RISC-V-specific)
Periodic check (openRuyi official site) No new additions to news list within window, September release page returns 404, latest official release remains 2026.08 (already reported), not repeated in this issue (see 1.3)
User pending-inclusion queue 1 item (IC WORLD RISC-V Open Computing Forum agenda), included as today’s highlight per user specification, queue file moved to used directory after inclusion

Complete Source List

Data source: Daily RISC-V Global Intelligence Briefing (2026-09-14 issue); topic is RISC-V global intelligence research, research window is 2026-09-11 to 2026-09-14. Google News aggregation channel accessed, GitHub organization and commit searches completed via GitHub API, queries merged at organization granularity under unauthenticated rate limits.