Research window: Past 24 hours (2026-09-10 08:18 ~ 2026-09-11 08:18, Beijing time) Sources: Hacker News, Google News aggregation, CNX Software / LinuxGizmos / Phoronix / riscv.org RSS, NextSilicon and Eindhoven University of Technology official websites, riscv.org blog, Chinese financial media (Sina Finance, etc.), GitHub API (pushed and commit searches across repositories of seven domestic RISC-V organizations) (see appendix source verification table for details)

Today’s Highlights: Bao Yungang on RISC-V and Open-Source IP — The “Open-Source IP Kill Line” Is Forming

Source: Beijing Institute of Open Source Chip (BOSC) WeChat account, “【Expert Viewpoint】Bao Yungang: A Brief Discussion of the Beijing Municipal People’s Government’s Issuance of the 〈Beijing ‘15th Five-Year Plan’ Period High-Precision and Advanced Industry Development Plan〉” (https://mp.weixin.qq.com/s/tUq67S2OF_yor_jD60HSHw)

The Beijing Municipal People’s Government issued the 〈Beijing “15th Five-Year Plan” Period High-Precision and Advanced Industry Development Plan〉, proposing to accelerate the construction of innovation platforms for the fifth-generation reduced instruction set architecture (RISC-V), chiplets, and optoelectronic integration, continuously advance the iterative upgrading of new architecture products such as compute-in-memory, and concentrate efforts on cultivating an autonomous computing industry ecosystem. Bao Yungang, Deputy Director of the Institute of Computing Technology, Chinese Academy of Sciences, and Chief Scientist of the Beijing Institute of Open Source Chip (BOSC), shared several observations on this:

First, the “forest theory”: The RISC-V ecosystem is like a forest — it needs both towering trees (high-performance RISC-V chips) and shrubs and grasses (a massive number of embedded MCUs). To cultivate towering trees, the ARM model is no longer applicable; new models must be explored, and open-source IP will be the path with the highest probability of success; cultivating shrubs and grasses to serve massive customized long-tail demand is like the “Yiwu model” — small commodities, big market — and can draw on the JLC model to respond with low-cost, agile development systems.

Second, RISC-V + AI will become mainstream in the AI era: Different AI scenarios, models, and deployment forms impose highly differentiated requirements on hardware. RISC-V’s openness and extensibility make it easier than x86 and ARM to adapt to AI customization needs. Recently, RISC-V has been behind the self-developed AI chips of Meta and OpenAI.

Third, the software ecosystem barrier needs a refreshed understanding: Migrating software across instruction sets is costly and has long been the core barrier in CPU ecosystem competition; but with the rapid development of AI Agents, the cost of code migration, adaptation, debugging, and optimization has dropped by orders of magnitude. In the future, the software ecosystem will no longer be a barrier.

Fourth, the “open-source IP kill line”: The global ARM ecosystem has only one IP supplier, with annual revenue of about US$3 billion. RISC-V IP prices must be lower than ARM’s to have a chance of replacement, and the total market is unlikely to exceed US$3 billion; but an open instruction set means multiple IP suppliers coexist, none of which can grow very large individually, making it difficult to sustain high R&D costs (the recent example being Andes closing the high-performance RISC-V IP subsidiary it established in Texas in 2023). The way to break through is to provide high-performance RISC-V IP as an industry public good in an open-source model, reducing licensing fees from tens of millions to hundreds of millions of yuan by 1-2 orders of magnitude — just as Chinese large models such as DeepSeek have spread AI applications across all industries through open source. The open-source model has a sustainable business model: when systems become complex enough, space for professional services emerges (“Linux + RedHat,” “Android + Thundersoft”).

Fifth, XiangShan’s six years of practice: XiangShan was launched in June 2020, and BOSC was established in December 2021 to support its continued development; as a non-profit organization (NPO), BOSC does not need to pursue valuation or profit, and only needs to raise funds covering operating costs each year (about 150 million yuan/year) to operate over the long term. XiangShan has basically solved three major challenges: fundraising, industrial-grade quality (sufficient verification), and continuous iterative evolution (one generation released each year) — “we have the confidence and the foundation to let XiangShan live for 30 years.” This forms a cold “open-source IP kill line”: if cost-effectiveness cannot rise above this line, the logic of self-developing high-performance IP will be difficult to sustain (analogous to the demise of proprietary Unix after the birth of Linux in 1991). Chip companies that actively embrace open-source IP will become the beneficiaries — the “XiangShan” R&D team has become a public asset of the entire chip industry.

Commentary: This is another important statement on China’s RISC-V policy and industry路线 following the August Dishui Lake Forum and the RISC-V China Summit: Beijing’s “15th Five-Year Plan” includes RISC-V in the construction of key high-precision and advanced industry platforms, while Bao Yungang argues at the level of industrial organization for the necessity and sustainability of the “open-source high-performance IP” route, which has bellwether significance for the route choices of domestic RISC-V chip companies (self-developed IP versus embracing open-source IP).

This Issue’s Index

  • Today’s Highlights: Bao Yungang on RISC-V and Open-Source IP — The “Open-Source IP Kill Line” Is Forming (BOSC WeChat account)
  • I. Open-Source Community and Software Ecosystem
    • XiangShan: vector pipeline restructuring moves into convergence, vxsat write-enable fix and VPUCtrlSignals cleanup, xspdb adapts to new picker (09-10)
    • DAMO XuanTie: AI microkernel library torq-tile updated within the window, RVV quantized GEMM and activation kernel functions merged in batches (merged 09-07)
    • openRuyi 2026.08 officially released: GCC 16.2 / glibc 2.44 / kernel 7.2, RVA23 integration and vLLM/ROCm implementation (included as a regular source starting this issue)
  • II. Product and Ecosystem Developments
    • NextSilicon publicly unveils Arbel for the first time: self-developed out-of-order superscalar RISC-V core, dual-core 2.4 GHz coherent test chip runs Linux/Ubuntu (09-10)
    • riscv.org publishes a contributed article by the CEO of MIPS: the significance of RISC-V to the automotive industry lies in freedom of choice (09-10)
    • Eindhoven University of Technology’s CONVOLVE project releases the Chimera chip: cross-layer collaboration between RISC-V processing cores and memory-centric/neuromorphic accelerators (released 09-08, follow-up coverage by English media on 09-10)
  • III. Domestic Team Developments and Deep Dives
    • Nuclei launches filing for Beijing Stock Exchange listing guidance: first-tier RISC-V CPU IP player sprints toward the capital market (09-10)
    • Sophgo SG2044: UEFI multi-architecture emulator memory allocation strategy adjustment (09-10)
    • SpacemiT: K1-series U-Boot merges k1-release into the k1-bl-v2.2.y boot branch (09-10)
  • IV. Special Chapter on Embodied Intelligence and Robotics
    • SpacemiT docs-ros: robot perception and navigation documentation updated, placeholder pages cleaned up (09-10)
  • V. Summary and Trend Observations
  • Appendix: Source Verification Table and Complete Source List

I. Open-Source Community and Software Ecosystem

1.1 XiangShan: Vector Pipeline Refactoring Enters Convergence, vxsat Write-Enable Fix and VPUCtrlSignals Cleanup, xspdb Adapts to New Picker (09-10)

Date: 2026-09-10 (Beijing time batch, 09:02 ~ 17:03)　Sources: GitHub OpenXiangShan/XiangShan commits, XiangShan-Dashboard, XSCache, XiangShanLab, minjie-playground, GEM5, extention-xspdb

After removing the VFAlu/VFMA wrapper layer on 09-09, the vector subsystem of the XiangShan open-source high-performance core (Kunminghu) entered a supporting convergence phase on 09-10: the 17:01 commit chore(vector): remove VPUCtrlSignals continued cleaning up redundant control signal structures in the vector unit; the 17:03 commit fix(vector): propagate vxsat write enable fixed the propagation chain for the vector fixed-point saturation flag (vxsat) write enable (author date 07-23, wrapping up a long-running branch batch). On the non-vector side, the 09:02 commit fix(build/xspdb): add required filelist arg for new picker (#6523, authored and committed the same day, a same-day development result) adapts the xspdb debugging and tracing tool to the new file picker. Supporting repositories were pushed across the board within the window: XiangShan-Dashboard (15:49), XSCache (15:49), minjie-playground (14:46), workload-builder (14:19), XiangShanLab (13:51), env-scripts (17:48), and GEM5 (23:25) were updated in succession. Overall assessment: the continuous merges of vector group instructions since 09-06 have transitioned from “feature rollout” to “structural cleanup and defect fixing,” leaving interface space for subsequent matrix/reduction operation extensions; the openxiangshan organization remains the most active open-source core team in China within the window.

1.2 DAMO XuanTie: AI Microkernel Library torq-tile Updated Within Window, RVV Quantized GEMM and Activation Kernels Merged in Batch (merged 09-07)

Date: 2026-09-10 (repository push time; most recent substantive commit 09-07)　Source: GitHub XUANTIE-RV/torq-tile

The XUANTIE-RV/torq-tile repository of DAMO XuanTie (T-Head) on GitHub showed a push record at 14:43 (Beijing time) on 09-10, with no new commits on the default branch (main, single branch), judged to be a branch/metadata operation; its most recent batch of substantive merges occurred on 09-07, consisting of a batch landing of quantized inference microkernels for the RISC-V Vector extension (RVV): new Q8_0×Qx_0, Q2/Q3 factorized GEMM microkernels and quantized activation block kernels were added, the quantized GEMM path for non-zero K starting points was completed, and ReLU / SiLU / GeLU and gated activation microkernels were introduced; on the convolution side, register pressure for 3x3s1 depthwise convolution and im2col/IGEMM input handling were optimized, while the split-K offset of the RVV tiled GEMM and the NaN preservation issue in the floating-point output path were fixed. The repository’s README describes itself as an open-source RISC-V microkernel/tile kernel library for AI workloads (Apache-2.0, v0.1.0), optimized for RVV and XuanTie processors, with the design goal of letting C/C++ machine learning and AI frameworks directly consume operators at file granularity. This repository had not previously appeared in the daily briefing; this is its first inclusion: it fills in the software link in XuanTie’s “open-source hardware (XuanTie series) + open-source operator library” chain, directly corresponding to the actual demand of domestic edge AI frameworks for RVV quantized operators.

1.3 openRuyi 2026.08 Officially Released: Security Fixes Dominate, GCC 16.2 / glibc 2.44 / Kernel 7.2, RVA23 Integration and vLLM/ROCm Acceleration Stack Land (included as a regular source from this issue onward)

Date: 2026-08 release (included as a regular source for the RISC-V daily briefing from this issue onward; future releases will be reported as they appear)　Sources: openRuyi official release announcement, release download site

The openRuyi distribution led by the Institute of Software, Chinese Academy of Sciences, released its August 2026 version, focusing on security fixes with concentrated package updates while advancing RISC-V and RVA23 integration and expanding cloud-native and accelerated computing capabilities. Key points:

Toolchain and runtime: GCC updated from 16.1.0 to 16.2.0, glibc from 2.43 to 2.44, Rust from 1.95.0 to 1.97.1; unnecessary build dependencies on LLVM static libraries reduced, and compatibility issues arising from the glibc migration fixed.

Kernel and core platform: Mainline kernel 7.1.4 → 7.2, LTS kernel 6.18.39 → 6.18.46; a kernel production and conversion process based on kernel-team-tools introduced (the initial migration conversion verified 244 mainline patches and 560 LTS patches, generating kernel configurations for x86_64, generic RISC-V, and RVA20); after the kernel refresh, support for RISC-V platforms including SpacemiT, Sophgo, T-Head (DAMO XuanTie), and UltraRISC was further expanded (PCIe/USB/storage/network/display).

RISC-V and RVA23 integration: LLVM 22 fixed RISC-V vectorization crashes and stack probe register clobbering issues; OpenBLAS selects the ZVL128B target in RVA23 builds; Rust QuickJS bindings added riscv64gc and riscv64a23 support (keeping the LP64D ABI unchanged).

Cloud-native/HPC/AI: Kubernetes 1.35.5 and containerd 2.3.3 added; OpenMPI 5.0.10 (with PMIx/PRRTE) included; the Jupyter/Dask scientific computing environment greatly expanded (numerical/geospatial/astronomy/imaging); ROCm 7.2.4 newly added with the ROCm backend enabled in PyTorch 2.13.0, and vLLM added to openRuyi in both CPU and ROCm build variants.

Desktop and security: KDE Frameworks 6.28.0, Plasma 6.7.4, and GIMP 3.2.0 added; security updates cover curl 8.21.0 (18 CVEs), OpenJDK (17/21/25/latest), .NET 10.0.110, OpenSSH 10.5p1, PHP 8.5.9, and more. The distribution offers four editions: Server, Container, Desktop, and Zero (BSP validation); existing users can upgrade via dnf update.

II. Product and Ecosystem Developments

2.1 NextSilicon Unveils Arbel for the First Time: In-House Out-of-Order Superscalar RISC-V Core; Dual-Core 2.4 GHz Coherent Test Chip Runs Linux/Ubuntu (09-10)

Date: 2026-09-10 (company blog; HN submission 09-10 17:18 UTC)　Source: NextSilicon blog (by Yiftach Gilad), Hacker News discussion

NextSilicon disclosed the full story behind Arbel, its in-house high-performance RISC-V CPU core. Author Yiftach Gilad says he spent 18 years doing processors at Intel and initially considered “building your own CPU core” nearly impossible. Arbel did not start as a standalone product but as the serial execution unit paired with the company’s Maverick dataflow accelerator: the first generation was an out-of-order, superscalar, integer-only RISC-V core integrated into the accelerator, running Linux and BusyBox to validate the approach; vector capability, cache coherence, a stronger memory structure, and wider issue were then added incrementally. The key milestone was a dual-core, coherent, 2.4 GHz test chip integrating PCIe Gen5, CXL, and a CHI-based on-chip network, paired with commodity CXL DDR and PCIe components to form a “mini PC” that runs Linux/Ubuntu directly with out-of-the-box GCC/LLVM and benchmarks. The production path is a 64-core, server-class, data-center-oriented chiplet covering virtualization, security, reliability, debugability, and high-bandwidth IO. Architecturally, the company highlights front-end choices that avoid an expensive micro-op cache, a virtual L1 cache structure that reduces load-to-use latency while handling aliasing and tag management, and an atomic L1 fill/evict pipeline. Significance: in HPC and agentic AI scenarios, the company argues the bottleneck is shifting from the math engine to orchestration, memory movement, scheduling, and software execution, making “a CPU next to the accelerator” critical again; Arbel makes NextSilicon the latest startup after SiFive, Ventana, and Rivos to publicly report progress on a server-class RISC-V core, and it is speaking with real silicon rather than a roadmap.

2.2 riscv.org Publishes MIPS CEO Op-Ed: RISC-V in Automotive Is About Freedom of Choice (09-10)

Date: 2026-09-10　Source: riscv.org blog (Viewpoints)

RISC-V International’s Viewpoints section published an op-ed by MIPS CEO Sameer Wasson (author affiliation listed as MIPS, by GF — i.e., MIPS after its acquisition by GlobalFoundries). Core argument: automotive vehicle platforms have decade-long lifecycles, and software must be maintained until the last vehicle is scrapped, so the choice of instruction set architecture (ISA) is a strategic decision; the “economic control” OEMs and Tier 1 suppliers need is not building everything in-house but owning supplier choice, bargaining power, cross-model software reuse, and the ability to evolve hardware without being tied to one vendor’s roadmap. The article argues an open architecture actually expands competition: semiconductor vendors can still differentiate at the implementation layer, IP vendors can innovate above the architecture, the software ecosystem can be reused across systems, and OEMs can maintain architectural consistency while freely evaluating options. The author also stresses that “openness should not mean commoditization,” and notes that as AI becomes ubiquitous in vehicles (perception, ADAS, safety, predictive maintenance, cockpit), architectures need headroom for workloads not yet foreseeable — and the value RISC-V provides is that “the software foundation stays consistent while the implementation layer evolves with the workload.” Significance: MIPS’s pivot to RISC-V with “automotive economic control” as its narrative thread continues this camp’s industry-discourse push following reports around 09-08 of GlobalFoundries launching the MIPS Acies edge AI inference platform, and reflects a shift in RISC-V automotive promotion from “performance benchmarking” toward “long-term cost and supply-chain autonomy.”

2.3 Eindhoven University of Technology’s CONVOLVE Project Unveils Chimera Chip: Cross-Layer Co-Design of RISC-V Processing Cores with Memory-Centric/Neuromorphic Accelerators (released 09-08, follow-up English coverage 09-10)

Date: 2026-09-08 (university release) / 09-10 (follow-up English coverage from Bits&Chips and others entering this window)　Source: TU/e official news, Bits&Chips, CONVOLVE project site

The EU-funded CONVOLVE project led by Eindhoven University of Technology (TU/e) announced its tape-out validation result — an edge AI chip prototype codenamed Chimera — and presented it to industry at the ESSERC conference (Spain). The methodological key is “cross-layer design”: rather than developing AI algorithms, processor architecture, memory systems, and circuit design independently in separate layers, they are jointly optimized, balancing accuracy, programmability, processing speed, silicon area, and energy consumption early in the design process. Architecturally, Chimera combines programmable RISC-V processors with dedicated AI accelerators, the latter covering memory-centric computing and neuromorphic computing techniques, with the goal of reducing the energy cost of data movement at the design source. The team emphasizes that validation is based on a taped-out prototype chip rather than simulation, measuring energy efficiency, throughput, latency, area, and accuracy on real AI workloads and comparing against existing designs. The team is led by Manil Dev Gomony, Henk Corporaal, Sander Stuijk, Marc Geilen, and others, with collaborators in Leuven, Delft, and Zurich. The project’s motivation is that GenAI workloads are driving up data-center energy and water consumption, while on-device local inference can simultaneously reduce energy, latency, and dependence on remote infrastructure; the authors position it as “Europe’s autonomous solution for edge intelligence processors.” Significance: this item fills in specific silicon-level progress from the European academic camp in the RISC-V + novel AI acceleration (memory-centric/neuromorphic) direction, offering a contrast to industry-side RISC-V AI chips.

III. Domestic Team Updates and Deep Dives

3.1 Nuclei Initiates Beijing Stock Exchange Listing Coaching Filing: First-Tier RISC-V CPU IP Player Races Toward Capital Markets (09-10)

Date: 2026-09-10 (company announcement disclosure date)　Source: Tongbi Finance (reposted by Sina Finance), Poker Finance

Nuclei Zhirong Semiconductor Technology (Shanghai) Co., Ltd. (securities abbreviation “Nuclei,” securities code 875127) disclosed on 09-10 the “Announcement on Filing for Coaching for Public Stock Issuance and Listing on the Beijing Stock Exchange and Its Progress”: the company signed a Beijing Stock Exchange listing coaching agreement with China Merchants Securities on 09-08, submitted coaching filing application materials to the Shanghai Securities Regulatory Bureau on 09-09, officially launching its Beijing Stock Exchange listing process. Founded in September 2018 and headquartered in Pudong, Shanghai, the company’s main business is RISC-V CPU IP licensing, SoC subsystem platform licensing, and chip customization. It is a national-level key “little giant” enterprise specializing in niche sectors and a vice-chairman unit of the China RISC-V Industry Alliance, with founder Hu Zhenbo controlling a total of 42.50% of voting rights. Its product system comprises four general-purpose CPU IP product lines—N/U/NX/UX—plus three specialized lines: NS (security), NA (automotive-grade), and NI (intelligent computing). Among these, UX1030H is one of the world’s earliest high-performance RISC-V CPU IPs supporting the RVA23 specification, and NA900 is the world’s first RISC-V CPU IP to pass ISO 26262 ASIL-D automotive-grade certification; it has cumulatively obtained 93 domestic granted patents (92 invention patents). According to the core shipment metric in The SHD Group’s March 2026 report, Nuclei ranks in the top four of the global RISC-V CPU IP market as a first-tier player, with over 300 formally licensed customers domestically and internationally, covering listed companies and state-owned enterprises such as GigaDevice, VeriSilicon, Bestechnic, and Amlogic. Financials: 2024/2025 revenue of RMB 73.9987 million / RMB 82.9411 million, with RMB 36.8745 million in the first half of 2026; 2024/2025 net profit attributable to parent of RMB -86.4673 million / RMB -95.9378 million, with losses excluding share-based payment effects narrowing from RMB -17.2273 million in 2023 to RMB -9.5863 million in 2025; cumulative R&D investment over the most recent two years reached 124.48% of revenue. The company was listed on the NEEQ Innovation Tier on 2026-08-28, concurrently raising approximately RMB 42 million through a targeted issuance for RISC-V chip customization platform R&D projects, with subscribers including industrial capital such as Heilongjiang Zhenxing Advanced Manufacturing Industry Private Equity Fund and SMIC Xicheng (Beijing) Digital Technology Fund, and plans to submit issuance and listing application documents to the Beijing Stock Exchange within 12 months of listing as scheduled. On industry data, the announcement cites SHD Group: global RISC-V SoC shipments in 2025 were approximately 6.9 billion units, expected to grow to approximately 36 billion units by 2031, a compound annual growth rate of 31.7%. Deep-dive perspective: Nuclei is one of the few domestic RISC-V companies with pure CPU IP licensing as its main business racing toward public capital markets; its combination of “automotive-grade ASIL-D certification + RVA23 high-performance cores + 300 licensed customers” is a key sample for observing the commercialization maturity of domestic RISC-V IP; the Nuclei GitHub organization (Nuclei-Software, 42 repositories) previously tracked in daily reports had no dedicated pushes during the window, and this update is on the capital markets rather than the code side. (Financial and market data are derived from company announcements and third-party report citations; refer to formal disclosure documents for accuracy.)

3.2 SOPHGO SG2044: UEFI Multi-Architecture Emulator Memory Allocation Strategy Adjustment (09-10)

Date: 2026-09-10 (15:20 Beijing time)　Source: GitHub sophgo/MultiArchUefiPkg, sophgo/sophgo-edk2

SOPHGO continues to advance its SG2044 firmware stack: MultiArchUefiPkg merged Emulator: force emulated allocations below 4GB on 09-10 at 15:20, forcing emulated allocations into the address range below 4GB for the multi-architecture UEFI emulator—an address space compatibility hardening measure when running heterogeneous UEFI images on the RISC-V platform. In the same organization, sophon-demo added a Qwen3_5 fixed text prefix KV cache demo on 09-10 at 14:43 (targeting image-change-type workloads); this repository targets BM168x series TPU inference rather than the RISC-V CPU mainline, and is recorded here as an ecosystem reference. During the window, sophgo-edk2, zsbl, and linux-riscv had no new commits (most recent on 09-09). Background: SG2044 is SOPHGO’s first RISC-V platform for servers/workstations; continuous iteration of UEFI (edk2) and zero-stage boot (zsbl) is a necessary condition for its transition from “able to boot” to “usable as a general-purpose computing platform”; limiting emulated allocations below 4GB is a typical firmware portability issue, reflecting that the stack is still filling in compatibility details.

3.3 SpacemiT: K1-Series U-Boot Merges k1-release into k1-bl-v2.2.y Boot Branch (09-10)

Date: 2026-09-10 (11:01 Beijing time)　Source: GitHub spacemit-com/uboot-2022.10, spacemit-com organization

SpacemiT merged Merge branch 'k1-release' into k1-bl-v2.2.y in spacemit-com/uboot-2022.10 on 09-10, merging changes from the K1-series release branch into the v2.2.y bootloader branch. Combined with the repository’s earlier commits on DDR training parameter tuning, LPDDR4/4x frequency point replacement (1600/3200 MTPS changed to 1066/2133 MTPS), MIPI DSI generic short write command support, and SPI-NOR flash ID expansion (ZB25LQ128C), it can be judged that K1 platform boot and memory initialization are still being continuously hardened, with v2.2.y being the production-oriented boot maintenance line. Another mainline in the same organization is embedded AI: the onnxruntime fork was pushed on 09-10 at 22:46, while the most recent substantive updates to ai-sdk and model_zoo_rl were on 09-09 (reported in the previous window, including inference cancellation and YAML provider selection), so SpacemiT’s substantive progress in this window is mainly boot/branch merges. Background: K1 is SpacemiT’s first mass-produced RISC-V AI CPU, and K3 is the world’s first mass-produced RISC-V AI CPU compliant with the RVA23 specification (60 TOPS); the company previously disclosed completion of R&D on its new-generation coherent interconnect bus N200, forming three major segments: general computing (X60/X100/X200) + intelligent computing (A60/A100/A200) + interconnect (N200).

IV. Embodied Intelligence and Robotics Special Chapter

4.1 SpacemiT docs-ros: Robot Perception and Navigation Documentation Update, Cleanup of Placeholder Pages (09-10)

Date: 2026-09-10 (08:51 and 09:23 UTC, i.e., 16:51 and 17:23 Beijing time on the same day)　Source: GitHub spacemit-com/docs-ros

SpacemiT’s ROS documentation repository docs-ros merged two commits during the window: on 09-10 it merged docs(robot): update perception and navigation (#204) (updating the robot perception and navigation chapter), followed by docs: remove placeholder camera and OTA pages (#205) (removing camera and OTA placeholder pages, a documentation quality cleanup). This repository is the external entry point for SpacemiT’s K1/K3 platform ROS 2 and robotics development documentation; previous records show a stable iteration cadence: 07-31 update to the perception grasping pipeline (Linksee), 08-02 addition of Gemma4 ASR guidance, 08-03 supplement to RealSense udev configuration, 08-10 update to robotic arm ONNX deployment, 09-02 addition of MuJoCo pipeline and qwen-sar backend. Significance: robotics is another clear product line for SpacemiT beyond “RISC-V + edge AI”; its documentation update frequency (over a dozen commits in the past six weeks) is higher than most domestic RISC-V vendors, reflecting that the K3 platform’s ROS/embodied intelligence software stack is still in an intensive polishing phase, directly corresponding to the user’s focus on “RISC-V × embodied intelligence (VLA/VLM local inference, ROS deployment).”

V. Summary and Trend Observations

  1. The “real silicon” narrative for high-performance RISC-V cores is heating up: NextSilicon has disclosed Arbel (dual-core 2.4 GHz, CXL/PCIe Gen5/CHI NoC, running Linux/Ubuntu and GCC/LLVM, with a roadmap toward a 64-core server-class chiplet), explicitly basing its argument on “CPUs becoming critical again in the agentic AI era.” Compared with the existing SiFive, Ventana, and Rivos approaches, Arbel’s distinctiveness lies in being a CPU that “grew out of” accelerator companion requirements, indicating that the driving force behind data center RISC-V is expanding from “replacing general-purpose CPUs” to “host-accelerator co-designed system integrity.”
  2. The open-source core camp is entering a structural convergence phase: After a consecutive week of vector instruction feature merges (whole-register moves, vfmac/widen, VIDiv), XiangShan performed consecutive wrapper-layer removals (VFAlu/VFMA) and control signal cleanup (VPUCtrlSignals) from 09-09 to 09-10, and fixed vxsat write-enable propagation. This is a typical “structural cleanup after feature rollout,” usually a precursor to the next phase (matrix/reduction operations or performance tuning).
  3. Domestic RISC-V IP commercialization is entering a capital validation phase: Nuclei has initiated filing for listing guidance with the Beijing Stock Exchange, another move in the capitalization of domestic RISC-V companies following ESWIN Computing’s bid for a Hong Kong listing. The two have different business models (Nuclei is CPU IP licensing, ESWIN is chip products) and can serve as mutual references; Nuclei’s differentiation is built on “automotive ASIL-D + RVA23 high-performance cores + 300 licensed customers,” but R&D spending over two years at 124.48% of revenue and continued losses after excluding share-based payments indicate that the profitability inflection point for the IP licensing model has not yet arrived.
  4. RISC-V promotion in automotive is shifting toward “long-term economics”: riscv.org published a contributed piece by the CEO of MIPS, shifting the automotive RISC-V selling point from performance benchmarking to “freedom of choice and software reuse over a platform lifecycle of ten-plus years,” echoing the previous day’s industry move by GlobalFoundries/MIPS to launch the Acies edge AI inference platform, showing that this camp is attacking the automotive-grade market with an “economic control” narrative.
  5. Edge AI acceleration and RISC-V are converging on the academic side: TU/e’s CONVOLVE/Chimera uses a cross-layer design of RISC-V programmable cores plus memory-centric/neuromorphic accelerators, taking “reducing data movement energy” as its primary goal and completing prototype chip measurements; DAMO XuanTie simultaneously fills in the RVV quantized operator microkernel library (torq-tile) on the open-source side. One end is architectural innovation, the other is operator engineering implementation, jointly supporting the practical usability of RISC-V in edge AI.
  6. On the day, domestic vendors’ code-side activity was mainly convergence maintenance: Sophgo’s SG2044 firmware added compatibility for address allocation below 4GB, and SpacemiT merged the K1 boot branch and updated ROS robotics documentation—both stability and documentation quality work, with no release-level new developments; the DAMO XuanTie torq-tile RVV quantized operator batch (merged 09-07) is the newly discovered content in this window.

Limitations: NextSilicon Arbel’s performance descriptions (2.4 GHz dual-core test chip, 64-core production plan, microarchitecture choices) all come from the company’s own blog, with no third-party evaluation or SPEC-level data to corroborate them, and its “server-class” positioning must be judged by actual production silicon; the MIPS contributed piece is a Viewpoints article, with views attributed to the author and MIPS, not representing the position of RISC-V International; TU/e Chimera’s specific energy-efficiency figures must be based on the ESSERC paper and publicly available project materials, and this item is based on the university’s news and project site descriptions; Nuclei’s financial and market data are sourced from company announcements and paraphrasing of The SHD Group reports, and investment-related content does not constitute advice; the code activity of XiangShan, XuanTie, Sophgo, and SpacemiT is based on commit messages and repository pushed times, without microarchitecture-level verification; no new commits were seen in torq-tile’s pushes within the window (possibly branch/metadata operations), and its description is based on the 09-07 merge batch.

Appendix: Source Verification Table and Full Source List

Source Verification Table

Source Verification Result
fetch_news.py 24-hour candidates (9 items) 1 valid: NextSilicon/Arbel (Japanese re-citation, actually an English blog); 1 riscv.org automotive feature (included); CPython Tier 3 (infoq, a repost of the 08-24 announcement, already reported on 08-25/09-01, excluded); 4 cryptocurrency post-quantum cryptography items (LayerZero/ForkLog, Vitalik/Decrypt, etc., unrelated to RISC-V, excluded); the grain series of low-star repos and wireguard-fpga (FPGA implementation, not RISC-V, excluded)
gnews English queries (“RISC-V” when:1d/3d, RISC-V AI/automotive when:3d, SiFive/Andes/StarFive/Milk-V/SpacemiT/SOPHGO/RISC-V Summit when:7d) Valid: NextSilicon Arbel, TU Eindhoven CONVOLVE (included in 2.3); old news/duplicates: CPython (already reported), GigaDevice podcast (already reported on 09-09), Quintauris (already reported on 09-09), Qualcomm Dragonwing Q-2390/IQ-2390 (released 09-01, already reported 09-02; this issue’s 09-10 piece is a standard watch analysis, excluded), GlobalFoundries MIPS Acies (around 09-08, same camp as 2.2, used as background); irrelevant noise: Decrypt/ForkLog post-quantum cryptography, coffee/dairy e-commerce articles matched by Milk-V (35 items, all excluded), Chilean glacier warnings and Colombian agriculture matched by Andes (excluded), zero valid hits within the window for StarFive/SpacemiT/SOPHGO/SiFive
gnews Chinese queries (XuanTie/DAMO, XiangShan/open-source processor, Nuclei, ESWIN, RISC-V chip when:2d/7d) Valid: Nuclei Beijing Stock Exchange coaching filing (included in 3.1); excluded: ESWIN “third Hong Kong IPO attempt” (verified as a re-forward of an old 2026-08-02 Beijing Business Today article; the original filing event was 07-31, already reported on 08-25); noise: XuanTie matched wuxia novels, DAMO matched MIIT AI case studies and gambling SEO articles; XiangShan matched the Beijing Xiangshan Forum/Xiangshan Co. shareholder reduction (not the same entity); RISC-V chip matched gambling and stock market articles (“Yabo Youyuehui platform chip”, etc.)
HN (Algolia, 24h) 2 items: NextSilicon Arbel (5 points, included in 2.1), ServeTheHome Hot Chips RISC-V recap (09-09, already reported in the previous window, excluded)
RSS (CNX / LinuxGizmos / Phoronix / riscv.org) Only one new article from riscv.org (MIPS feature, included in 2.2); the other three had no RISC-V keyword hits within the window. CNX’s YuzukiNeko Allwinner F101 report was 09-08/09-09 (outside the window and a follow-up on a Pico-form-factor SBC), not included
GitHub organization scan (7: OpenXiangShan / XUANTIE-RV / spacemit-com / Nuclei-Software / sophgo / revyos / eswincomputing) Active: XiangShan family (8 repo pushes, included in 1.1), spacemit-com (including docs-ros robotics documentation and U-Boot merge, included in 3.3/4.1), sophgo (MultiArchUefiPkg, included in 3.2), XUANTIE-RV (torq-tile push, included in 1.2); quiet: Nuclei-Software (last 09-04), revyos (last 09-07), eswincomputing (last 07-14, zero pushes within the window)
GitHub active project search (topic:risc-v pushed:>2026-09-09) Activity within the window was mainly routine progress on large open-source projects (chipyard, cva6, riscv-unified-db, tock, simdutf, DietPi, arduino-pico, etc.), with no release-level dedicated events; most newly added low-star repos are teaching-oriented emulators (emulsiV, rv64-vm, RISC-V-emulator-Native, etc.) and Teleport’s unofficial riscv64 build, not included

Full Source List

No. Event Source Link
1 XiangShan vector pipeline convergence and companion repo pushes XiangShan commits, Dashboard, XSCache, XiangShanLab, GEM5, extention-xspdb
2 DAMO XuanTie torq-tile RVV microkernel library GitHub XUANTIE-RV/torq-tile
3 NextSilicon Arbel RISC-V CPU NextSilicon blog, Hacker News
4 MIPS automotive RISC-V feature riscv.org
5 TU/e CONVOLVE / Chimera chip TU/e official news, Bits&Chips, CONVOLVE
6 Nuclei Beijing Stock Exchange listing coaching filing Tongbi Finance (Sina Finance), Poker Finance
7 Sophgo SG2044 UEFI emulator adjustments sophgo/MultiArchUefiPkg, sophgo/sophgo-edk2
8 SpacemiT U-Boot branch merge spacemit-com/uboot-2022.10
9 SpacemiT ROS robotics documentation update spacemit-com/docs-ros

Data source: Daily RISC-V Global Intelligence Brief (2026-09-11 issue). Google News aggregation channel access; GitHub organization and commit searches completed via the GitHub API, with queries under unauthenticated rate limits merged at the organization granularity.