Reporting period: October 19, 2026 (Monday) to October 23 (Friday), 5 working days in total Sources: 5 issues of this publication’s daily TileLang Community Update (10-19, 10-20, 10-21, 10-22, 10-23); the combined collection window of the five issues spans 10-16 07:00 to 10-23 07:00; supplemented by an additional 168-hour window review of 29 repositories in the tile-ai organization and verification against each repository’s releases page, tags, and VERSION file (see appendix)

I. Weekly Highlights

  • TileFoundry 0.0.3 released, handing instruction-level scheduling to an agent; on H200, Qwen3.8-27B prefill beats SGLang across all three tiers (10-21): v0.0.3 was tagged at 10-21 10:26, published to PyPI as tilefoundry==0.0.3, codenamed “Agent-driven scheduling”. The core change is where scheduling authority resides—the compiler lists which instructions can implement each HIR operation and what each requires, the agent selects among the candidates, and the compiler then lowers the chosen schedule to TIR; the accompanying CLI adds schedule candidates and schedule facts, instructions are declared as AtomSched operations with explicit TIR operand contracts, starting from CUDA MMA atoms, SM90 WGMMA, and async copies. Performance figures come in three real sets: Qwen3.8-27B prefill on a single H200 at 1024 / 4096 / 8192 tokens takes 80.29 / 309.61 / 631.19 ms respectively, versus SGLang’s 89.06 / 317.11 / 638.25 ms; for short sequences of 128 / 256 / 512 / 1024 tokens it is 1.88 / 1.41 / 1.10 / 1.03× SGLang. Two known issues: the wheel does not yet package CUDA runtime headers (CUDA kernels cannot be built from the installed package and require a source checkout; fixed next release), and the performance timeline mis-prices insert_slice and tf.zeros across mesh positions (#239).

  • SemiAnalysis devotes a dedicated chapter to TileLang Ascend: of six Ascend-supported repos, only TileLang was usable at time of writing (10-21 ~ 10-22): The 10-21 piece “The Huawei-DeepSeek Symbiosis” lists in its subtitle Huawei Ascend 950PR microbenchmarks, DSv4.1 Flash analysis, DeepSeek’s Ascend support, AICPU, and TileLang Ascend. Three points bear directly on TileLang: first, of the six repos with Ascend support (TileLang, DeepGEMM, DeepEP, TileKernels, FlashMLA, DeepSelect), only TileLang was usable at time of writing, because CANN 9.2.0 has not been released and DeepSeek requires CANN 9.2.0 plus a C++20 compiler, which 9.2.0-beta.2 does not provide; second, the Ascend 950 backend has been merged into the TileLang main repo rather than living only in a separate port repo, providing native compilation, scheduling, synchronization, and runtime integration, with AutoSchedule deciding overlap and on-chip buffer slot counts from data dependencies and estimated execution time, cutting up to 40% for small single operators on 950PR; third, against CANN and Triton-ascend, “some sizes can match or exceed CANN,” with the best implementation switching by size (the author notes these are naive benchmarks under warm cache). The article also flags ecosystem gaps: most optimizations target superpods, and vLLM-Ascend 0.26.0rc1 still has multiple issues on x86 hosts. On 10-22 the South China Morning Post’s “Jensen’s nightmare” relayed the same report—second-hand coverage that constitutes no new technical progress, but shows the judgment is entering mainstream media framing.

  • Main repo completes three rounds of correctness hardening in one week, with defect types expanding from “wrong numbers” to “wrong target” and “compile-time state corruption” (10-19 ~ 10-23): Round one cleared warp specialization and pipeline geometry—#3503 makes every thread in a pure-TMA producer arrive at the forward barrier (fixing the parity hang in #3470), #2342 makes sibling pipelines expand a shared buffer only once (fixing the 4-D LayoutInference crash in #2309), #3536 adds thread offsets to T.cumsum on shared buffers, and #2822 preserves transitive copy dependencies. Round two cleared silent numerical errors—#2818 requires explicit K padding for unsupported MMA tiles (previously the K atom was silently shrunk), #2815 fixes a crash in (64,1) keep-dim reductions, #3550 rewrites TIR predicates in step with integer bit-width promotion, #3070 fixes batched finalize_reducer reducing only the first output block, #3350 pre-validates the source/target/rounding combinations of casts, and #2860 makes a CUDA target without an arch error out instead of silently defaulting to sm_50. Round three cleared compile-time state—#3579 brings nonzero loop lower bounds into vectorization analysis (10 files, +818/-198, closing #2669 and #2616), #3612 clones the analyzer before vectorization rewrites, and #3226 fixes stale analyzer bindings after parallel loop splitting. What the three batches share: no errors are raised, and untrustworthy results appear only at specific sizes or loop shapes.

  • Ascend line shifts focus to training backward and low-level data paths, merging 11 port-repo PRs in a week and opening sparse_mla in both directions (10-20 ~ 10-23): Training-side operators landed in a cluster—#1887’s indexer_bwd (+1294, serving DSA sparse fine-tuning, supporting both AscendC and PTO backends, with fast, general, and cast kernel tiers), #1877’s SiTU-GLU backward (+854, semantically aligned with CANN’s aclnnSituGluGrad, used for Kimi K3 Stable LatentMoE gated activation backward, cross-checked against the official aclnn on 910B3 with max relative error around 3e-3), #1892’s LSTM (+2304, 12 jit kernels, supporting multi-layer stacking, bidirectionality, and LSTMP projection), and #1902’s GRU (+2267, 8 kernels, with AUTO_SYNC manually disabled to avoid roughly 58 PipeBarriers per time step). The review queue then adds sparse_mla forward and backward (#1929 / #1928), GLM-5.3’s kpool compression (#1910), and the WY fast series (#1827 et al.). On the data path side, #3530 uses 18 files, +993/-256, to let compressed NZ buffers support partial UB→L1 copies with explicit C0-group row pitch; #1795 identifies that sub-32B compact row-pitch sources cannot be expressed, with the second burst measured reading element 8 instead of element 1, fixing garbled keepdim reduce output; #1903 makes JIT cache publication atomic and restores the cache when it has been deleted.

  • TileOPs merges 68 PRs in a week, with SM89 and SM90 as parallel mainlines and specs and benchmarks both reporting 205/205 (10-19 ~ 10-23): The org stats branch, after 20 merges on 10-18 alone and 44 in the window, refreshed to “205/205 implemented, 205/205 benchmarked,” both at full coverage. On the SM90 side, six warp-specialized kernels were added in a week—paged GQA forward (#2668), FP8 lightning indexer with dual consumer warpgroups (#2666), MLA decode staggered seesaw (#2665), dense prefill persistent traversal (#2706), dense GQA decode (#2694), and causal sliding-window band (#2696). The SM89 side filled gaps for consumer and single-GPU scenarios: block-scaled FP8 grouped GEMM (#2659) and INT8 W8A8 (#2655) landed the same day, FP8 BMM’s default tile changed to 64×64 (#2681, 1×16×64×128 dropping from 5.161 to 3.799 us), W4A16’s M upper bound extended to 64 (#2672, with M=17 / 32 / 64 down 43.35 / 47.20 / 40.00 percentage points), paged DSA implemented with MMA (#2669, 0.269 ms versus 0.727 ms for the PyTorch FP32 reference), and NSA top-k extended to 2048 compressed blocks (#2675). Two NaN fixes in the same period both occurred on warp-specialized paths: an incorrect shared-memory liveness check (#2708) and FMA fusion overflow under fast math (#2699).

  • PTO moves from “separate execution path” to “auto-vectorization + default execution backend” (in review, since 10-18): The main repo’s PTO vectorization framework #3512 lets users write scalar-parallel T.Parallel (elementwise, control flow, reductions) inside T.SimdVF(lanes=L), which the compiler vectorizes into PTO VMI instructions that run on Ascend 950 after compilation through PTOAS; scale grew from 44 files and 18,988 lines on 10-18 to 50 files and 21,022 lines on 10-21; #3516 proposes resolving target="pto" with execution_backend="auto" to tvm_ffi and making it the default. Merged supporting work is a string of storage, predicate, and reduction semantics fixes: T.alloc_ss in #3514, SimdVF dim=1 reduction in #3437, PTO integer signedness in #3582, predicate exponential growth in #3581, and SIMT vector local variable allocation in #3523. The main repo also uses #3511 to add explicit pitch for L0 local copies on the AscendC side (24 files, +1458/-187, letting one GEMM tile be assembled from multiple copies)—the two paths advance in parallel rather than replacing each other.

  • Second instance of downstream distribution form: Sunrise opens a 0.1.15+sunrise.1.2.0 release PR (10-22): #9 created branch candidate/sunrise-0.1.15-1.2.0-20261019 at 10-22 16:48 and opened a PR updating the Sunrise distribution to 0.1.15+sunrise.1.2.0, incorporating TileLang 0.1.15 and the accompanying reviewed TileOPs, TileKernels, TVM, and tvm-ffi changes; source import and merge are committed separately from distribution adaptation, with the final wheel adapting the TANG backend and fixing a sliced GEMM regression. Self-reported validation: 55 local contract tests pass, 54 TANG pipeline codegen tests pass, two lint jobs and the trust-boundary check pass; however, after the S2 wheel was built, the post-install import smoke check failed at tangGetDeviceCount. The PR is not yet merged.

  • Several new community repos appeared in a week: a Chinese systematic tutorial, a CANN community operator repo, an agent workflow, and a Hexagon backend experiment (10-20 ~ 10-22): huandu/tilelang-tutorial was created on 10-20, positioned as a “from zero to one TileLang Chinese systematic tutorial” covering operator authoring, compile-time mechanisms, and both the NVIDIA and Ascend backends—the first appearance of a structured Chinese tutorial repo; Atlas-Ascend-Fork/ops-tilelang was created on 10-20 as a CANN community operator asset repo for Ascend NPUs (unified management of kernel implementations, automated tests, standard workloads, and performance baselines), with its first fix pushed on 10-22; tilelang/agent was pushed on 10-22, its README itself an executable prompt template that injects domain knowledge via @tilelang-operator-dev/SKILL.md and walks operator optimization through a ten-step loop; also SoilSoi1/tilelang-hexagon (created 10-20, a community experiment for the Hexagon backend), echoing the main repo’s in-review #2155 Hexagon HMX backend support.

II. Core Project Progress (Main Repo tilelang)

Versions and Releases

  • The main repo’s latest tag and release remain v0.1.15 (released 09-30), with no new tags and no new release-page entries all week — 23 days as of this Friday. The VERSION file still reads 0.1.15, and the README’s latest milestone remains the 09-30 Ascend 950 backend.
  • TileFoundry 0.0.3 is the only new version this week (10-21 10:26) and the first new tag in the org since 09-30. Adaptation-line tags did not move all week: MetaX v0.1.14 (09-17), Moore Threads v0.1.15+musa.1 (09-30), MLIR Ascend v0.1.2.020.sglang.poc (09-09), Ascend v0.1.2.000.
  • Downstream constraints remain stuck between 0.1.12 and 0.1.15: TileOPs’ pyproject.toml still hardcodes tilelang==0.1.12, and the 10-18 attempt to upgrade to 0.1.15, #2554, was closed without merging. The PR’s stated blocker is that 29 smoke tests passing on 0.1.12 fail on 0.1.15: 28 stem from T.Pipelined with dynamic extents leaving ptx_wait_group(3 - t * 2) at the cp.async epilogue, causing a Downcast failure in CUDA codegen; the other is LegalizeSafeMemoryAccess failing a null check under a branch folded to False. The SM89 test case merged this week ran against both 0.1.12 and the 0.1.15 dev build, indicating the upgrade gate requires dual-baseline validation.

Compiler, Language Layer, and Execution Paths

  • Windows ARM64 enters the release pipeline (#2962, merged 10-19, 12 files +356/-45): adds a PowerShell install script that pulls the CUDA 13.4 windows_arm64 local installer from NVIDIA’s pre-release channel into a fixed path, adds a FindPipCUDAToolkit module and a windows_arm64_clang_compat.h compatibility header to resolve header and builtin differences in the MSVC toolchain on ARM64, and adjusts pyproject, both requirements files and layouts, and the MSVC helper module accordingly. This is the third non-x86 delivery surface after ROCm and Ascend.
  • Lower trace splits host and device source (#3496, merged 10-19, 6 files +121/-63): the device side now emits codegen_device.cpp with an .original baseline and a .latest latest version, while the host side emits codegen_host.cpp with the same baseline structure; report.html symlinks to the most recent run. Correspondingly, #3583 under review (13 files +106/-4390) removes the lower trace implementation, its dedicated environment configuration, and related tests from the main repo entirely, keeping only the shared compiler instrumentation interface so the tracing tool can evolve independently.
  • CUDA 16-bit math lowering completed (#3172, 3 files +463/-8): asin, acos, asinh, acosh, atanh, log1p, atan2, hypot, copysign, ldexp, and nextafter lacked CUDA-specific lowering rules, leaving float16 and bfloat16 calls unhandled at codegen. The fix registers them in CUDAMath and adds half_t and bfloat16_t overloads: the ten operators evaluate in float32 and convert back, and nextafter steps via integer comparison on the 16-bit encoding to preserve bfloat16 subnormals under fast math.
  • Eager frontend preserves Python source locations (#3558, 4 files): maps generated loop calls back to for statements and context wrappers back to with statements, and adds locations for iterable argument unpacking, fixing traceback and coverage misalignment.
  • BF16→FP32 vectorized conversion switches to inline PTX (#3595, 4 files +19/-7): adds a paired-lane f32x2 conversion replacing per-lane scalar promotion, retaining support for lane widths 2, 4, and 8, with unchanged semantics and only the instruction sequence modified.
  • Unroll pass and ROCm Select (#2887): loop unrolling no longer eliminates stepped loops with a trip count of 0, and vectorized Select on ROCm lowers per lane, avoiding whole-group lowering failures on unsupported targets.
  • Softmax split across a 16-CTA cluster (#2632, merged 10-18): adds a kernel for few-row, long-row shapes like lm-head (4×102400). The old implementation exchanged (max, sum) per row across 58 segments via global memory and a cross-grid barrier; the new one spreads a row across the registers of a 16-CTA cluster, exponentiates each element only once, and folds max-first via a shuffle tree across warps, CTAs, and the cluster.
  • Under review: besides the two PTO items, [Transform] Locate VerifyBufferInit reads outside tile ops (#3620), [Codegen] Add unsigned mulhi intrinsic (#3617), [Transform] Keep assumption checks with local dependencies in scope (#3611), [Transform] Preserve tl.assume predicates that simplify to true (#3610), and [CPU] Support clz in C and C host code generation (#3609) were updated in the window; the mixed-sign shift fix in #3597 was submitted in tandem with #87 in the tile-ai/tvm fork, while #86 backports an upstream loop-scope fix. The fork has 25 open PRs and the main repo 163; the collaboration path of TIRx leading and the main repo following appeared for the second time this week.

Correctness and Bug Fixes

  • 10-16 to 10-18 (the three-day Monday window): pure TMA producers are brought into the forward barrier (#3503 — producer warps 1 through 3 wait only on the backpressure barrier, can lag by two phases, and hang the entire block on a reused parity); sibling pipelines sharing a buffer are unrolled only once (#2342 — fixes two T.Pipelined loops sharing a buffer with different num_stages, where a four-dimensional (4,2,64,32) triggered a LayoutInference ICHECK); three Profiler fixes (#3559 cross-device CUDA Graph capture coming out empty, #3560 subsequent calls overwriting the previous snapshot output, #3561 excluding cache-flush time from the early-stop criterion).
  • 10-19: T.cumsum on shared buffers gains a thread offset under warp specialization (#3536, 4 files +101/-38, introducing thread_offset into both the CUDA and HIP scan templates); bare data variables in call_extern are conservatively marked as written (#2618, adding 69 lines of test cases covering “call_extern writes the output buffer” — the direction is to under-optimize rather than mis-optimize).
  • 10-20: vectorization analysis accounts for nonzero loop lower bounds (#3579, 10 files +818/-198 — the original implementation implicitly assumed loops start at 0, so with a nonzero lower bound unit-step vectorization computed different lanes’ addresses as the same group); cross-thread WAW detection on shared memory now uses two thread instances (#2821, 3 files +153/-19 — the old WAW check reused the same thread variable for both accesses, missing conflicts and omitting barriers); unsupported MMA tiles now require explicit K padding (#2818 — FP16 K=8 produced wrong results, and irregular sizes like K=20 / 28 now fail directly at layout inference); fragment reduce supports retained-dimension targets (#2815, 8 files +343/-63); TIR predicates are rewritten in sync with integer bit-width promotion (#3550, 4 files +950/-27, adding IndexPredicateRewriter); CuTeDSL scan gains participating-thread offsets (#3576, 2 files +30/-6 — tl.CumSum1D(32, False, 0) previously raised a constructor argument error outright).
  • 10-21: batched finalize_reducer previously reduced only the first output block (#3070, 2 files +29/-5 — when the output dimension exceeded the batch, subsequent segments received uninitialized values; the fix emits block by block per ceil(OutputDim / batch), with 23 cases passing on L40S and zero mismatches across a 16-case external reproduction matrix); upfront validation of the source/target/rounding combination for cast (#3350 — the f32→E8M0 helper rounds toward positive infinity and does not accept a rounding argument at all, while the vectorized branch never read round); CUDA targets without an arch are rejected rather than silently defaulted to sm_50 (#2860, 1 file, fixing #1049, with the error message giving two explicit arch forms); software pipelining preserves transitive copy dependencies and lets thread domains participate in region conflict determination (#2822).
  • 10-22: clone the analyzer before vectorization rewrites (#3612, 1 file +2/-1); stale analyzer bindings after parallel loop splitting (#3226, 6 files +55/-19, touching the loop_partition, loop_vectorize, and lower_tile_op passes); out-of-bounds candidate buffer in the deepseek_v32 top-k selector (#3280, 2 files +91/-10 — tl_topk_impl packed radix candidates into a fixed [2, 4096] shared buffer without bounding the first-round threshold bucket size, so FP32 scores sharing low mantissa bits or fully identical inputs wrote out of bounds and crashed with CUDA_ERROR_ILLEGAL_ADDRESS; the fix allocates a (batch, 2, seq_len) global workspace in the tl_topk wrapper); sm8x sparse metadata with non-bijective shapes is now rejected (#3125, single file +6/-0).

Runtime, CI, and Toolchain

  • Performance regression jobs pinned to H100 (#3569, 1 file +15/-1): the org is introducing self-hosted H20 capacity machines for routine correctness CI, whose label set overlaps the existing [self-hosted, nvidia]. H20’s dense FP16 throughput is about 148 TFLOPS versus roughly 990 TFLOPS on H100 — about a sevenfold gap — so if benchmark jobs were silently picked up there, every benchmark would report a regression that does not exist. pr-regression now must carry the h100 label and verify before starting that the allocated card really is an H100, failing fast on a mislabeled runner.
  • Autotuner passes through profiler parameters (#3337, 3 lines): warmup, rep, and timeout on the decorator were not forwarded to the tuner, so user changes to these three parameters had no effect. Three other maintenance changes in the same batch: FP4 (e2m1) floating-point constant printing on ROCm (#3548, now generating constants on the device via a helper converting from float32), cibuildwheel bumped from 4.2 to 4.3 (#3565), and an additional reviewer for the ROCm line (#3567).
  • Ascend CI merged into a single check with steps (#3564, 1 file +61/-9): build and test results are consolidated into one Test for Ascend PR check, with the CANN environment set up once and built once; the AscendC examples, PTO examples, and Ascend unit tests run as three separate steps of the same job. If one suite fails, the others still run, and the overall result is still a failure.
  • Docs sites: tilelang.github.io saw 15 automated build pushes in one week (10-19 to 10-22, all triggered by main-repo merges); the TileOPs docs site had three manual content updates — eight new operators added to the API page (#76), six new operators added (#77), and two MLA backward ops added to the Attention page (#78, prompted by check_api_pages.py reporting two missing pages among the 207 ops exported by the main repo).

Review Queue Observations

  • Open PRs in the main repo fell from 167 (10-21 count) to 163 (10-22 count), TileOPs from 16 to 9, while the Ascend adaptation repo held at a high 235 to 236 — the pattern of “main repo and operator library tightening while the adaptation repo stays thick” matches last week, but TileOPs’ drop is the largest within the org this week.
  • In-window review updates across the org: 52 (10-20) → 71 (10-23). Of the 51 under review in the main repo as of 10-19, 27 are tagged [BugFix], concentrated in ThreadSync, Transform, and codegen — edge cases flowing back after large-scale use.
  • Around 11:30 on 10-20, the updated_at of 64 open PRs refreshed simultaneously; spot-checking three of them found no comments, reviews, or branch pushes at that time, so this was judged a platform-side batch recomputation and not counted as development activity; open counts are taken from each repo’s is:open count.

III. Multi-Backend Adaptation (Ascend / Hygon / MetaX / Moore Threads)

Ascend: Shifting from Operator Patches to Training Backward Passes and Data Paths

  • 11 adaptation-repo PRs merged this week: Chinese documentation for elementwise operators (#1657, completing functionality, parameters, return values, and typical usage for relu / leaky_relu / sigmoid / silu, 6 files +451/-19), indexer_bwd (#1887), SiTU-GLU backward (#1877), LSTM (#1892), GRU (#1902), Chinese version of the CrossEntropy benchmark (#1801, following the en/zh paired convention of FA and SFA), sub-32B row-stride fix (#1795), atomic publication of the JIT cache (#1903), depthwise_conv_2d example (#1915), Dilation2D example (#1916), and a same-day revert of depthwise_conv_2d (#1919, commit message gives no reason; the examples repo is in a “one in, one out” state).
  • 12 Ascend changes on the main repo side: T.alloc_ss (#3514, scalar storage shared by one AIC and two AIVs on dav-3510, 3 KiB SS pool per group, 32-byte-aligned base address), RNG state reset (#3331, avoiding a stale __asc_rng_state left by sibling kernels causing bisheng to report an undeclared identifier), SimdVF reduction storing only lane 0 (#3437), scalar sqrt outside the VF domain routed through the standard math library (#3466), PTO Ramp emitted as typed vectors (#3535), explicit pitch for L0 local copies (#3511), DeepGEMM heuristic and epilogue alignment (#3577, 29 files +1392/-1036, covering fused bias, Alpha, BF16 stochastic rounding, and FP8 quantization for dense/batched/grouped GEMM), PTO integer signedness (#3582, pto.redux_max/min rejecting typed integers, exposed via uint32 lanes ≥2^31), partial UB→L1 copy of NZ buffers (#3530), exponential growth of MAD direction predicates (#3581), SIMT vector local variables allocated per lane (#3523), and msprof host-device correlation (#3321).
  • #3321 is a structural gap-fill in measurement capability: previously the Ascend profiler could only report device kernel time, with no correspondence between host operators and kernels, so autotuning samples could not be attributed to specific calls. This PR probes CANN’s profiling headers at build time (compatible with both msprof and profiling installation layouts; enabled if installed, skipped if not, with no user-facing compile switch), adds ascend_profiling.h and a host-side profile module at runtime, and correlates host operator dispatch with device kernel execution by call order; the grouped compilation path reuses the same reporting (13 files +676/-13).
  • #1795 is the most technically substantive: the root cause lies in the template layer — copy_ub_to_gm unconditionally generates multi-burst DataCopyPad, while the MTE3 engine implements the system-level convention that “narrow UB rows are stored in 32B slots,” with the source address advancing ceil(blockLen/32) + srcStride 32B blocks per burst. For producers that write rows on 32B boundaries this is an exact match, but the (M,1) fp32 output of T.reduce_max is written compactly by the V-pipe with a row stride of only 4B, which the engine cannot express. The fix collapses to a single flat burst when both sides are packed and the total does not exceed 65535; inexpressible non-32B-multiple row strides now call trap() to abort explicitly. The reason for not falling back is that bisheng’s cross-pipe automatic synchronization only covers straight-line intrinsics; wrapping DataCopyPad in a conditional branch makes bisheng generate bad synchronization code and deadlock the device (measured: per-row DMA wrapped in a runtime branch triggers an aicore exception). The PR itself notes two remaining boundaries: sub-32B compact row strides with a strided destination still use slot stepping; and blockCount > 4095 (12-bit field) still silently truncates.
  • Review queue: sparse_mla_fwd (#1929, varlen packed random-row gather, online softmax, fused QK/PV dual GEMM, landing in examples/dsa_sparse_finetune/, with the fast path’s applicability domain hard-coded to H=128 and G=1, dim/tail of 512/64, and topk a multiple of 256) and sparse_mla_bwd (#1928, dQ GEMM chain, P/dP vector chain, dKV random-row scatter); indexer_topk_reducesum (#1917); kpool compression for GLM-5.3 (#1910); the WY fast and chunk series (#1827 / #1828 / #1802 / #1803 / #1799, clearly aimed at the training chain for linear attention and gated delta networks); plus UB-to-L1 scratch retained-block annotations and ND offsets (#1907), a fix for concurrent kernel cache publication (before #1903 merged), validation of automatic cross-core synchronization configuration (#1854), and wrong W4A4 int4×int4 results in gemm_v0 (#1731).

Hygon: Constant-Window Fix Merged, Performance Work Moves to a Branch

  • #25 merged at 10-20 09:53 (2 files +346): after loop unrolling, MLS resource promotion drops the constant-window offset, causing subsequent accesses to land in the wrong range; the fix validates the non-updated dimension before choosing between single-axis update and forward incremental addressing, conservatively reinitializes the window when necessary, and adds regression coverage on the existing MLS tests. This is the only merge on Hygon’s mainline this week, and main has been parked at this commit since.
  • Three under review: #26 handles warp partitioning for fp4 MLS (14 files +261/-144), #18 adds register pipelining and warp-diverge support (self-reports example_gemm performance approaching rocblas), and #19 covers distributed-related changes.
  • The feature branch yields reusable performance conclusions: feat/hcu-smls-b-vgpr had three pushes at 10-21 11:04 and 15:27. The 11:04 push unrolled the k-loop of the decode GEMM and returned M>96 tiles to bn96; the author’s key judgment is that “the fixed per-step overhead comes from the address chain, not the barrier” — the symbolic shared-level index (k+d) % 3 lowers to v_mul_lo_u16, v_sub_u16, and v_readfirstlane_b32 and lands on matrix_load’s address path, consuming 13% of the kernel, while T.Pipelined would emit the same two barriers anyway. The 15:27 push prioritizes splitting the wide-N middle range with M between 64 and 128 by block count, uses bm96/bn128/bk128/ns2 for gate_up with M between 64 and 96, and condenses the decode GEMM notes from 3825 lines into a 588-line two-part “results + optimization log” document.
  • On 10-22, gcy_merge_main removed the register pipelining switch (6 files +10/-24): it changes both the injection and pipeline-planning passes for HCU register soft pipelining, along with pipeline_utils.h and the language-level loop extension. Removing a switch usually means the register pipelining path is now on by default and dual-track maintenance is no longer worthwhile, but this batch is still on the merge branch awaiting landing.

MetaX / Moore Threads (MUSA) / MLIR Ascend: Silent All Week

  • MetaX: last push was on 10-16 (dev branch #161 merged main into dev, #160 fixed xfail cases for MetaXGPU); the release remains v0.1.14 from 09-17. No new commits or tags all week.
  • Moore Threads: last push was on 09-30, “Prepare public TileLang MUSA 0.1.15”; latest release is v0.1.15+musa.1, with zero commits and zero items under review all week.
  • MLIR Ascend: merged #204 on 10-19, a TVM isolation fix addressing mutual contamination between the repo and TVM’s namespaces and symbol visibility — small in scope but directly affecting link stability when multiple backends coexist; no pushes since.
  • Conclusion: all backend changes in this window come from the Ascend and Hygon lines; the other two lines remain at existing versions. This is consistent with last week’s judgment that “Moore Threads is the only backend not aligned to v0.1.15,” and this week MetaX has also gone silent.

IV. Ecosystem and Adopters (TileOPs / TileFoundry / Adopters)

TileOPs: 68 merges in one week, two hardware tracks advancing in parallel

  • Coverage: The org-spec statistics branch refreshed to “205/205 implemented, 205/205 benchmarked” after 20 merges on 10-18 alone and 44 merges in the window — both metrics at full. Operators merged this week span six categories: attention, linear attention, state space, convolution, normalization, and GEMM: MLA prefill backward op layer (#2678, aligned with FA3’s _flash_attn_backward interface), MLA backward SM90 warp-specialized kernel (#2680, D_qk=192, D_v=128), MLA paged forward (#2642), MLA KV cache write (#2635), QK-Norm-RoPE fusion (#2639, seven row/precision combinations, supporting both NeoX and adjacent-pair rotation layouts), per-token quantized RMSNorm fused residual (#2634, 12 workloads aligned with vLLM’s same-named interface), CausalConv1d dual operators (#2627, width 2 to 4, optional bias and SiLU), Hadamard transform (#2624, base_order 1/12/20/28/40, n up to 2^28), Mamba-1 selective scan (#2638, nine row workloads covering Mamba-2.8B’s 4096-token prefill and single-token decode), DSAPaged (#2633, FlashMLA’s DeepSeek-V3.2 656-byte row format), GQA paged FP8 forward (#2648, all 36 cases pass including NaN and Inf checks), dense GQA FP32 attention sink (#2515, -inf disables the sink, +inf zeroes that head’s output).
  • SM90 specialized programs appear as a group: Paged GQA forward switched to GQAPrefillPagedWSKernel (#2668, 8 files +901/-103, serving head dim 256 and query groups wider than 16 heads on a single KV head; dims 64 and 256 not covered by FP8 are read via a 16-bit mirror of the page, capped at 4 GiB per call); FP8 lightning indexer changed to dual consumer warpgroups taking turns consuming 64-key tiles (#2666, the original implementation’s single clean sweep wrote -inf outside the window at 2.5 TB/s, accounting for 425 of the 472 microseconds in chunk-prefill-kscale); MLA decode uses a staggered seesaw (#2665, one request’s keys split into min(sm_count // blocks, tiles // 2) segments then merged with log-sum-exp); dense prefill persistence (#2706, when query tile count exceeds SM count, one CTA occupies one SM and walks its tiles in alternating rounds; on D64, 192 query rows per tile are spread across three 64-row consumers, cutting K/V re-reads by one third); dense GQA decode (#2694, TMA producer warp fills a two-slot K/V ring); causal sliding-window band (#2696, one CTA loads the band’s two key/value tiles only once per “query tile, KV head”); GQA backward directly serving grouped KV heads (#2685).
  • SM89 fills in consumer and single-card scenarios: Block-scaled FP8 grouped GEMM extended to SM89 (#2659, four explicit configurations, six benchmarks including copy, cases increased from 42 to 77), INT8 W8A8 enabled on SM89 (#2655, all 13 SM89 interface cases and 29 INT8 benchmark workloads pass correctness checks against vLLM), FP8 BMM default tile reduced to 64×64 (#2681, 1×16×64×128 from 5.161 to 3.799 us, 16×128×128×1024 from 12.943 to 7.414 us), W4A16’s 64-column default M upper bound expanded from 16 to 64 (#2672), paged DSA implemented with MMA (#2669, batch 4 / 128 head / 256 positions at 0.269 ms vs. PyTorch FP32 reference at 0.727 ms; the author explicitly notes “large cases are essentially at parity, not a general advantage”), NSA top-k extended to 1024 to 2048 compressed blocks (#2675) and group48 reusing tiled programs (#2674), single-row single-column to vector GEMM (#2660, candidates filtered by shared memory budget, max staged ring 96 KiB), SSD chunk scan default pipeline stages reduced to two (#2705), paged DSA key range splitting (#2691), NSA top-k using 32-column tiles (#2690, median GPU busy reduced 2.1% to 15.0% across eight cases).
  • The fixed playbook for performance convergence: Over ten merges across the four linear attention lines GLA, GDN, KDA, and DeltaNet converge on two techniques — compressing the matrix multiplies on the chunk chain to one per block (#2626, #2645, #2637, #2625), and choosing between grouped solve and single warp based on how many warp groups an SM can hold (#2650, self-described threshold of “about seven warp groups solving per SM”); plus overlapping batched GEMM tile writeback beneath the next tile’s first WGMMA (#2636), long-row reduction switched to 512-thread folding (#2641), bypassing bf16 division when the scale factor is exactly 1 (#2646), approximate reciprocals for float32 modulo and floor division (#2652), and predicate broadcast and boolean operands switched to 16-byte vector reads (#2702 raises linear-bias-float32 six comparisons from 0.99 to 1.06, #2697 switches binary kernel full-size operands to evict-first reads).
  • Two NaN fixes and three contract fixes: The shared memory planner read each warp role’s buffers as live in different time windows, so it placed the split handover onto key or value ring addresses still being filled by TMA (#2708, 2 files +80/-30, returning NaN under the combination of “seven single-token requests queued before a 300-token request, 4099-row FP8 cache, 48-row pages”); under the causal window, the 128×64 tuned tile made the last few rows hit two consecutive fully-masked key tiles, and fast math fused prev * scale - curr * scale into an FMA whose rounding error of about 2 to the 99th power overflowed to NaN (#2699, fixed by subtracting the running maxima before the scale rescale); varlen query RoPE dropped the loop upper bound when, under odd half-rotation widths, parallelism was not divisible by the rotation branch’s thread count (#2700, the generic path simply hangs); paged decode’s autotune supply gave every request the same block table (#2703, measured MHA decode tuner on opt-1.3b-b16 picked block_N 128, i.e. a cold 80.0 us, over 72.5 us, dropping to 0.994 of flashinfer); ref_program served both as correctness reference and as the torch baseline timing target, following the input dtype (#2692, GroupNorm and InstanceNorm failed on MTT S5000; changed so the reference computes in float32 or wider).
  • Nightly pipeline and reports: #2656 adds a “new operators” column to the nightly report and switches historical data item reads from legacy string representations to JSON parsing; its self-described 10-18 report (statistics window 10-05 to 10-17) lists 109 improvements, 6 new operators, 121 rows total, of which W4A8 GEMM accounts for 98 rows. The snapshots branch took two snapshots this week at 10-19 05:41 and 10-20 05:39, after which the nightly report cadence switched to daily.
  • Queue: In-review dropped from 16 (10-21) to 9 (10-22), the only repository in the org with a clear decline in in-review count this window; the two days with 20 merges (10-21 and 10-23 report periods) both accompanied this contraction.

TileFoundry: a refactoring week before 0.0.3

  • Release: 0.0.3 was tagged on 10-21 10:26 (see Top Stories); the README’s Latest News had already gained three 10/2026 entries via #247 before 10-21 (0.0.3 release, Qwen3.8-27B prefill example, Apple AMX prefill example), with two 08/2026 entries moved into the collapsed Earlier list. The commit message notes that the README is the PyPI long description (readme = "README.md" in pyproject.toml), so announcements must land before tagging.
  • Structural refactoring: Storage plan and issue plan separated (#243, 39 files +2543/-1889, keeping raw allocation decisions in the analysis layer, removing executable alias publishing, splitting out read-only StoragePlan and IssuePlan, and fixing shared memory placement that still reserved by logical bytes under sparse physical layouts); schedule milestone corrections (#241, 314 files +53049/-69314, covering M1 through M8, migrating two Qwen examples, regenerating 31 full long groups and all 64 short TIR files); test refactoring (#246, 51 files +655/-366, reusing ccache and torch extension caches locally and in CI, with two tests switched to host-side compiled CuTe references to compare MMA layouts, replacing hand-written references and thousands of parameterized cases).
  • Cross-accelerator: Apple AMX support with the Qwen prefill example running on an M2 Pro (#244, four AMX operations incorporated, Copy and Fill can land in the Apple core and AMX executor scopes, both Qwen3-1.7B and Qwen3.5-4B complete 128-token prefill with finite output logits and next-token IDs of 1813 and 306 respectively). This is the first time the TileLang ecosystem has put a full-model inference example on a non-CUDA accelerator.
  • Device modeling and costing: Added sm_89 architecture and RTX 6000 Ada target descriptions with synchronized spec docs (#259, 11 files +392/-22), extending device modeling from Hopper to Ada; gmem costing switched to footprint and running mesh with callee dimensions bound (#258, 74 files +1128/-553, fixing #239, #252, #253; previously under-fill was invisible when only 40 of 132 CTAs were probed); the device must raise an error when it refuses to launch a kernel (#256, 7 files +69/-11; previously the launcher never read launch status after issuing a kernel, so on a single sm_89 card a test compiled against the bundled sm_90 target only showed wrong values, and only compute-sanitizer revealed cudaLaunchKernel returning cudaErrorNoKernelImageForDevice).

Adopters and distributions

  • TileKernels: DeepSeek’s adopter repo had zero commits this week, with the last push at the 10-14 v2.1.0-release merge (stars 1991 to 2005). That release explicitly requires TileLang 0.1.15, PyTorch 2.13, Ascend 950 NPU, and CANN 9.2.0 — the first downstream hard constraint on the “0.1.15 baseline,” and one that echoes SemiAnalysis’s observation that CANN 9.2.0 is unreleased.
  • FlashQLA: Qwen’s adopter repo likewise had zero commits, with the last push at the 10-14 SM120 fix (stars 732 to 737), version still v0.1.3 from 09-30. The adopter side has been silent for two consecutive weeks; momentum remains inside the tile-ai org.
  • Sunrise distribution: The 0.1.15+sunrise.1.2.0 release PR (#9) is in review; details in Top Stories. It delivers TANG backend wheels, a different distribution shape from the main repo’s CUDA / ROCm / Ascend delivery surfaces, marking the emergence of a second downstream distribution form for TileLang.
  • TileRT / tilescale / DeepStack: No commits in any of the three repos during the window (latest 09-24, 08-25, and 10-05 respectively).

V. Community, Tutorials, and Events

  • A Chinese systematic tutorial repository appears: huandu/tilelang-tutorial was created and pushed on 10-20, positioned as a “from zero to one TileLang Chinese systematic tutorial,” covering operator authoring, compile-time mechanisms, and both the NVIDIA and Ascend backends. Previously, Chinese-language material consisted mainly of single blog posts and translations of official documentation; this is the first appearance of a systematic tutorial repository. In the same week, RuneFang/tvm_tilelang_cookbook (34 stars, pushed 10-21) was also updated; it positions itself for readers who “can write some Python and have heard of CUDA but have never read compiler code,” walking from @tilelang.jit all the way to .cubin.
  • The CANN community launches an operator repository: Atlas-Ascend-Fork/ops-tilelang was created on 10-20. The repository already contains four layers—src, tests, scripts, and docs—along with OpenAtom community specification files such as OAT.xml and SECURITY.md; on 10-22 it pushed a fix for “a legal upper-bound seed combined with a test-case hash overflowing and causing CPU test failures,” and earlier commits include “replace Ascend A5 references with Ascend 950” and “sessions where the benchmark fails or is interrupted still overwrite the performance baseline.” A community-level operator repository using a single DSL as its sole implementation language has not been seen before.
  • Agent workflows take shape: tilelang/agent (created 08-28, pushed 10-22) writes its README as an executable prompt template—injecting domain knowledge via @tilelang-operator-dev/SKILL.md, with inputs limited to the operator name, GPU/CPU reference implementations, shape, and the constraints “tilelang npu delivery, Chinese delivery”; the comments state that the agent must execute in an A5 environment and, after loading, follow a ten-step closed loop. The Skill contains a selection decision tree, 8-CSV rules, L0-to-L4 strategies, and 11 pitfalls. Separately, cc-c122/TileLang-Remote-Autotuning-Agent (1 star, pushed on both 10-21 and 10-22) is also turning autotuning into a remotely drivable agent.
  • Backend experiments and toolchain: SoilSoi1/tilelang-hexagon was created on 10-20 as a community experiment for the Hexagon backend, echoing #2155 under review in the main repository; PTO-ISA/tilelangGym (created 10-14, pushed 10-20) is used to test the performance sensitivity of different benchmarks and microbenchmarks under PTO lowering; easy-tilelang/tilelang-devkit-vscode (created 10-19, pushed 10-20) is positioned for exploring lowering passes, IR differences, and CPU C JIT compilation in VS Code, consistent with the main repository’s direction of moving the lower trace out wholesale (#3583).
  • Third-party small repositories: fanyuxiao-ui/w4a16-tilelang (created 10-10, uses TileLang plus hand-written CUDA to implement GEMM and GEMV for W4A16 quantized inference on the A800), sablin39/tilelang-cuda-skills (145 to 146 stars; the author is also an active contributor to TileFoundry), localizethedocs/tilelang-docs-l10n (localization of the official documentation), flytiger-eco/tilelang-wrapper-for-sail (created 10-21, pushed 10-22; the repository name points to providing a TileLang wrapper for SAIL, with no description and no README), and chaigua/tilelang-agent (newly created 10-19). All are community-initiated, not official organizational repositories.
  • Media and academia: Multiple Google News queries in Chinese and English had zero new items in the 10-19 window and three hits in the 10-20 window (two industry reports on DeepSeek and Huawei chips, and one prime-rl 0.10.0 release post; after checking each one, no specific TileLang facts were found, so they were treated as not directly relevant); the 10-22 window had three articles centered on Huawei-DeepSeek collaboration, with only one SemiAnalysis piece containing a dedicated TileLang section; the 10-23 window had two items that were media reprints of the same report, plus one DeepSeek financing item unrelated to the topic, which was removed. Hacker News had no related discussion throughout the week; an arXiv search using TileLang as a title or abstract keyword returned 0 items in the window, and the most recent related entry remains TileSight from 07-24.

VI. Trend Observations

  • The layers of correctness hardening are progressing, not repeating at the same layer: Last week the main repo cleared “shape and geometry validation”; this week’s three segments are each different—first the geometry and barriers of warp specialization and pipelining (#3503, #2342, #3536, #2822), then silent numerical errors (#2818, #2815, #3550, #3070, #3350, #2860, #3125), and finally compile-time state consistency (#3579, #3612, #3226). The third segment is the most noteworthy: kernels generated by this class of defects may still be correct, but what the compiler tells the user and what it actually does are inconsistent; TileLang is bringing in agents to automatically write kernels, and whether compile-time state can be self-consistent will directly determine whether the agent iteration loop can converge.
  • The bottleneck on the Ascend side has shifted from operator count to the memory model, runtime boundaries, and training backward passes: Of the 11 adaptation-repo merges this week, backward and recurrent operators account for five (indexer_bwd, SiTU-GLU backward, LSTM, GRU, CrossEntropy docs); on the main-repo side, the largest is the UB→L1 row-stride expression for NZ layout (#3530, 18 files), and the highest technical density is the explicit abort when sub-32B compact row strides cannot be expressed (#1795). Add to that atomic publication of the JIT cache (#1903) and the exponential growth of PTO predicates (#3581), and the theme of this line is “keeping existing operators from failing under boundary conditions.” Combined with the CANN community spinning up a separate ops-tilelang operator repo, the division of labor becomes clear: operator assets are carried by the community repo, while the main repo focuses on backend semantics and codegen.
  • SM89 and SM90 have become two parallel hardware mainlines, and the criterion for prioritization has shifted from peak performance to availability: The SM90 direction produced six warp-specialized kernels this week, while the SM89 direction advanced six paths simultaneously—block-scaled FP8, INT8 W8A8, FP8 BMM, W4A16, paged DSA, and NSA top-k—and the PRs generally include single-GPU measurements and explicitly state “does not claim SM90 results” and “large test cases are basically on par, not a general advantage.” Ada-class GPUs (L40S, 4090, and the like) are the main hardware in the hands of domestic developers; this orientation is exactly complementary to SemiAnalysis’s point that “optimization is mostly oriented toward supernodes, and generality lags behind performance.”
  • The ecosystem layer sees more organizational activity than code activity: The main repo had no release and no breaking change this week, but outside the organization there appeared a Chinese systems tutorial repo, a CANN community operator repo, an agent SKILL workflow, a Hexagon backend experiment, a VS Code extension, and a SAIL wrapper repo; inside the organization there were TileFoundry 0.0.3’s agent scheduling, Sunrise’s second distribution form, and TileOPs’ full spec. Looking at “humans write rules, agents tune, and the repo accumulates baselines” together, the engineering division of labor on the Ascend side and across TileLang is being rearranged, while the code cadence itself is calm.
  • Analyst firms are beginning to treat TileLang as the criterion for Ascend usability: SemiAnalysis used “only TileLang among six repos was available at the time” to define the completeness of DeepSeek’s Ascend support, which illustrates TileLang’s position in the domestic-compute narrative better than any single technical blog—from an experimental DSL to the default carrier layer. The same report also gives a counter-signal: optimization is concentrated on supernodes, x86 host support remains incomplete, and there is a clear trade-off between performance and generality. SCMP’s relay shows that this judgment is entering the mainstream media narrative.
  • What to watch next issue: Whether main repo v0.1.16 is released (silent for 23 days); whether TileOPs’ 0.1.12 lock can be lifted (no new proposal seen after #2554 was closed, and dual-baseline validation remains the gate); whether PTO’s #3512 and #3516 can be merged (determining whether PTO becomes the default execution backend); whether TileFoundry 0.0.3’s wheel missing headers and the #239 pricing issue are fixed in the next version; how to handle Sunrise’s S2 wheel failure at tangGetDeviceCount; the landing cadence of Ascend sparse_mla forward and backward (#1929 / #1928) and GLM-5.3 kpool (#1910); and when the Hygon gcy_merge_main register-pipeline switch cleanup enters main.

Appendix: Sources and Verification Notes

  • Sources: Five issues of this publication’s daily TileLang community update (10-19, 10-20, 10-21, 10-22, 10-23), with a combined collection window of 10-16 07:00 to 10-23 07:00 (Beijing time). The 10-19 issue covered a three-day Monday window from 10-16 07:00 to 10-19 07:00, mainly weekend activity from 10-16 to 10-18; this report includes it as background and does not count it toward this week’s merge statistics. The four issues from 10-20 to 10-23 fall strictly within this week.
  • Merge statistics basis: 129 merges this week. By the four daily issues, the counts are 36 (10-20), 26 (10-21), 32 (10-22), and 35 (10-23). By repository: main repo tilelang 37, TileOPs 68, Ascend adaptation repo 11, TileFoundry 8, Hygon 1, MLIR Ascend 1, documentation sites 3. The 10-19 issue contains another 61 merges from the 10-16 to 10-18 weekend window, which are not included in the table above.
  • Supplementary verification: An organization-level check over the 168-hour window confirmed that 11 of the 29 tile-ai repositories had pushes during the window (TileOPs, tilelang, tilelang-ascend, tilelang-hygon, tilelang-mlir-ascend, tilelang-sunrise, TileFoundry, TileFoundry documentation site, TileOPs documentation site, tilelang documentation site, TileOPs-nightly), consistent with the per-repository conclusions in each daily issue. Organization activity after Friday 07:00 is, by convention, folded into the next daily issue; this report does not forecast its content.
  • Scope and boundaries: All performance figures are self-reported in PR descriptions or release notes (H100, H200, L40S, M2 Pro, 910B3, MTT S5000, etc.); this publication has no corresponding hardware and has not independently reproduced them. The 205/205 specification and benchmark coverage comes from badge data on the organization’s stats branch and is a project self-reported figure. Release dates are verified against repository tags and release pages; the release pages and branch progress of adaptation repos may lag. Judgments from SemiAnalysis and SCMP are third-party analysis, not official vendor statements. The statistical basis for in-review counts is not fully consistent across issues (some use the repository’s total is:open count, others use the count updated within the window); the basis is noted in the body text where cited.
  • Suggested next cycle: 2026-10-26 to 2026-10-30.

Source Verification Table

Source Verification result
tile-ai organization (29 repos) 11 repos had pushes within the 168-hour window; 129 merges this week by the four-issue basis; 52 to 71 in-review updates within the window
Main repo tilelang 37 merges this week; open PRs fell from 167 to 163; VERSION remains 0.1.15, with no new tags and no releases all week (silent for 23 days)
TileOPs 68 merges this week (plus 44 in the weekend window); in-review fell from 16 to 9; specification and benchmark coverage reported at 205/205; still pinned to tilelang 0.1.12
TileOPs-nightly Two snapshots on the snapshots branch: 10-19 05:41 and 10-20 05:39; a “New Operators” column was added to the report
TileFoundry 8 merges this week; v0.0.3 released 10-21 10:26 (the only new version this week); in-review 1 to 4
Ascend (tilelang-ascend + Ascend changes in the main repo) 11 merges and 11+ in review in the adaptation repo; 12 Ascend-related merges in the main repo; sparse_mla forward and backward in review
Hygon (tilelang-hygon) 1 merge to main (#25); 3 in review; three pushes to a feature branch pinpoint the address chain for decode GEMM
MetaX / Moore Threads / MLIR Ascend No commits in any of the three repos during the window; last activity 10-16 / 09-30 / 10-19 respectively
Sunrise Release PR for 0.1.15+sunrise.1.2.0 (#9) in review; import after installing the S2 wheel fails at tangGetDeviceCount
Adopters (TileKernels / FlashQLA) Both stalled at 10-14 with no commits all week; version requirements still point to TileLang 0.1.15 and CANN 9.2.0
TileRT / tilescale / DeepStack No pushes within the window (latest 09-24, 08-25, 10-05 respectively)
Community and third-party repos 4 new repos (tilelang-tutorial, ops-tilelang, tilelang-hexagon, tilelang-wrapper-for-sail); 5+ active (cookbook, devkit-vscode, tilelangGym, w4a16-tilelang, tilelang-cuda-skills)
Media and academia 6 hits across multiple Google News queries in English and Chinese during the window; only one SemiAnalysis piece contains a dedicated TileLang section, the rest are reprints or not directly related; no related discussion on Hacker News; 0 arXiv items in the window

Main References

Data sources: Daily TileLang community update (five issues, 2026-10-19 to 2026-10-23) and hands-on verification during this cycle; reporting period: October 19 to October 23, 2026.