Reporting period: October 12, 2026 (Monday) to October 16, 2026 (Friday), 5 working days in total, 5 daily-report source sets Source material: 5 issues of this publication’s daily TileLang updates (10-12, 10-13, 10-14, 10-15, 10-16); additionally supplemented by a 168-hour window check across 29 repositories in the tile-ai organization, item-by-item recomputation of test results from six nightly-pipeline snapshots, and review of each repository’s release metadata (see appendix)

I. Weekly Highlights

  • Main repo ROCm line closes out four consecutive days, DeepSeek new-architecture kernels become the third closing line (10-13 ~ 10-14): On 10-13, merged the 64-lane single-wave implementation of DeepSeek NSA forward/single-token decoding (#3152, +111/-2) and the LDS/VGPR budget-adaptive tiling for flash-decoding (#3149, +82/-5); in the early hours of 10-14, merged the mHC (manifold-constrained hyper-connections) pre/post-processing kernels (#3156, 2 files +83/-6, with the HIP side reworked to divide work across a full 64-lane wavefront and converting FP32 mixed weights to BF16 for MFMA) and the safe-gated KDA decoding example (#3249, +360, including a GLM-5.3-Flash TP8 specialized configuration); 10-14 also saw a 64-lane segment-width fix for cumsum/cummax (#2326). All four point to “adapting to device reality”: gfx942 wavefront size, MFMA input types, and LDS/VGPR budgets settled item by item, with ROCm support moving from “working” to “in sync with new-architecture releases.”

  • Ascend PTO elevated from “standalone target” to “first-class execution path,” NSA dual migration and rollback discipline in the same week (10-12 ~ 10-15): On 10-15, merged execution routing #3316—the combination of target="ascend" and execution_backend="pto", after execution-aware target normalization, connects directly to CodeGenTileLangPTO, while the auto path retains AscendC + TVM-FFI; the preceding example target selection #3474 (merged 10-14, removing the hardcoded target="ascend", with CI running once each for the ascend / pto dual targets) and the seven PRs under review in this window—the tvm_ffi backend, VMI vectorization, SS buffer, and partial L0 copy pitch—form the family. In the same week on 10-12, Ascend NSA Decode (#1701, +755, 28 layered tests) and NSA Bwd (#1730, +1593, 20 cases) were merged; on 10-14, three “documentation fact-check” PRs (#1612, #1676, #1681) were rolled back as a batch (#1888 through #1890) due to an exception regex mismatch on low-priority expected-failure cases, and bitwise_rshift was resubmitted as a reworked version #1893 after removing the expected-failure assertions; on 10-15, opened a fix for a silent numerical error in gemm_v0 on dav-3510 (#1900), exposing that --npu-arch unconditionally takes dav-2201, causing A5 kernels to target the wrong architecture.

  • TileOPs 52 merges in one week: Op base-class refactor finalized, MoE dual operators settled, SM89 becomes the second platform (10-12 ~ 10-16): The Op base-class refactor merged on 10-11 (#2520, 363 files, +3362/-5227, self-described as “pre-release” closure) unifies operators with and without compilation boundaries through _run_call, merges select_kernel_key/select_implementation into key_for, and derives compilation boundaries from the manifest, with the docs site following up the next day with the “Op Base Class Guide”; on 10-13 the MoE dual operators were settled the same day—masked FP8 grouped GEMM (#2521, 20 files +1788/-37, aligned with deep_gemm masked semantics) and DeepSeek grouped top-k (#2535, 15 files +1193/-69, aligned with vLLM grouped_topk and fixing the 32/132 SM scheduling issue at T=512); SM89 has been closing out in batches since 10-12 (GQA prefill/decode, GDN / DeltaNet prefill, GLA / DeltaNet backward, KDA prefill, full Norm spectrum), putting RTX 40-series and L40 / 6000 Ada-class workstations on par with Hopper on the operator-library side.

  • Six nightly baseline snapshots: correctness 1032 → 1134 (+102), benchmarks 1947 → 1989 (+42), zero failures throughout (10-12 ~ 10-16): This week’s six snapshots raised correctness cases from 1032 to 1134 and benchmarks from 1947 (52 suites) to 1989 (55 suites), all six with zero failures and zero errors, 1 skip each. The largest single-day increase came on 10-15 (+41, coinciding with TileOPs’ 16 merges); 10-16 saw two snapshots (one in the early hours and one at night), the first single-day double snapshot this week. The evaluation environment is H200, CUDA 13.2, torch 2.13.0+cu132, tilelang 0.1.12 (see the table in Chapter 4).

  • Multi-backend same-version closure: Hygon v0.1.15 upgrade lands and opens a distributed IPC line, MetaX catches up to upstream, Moore Threads silent all week (10-13 ~ 10-16): Hygon merged the full v0.1.15 upgrade on 10-14 (#20, retaining the HCU backend and adding scale-buffer layout planning for block-scaled GEMM) and established the v0.1.15-release branch; the same day, with #19 (+2577/-28, 44 files), it opened the Distributed line (unified process launcher, IPC allreduce tests, IPC GEMM allreduce examples, etc.); on 10-15, with #21, it opened and merged the block-scaled async copy layout into the v0.1.12-release maintenance line the same day; on 10-16, it merged #22 (K-major packed scale copy and native FP32 MLS GEMM). MetaX pushed main to the upstream v0.1.15 node on 10-13 (mirror #3309), and on 10-16 merged upstream main into the dev line and fixed one xfail case. Moore Threads has had no activity all week since 09-30, the only one of the four backends not aligned to v0.1.15.

  • TileFoundry ten merges in one week: sparse decoding threaded through TIR, Qwen3.8-27B prefill surpasses SGLang across all lengths for the first time, core refactor and external audit in the same period (10-12 ~ 10-16): On 10-12, merged #223 threading sparse decoding through TIR (84 files, +4424/-1543, fixing lost loop work, excessive lookup billing, and phased-update errors); on 10-13, merged the Qwen3.8-27B prefill example #229 (89 files, +38069), the repo’s first example faster than SGLang at all three lengths of 1024 / 4096 / 8192 (at 8192, scoring accounts for only 3.1% of FLOPs, with the load exceeding the H200 inflection point by 36×); on 10-15, landed the instance-slot refactor (#232, full source suite 1674 passing) and the lowering / printer contract (#233) in the same window; on 10-16, added the analysis access context (#238) and the allocation/lowering fix for issue 237 (#241). In the same window as the refactor landed, a third-party skills repo vendored TileFoundry into its workflow and listed 4 emitter bugs and 2 runtime bugs—entering the external audit period.

  • First version iteration among adopters: TileKernels v2.1.0 Ascend-side rewrite, FlashQLA fixes Blackwell sm120 (10-14): DeepSeek TileKernels v2.1.0 (16 files, +352/-382) is the repo’s first version iteration since adding Ascend support on 09-30, with changes concentrated on the Ascend side (norm_forward_asc substantially rewritten, SwiGLU forward/backward, Engram gating); the README requires upgrading to TileLang 0.1.15, PyTorch 2.13, Ascend 950 NPU, and CANN 9.2.0; Qwen FlashQLA #48 (5 files, +82/-5) fixes Blackwell sm120 forward/backward being unavailable since 0.1.13 (block_DV mistakenly changed to 128, missing aggregate_card_state), with all tests passing on RTX 5090 + tilelang 0.1.15 + CUDA 13.0.

  • Hardware matrix expands in the same week: SM121 lit up, SM120 block-scaling dual lines under review, D=256 decoding extended to SM80/SM90, CPU OpenMP grid parallelism lands (10-12 ~ 10-15): SM121 (GB10 / DGX Spark) block-scaled MMA lit up on 10-11 (#3430, measured on DGX Spark driver 580.178.04 / CUDA 13.0); previously all block-scaled MMA under sm_121a compiled to BPT.TRAP; on the SM120 side, MXFP8/MXFP4 (#3495) and the full-operand mxf8f6f4 family (#3099) were under review all week. On the consumer and workstation side, D=256 FP16/BF16 dense decoding was extended from SM89 to SM80/SM90 (#2563, with a Gemma-2B 8K cache workload, also fixing dense RoPE split ignoring softcap); the main repo merged grid-level OpenMP parallelism for the CPU backend on 10-14 (#3109) and switched Windows NVCC to cl.exe (#3510).

II. Core Project Progress (main repo tilelang)

Versions and Releases

  • The main repo’s latest tag and release remain v0.1.15 (released 09-30); no new tags and no new release-page entries all week, now 16 days as of Friday. The three most recent release-page entries are v0.1.15 (09-30), v0.1.14 (09-02), and v0.1.13 (08-03); the prior monthly cadence was broken this week.
  • Adaptation-line tags unchanged all week: Ascend v0.1.2.000, MLIR Ascend v0.1.2.020.sglang.poc, MetaX v0.1.14 (10-13 only mirrored main to the v0.1.15 node, no new tag), Moore Threads v0.1.14+musa.1; Hygon runs dual lines in parallel: the v0.1.15 mainline plus the v0.1.12-release maintenance line.
  • The counterpart to release silence is downstream constraints moving up: TileKernels v2.1.0 explicitly requires TileLang 0.1.15 or later, and FlashQLA’s sm120 fix was also validated on 0.1.15 — starting this week, the “0.1.15 baseline” becomes the de facto minimum requirement for adopters.

Compiler, Execution Paths, and Language Layer

  • PTO execution routing (#3316, merged 10-15): adds an execution-aware target normalization hook (attached at BackendContext creation); the Ascend-specific normalizer specializes native Ascend targets into PTO target variants before parsing while preserving attributes such as arch; device codegen switches to PTO_CODEGEN and target.build.tilelang_pto_without_compile; the docs give the equivalent configuration of TILELANG_DEFAULT_TARGET=ascend plus TILELANG_EXECUTION_BACKEND=pto. Tests cover context resolution, target attribute preservation, cache dispatch, and environment-variable selection.
  • PTO DeepGEMM codegen (#3330, merged 10-14): tracks tl.ascend_set_mmad_direction across control flow and encodes the effective direction into MAD instructions, rejecting MADs reachable under conflicting directions; supports incremental loads after SIMD, UB address to PTODSL pointer conversion for mixed AIC/AIV kernels, dynamic L0C→UB dimensions and strides, and int16 signed packed MX scale. Self-reported 14 of 15 DeepGEMM PTO cases pass; test_bf16_m_grouped_padding remains blocked by the PTOAS VPTO backend’s inability to legalize FP32→BF16 conversion.
  • Independent AIV execution (#3485, merged 10-14): extends Ascend AutoSchedule so AIV0 and AIV1 can perform different work under sid dependencies (alternating epilogues, dequant/epilogue split, disjoint input partitions, in-loop role switching); AssignCore is moved ahead of latency estimation and scheduling, and independent identities are established for AIV-local UB buffers and scalar state.
  • Shared C-family codegen base class (#3289, merged 10-14): CodeGenTileLangCBase unifies CUDA, HIP, CPU C, Ascend C++, Metal, and C host code generation; fixes T.import_source, T.Kernel(prelude=...), and pragma_import_c swallowing the next generated line when the source text lacks a trailing newline or ends with a backslash. Validation: 83 focused regressions pass, 405 codegen and launch suite tests pass.
  • CPU grid parallelism (#3109, merged 10-14): adds MaterializeCPUParallelGrid to turn annotated CPU grid loops into OpenMP parallel loops, with loop collapse, thread-count configuration, a minimum trip-count threshold, and allocation sinking, plus compile flags for Linux / macOS / Windows — the CPU backend gains grid-level parallelism for the first time.
  • Host IR line under review all week: #3473 unifying the CUDA and CuTeDSL execution paths and #3481 for direct Host IR JIT with native caching have seen no merge since opening on 10-10, and remain the main repo’s largest in-review direction.
  • Seven PTO-family PRs (under review since 10-15): tvm_ffi execution backend (#3516), T.Parallel to PTO VMI vectorization (#3512), SS buffer (#3514), explicit pitch for partial L0 copies (#3511), NZ buffer UB→L1 partial copy (#3530), PTO Ramp value vector emission by type (#3535), and a fix for vector local access inside SIMT VF (#3523). Of these, SS buffer merged on the morning of 10-16 (#3514, confirmed via supplementary verification after the daily-report cutoff).

Correctness and Bug Fixes

  • 10-12 (weekend window close-out): GEMM dtype whitelist (#3245, unsupported combinations rejected before CUDA codegen, bug #3004), For-loop step (#3427), JIT output index normalization pollution (#3318), popcount narrow-integer lowering (#3300, int8(-1) counts 8 bits), bit reduction allowing floating-point sources (#3332), CuTeDSL barrier election (#3400, duplicate arrival publication by multiple threads under 2D/3D thread blocks), NVRTC / CuTeDSL parameter identity (#3414).
  • 10-13: thread_storage_sync precise thread bounds (#3291, 4 files +292/-96, fixes #2954); Ascend PTODSL reduction helper vendoring (#3469, +555/-115) fixing ModuleNotFoundError under CANN Weekly.
  • 10-14: SimdVF multi-buffer T.fill (#3455, multi-buffer version dimension caused the whole-buffer fill check to reject), bisheng temp-file cleanup switch (#3461), cross-warp allreduce group misdispatch (#3494).
  • 10-15: JIT rejects unhashable compile-time parameters (#3417, preventing mutable defaults from silently reusing stale kernels, 91 pass), test compile-time elimination (#3517), governance config (#3513, CodeRabbit auto-labeling).
  • 10-16 (including items confirmed via supplementary verification after the daily-report cutoff): Ascend SS buffer (#3514), SimdVF dim=1 reduction per-row single-element store (#3437), Ascend RNG cross-kernel state reset (#3331), sibling-pipeline shared buffer double-expansion prevention (#2342), TMA-only producer restricted to warp 0 (#3503).
  • Newly opened for review in the early hours of 10-16: fix for cumsum shared buffer under warp specialization (#3536) — consumer threads are numbered from 128 while the scan template did not receive the interval lower bound, causing CumSum1D / CumSum2D to return early on consumer threads and leave the buffer unwritten; after the fix, the #3528 reproducer gets all 131072 items correct (129019 items wrong on main). Also profiler L2 read-only flush (#3534) and shared scan thread-count diagnostics (#3532).

Performance and Hardware Matrix

  • SM121 (GB10 / DGX Spark): #3430 makes tl::sm120_mma_sync_blockscaled accept both SM120 / SM121 by arch and family, gates NVF4 tests by the SM12x family, and allows sm_121 / sm_121a in the CuTeDSL TMA architecture table.
  • SM120 block scaling: MXFP8 (kind::mxf8f6f4, 1X, UE8M0) and MXFP4 (mxf4nvf4, 2X, UE8M0) extensions (#3495, +884/-51, FP32 accumulation, one scale per 32 K elements) and the full f8f6f4 operand family (#3099) remain under review.
  • ROCm: beyond the four headline items, the 10-15 scan wavefront fix (#2326) makes cumsum / cummax select segment width by target wavefront width, with 32-thread blocks excluding the 64-lane template at compile time; the CUDA scan suite passes 17 on B300.
  • SM89 batched performance policy: MLA decode selects 2/4/8/16 KV splits by batch and head-block count (#2511: single-request bf16 4k 0.158→0.034 ms, ~4.6x; 32k 1.170→0.162 ms, ~7.2x), KDA prefill tiles by 16-column value tiles (#2510: 4k/32k/64k down 22.9%/19.8%/18.5%), scan widening (#2574: 4096–16384 tokens widened from 8-value heads to 16-value heads, 19 rows 2.5%–19.7% faster).
  • Windows / Metal: Windows NVCC switches to MSVC (#3510, reproducer fixed under CUDA 13.3); ten Metal PRs (#3194 to #3210) under review, covering segmented normalized accumulators, simdgroup GEMM fragments, BF16 vector types, short-constant loop unrolling, etc.

Review Queue Observations

  • Main repo open PRs: 170 (10-12) → 168 (10-13) → 161 (10-14) → 160 (10-15) → 165 (10-16), oscillating between 160 and 170 during the week; org-wide open PRs rose from 498 (10-12) to 507 (10-13), and stood at 532 at the time of this compilation.
  • Org-wide merges and output: 109 PRs merged this week, 158 newly opened (main repo 30, TileOPs 52, Ascend adaptation repo 8, TileFoundry 10, Hygon 3, MLIR Ascend 2, MetaX 2, docs site 2; Beijing-time window 10-12 to 10-16, measured via GitHub search). In-review updates reached 172 on 10-16 alone, the week’s high.
  • The structural read continues and strengthens: main repo slimming (170 → 165), TileOPs thickening (9 → 16, then falling back), Ascend adaptation repo rebounding (230 → 237) — the pattern of “tighter merge gates, thicker review queue” held all week, with preparation during the release silence concentrated on the review side.

III. Multi-Backend Adaptation (Ascend / MetaX / Hygon / Moore Threads, etc.)

Ascend: Migration Merges, Execution Path Convergence, and Rollback Discipline

  • Migration merges: NSA Decode (#1701, 10-12, +755) implements single-core decoding (seq_q=1) via Developer mode hybrid, with explicit L1/L0C/UB allocation, 5-segment GM workspace auto-allocated via workspace_idx=[6..10], and the compiler automatically switching Cube/Vector scopes and inserting cross-core flag synchronization; 28 layered tests (L0 thresholds, L1 functionality including DeepSeek-V3 typical config D=128/S=16/BS=64, L2 exceptions and boundary special values), measured on 910B3 fp16. NSA Bwd (#1730, +1593) provides two JIT kernels, nsa_fwd and nsa_bwd_single; the backward pass follows the flashattn_bwd paradigm using on-chip direct T.copy (L0C→UB, UB→L1) to eliminate 9 GM workspaces, with 20 layered tests.
  • Rollback and redo: On 10-14, three documentation fact-check PRs (round semantics #1612, bitwise_rshift #1676, bitwise_xor #1681) were rolled back as a batch (#1888 through #1890). The reason is explained by the redo version #1893: when the daily full suite runs low-priority cases, the exception regex for expected-failure cases does not match—the actual throw is an InternalError from AscendVectorInstructionSelection rather than the asserted Compilation Failed, and since these cases are marked low_priority, CI does not execute them at the PR stage, so they are caught by the daily full run as a backstop. The redo removes all expected-failure assertions (unsupported dtypes are now covered by the documentation dtype support table), retaining the docstring rewrite and on-device tests.
  • Under review and queue: dav-3510 gemm_v0 silent numerical error (#1900, opened 10-15) is the most worth tracking this week—no exceptions, no NaN/Inf, no zero values, all multiset checks pass, and it only manifests as a precision failure on the remote; two separable commits (--npu-arch taken from the platform, gemm_v0 staging restriction) await verification of dependency order. Also in queue: KDA chunk_delta backward/forward migration (#1895 / #1896), bitwise_xor documentation redo (#1899), situ_glu (#1891), cann-bench/lstm examples (#1892), indexer_bwd (#1887). Open PRs rose from 230 to 237.
  • Main repo side: In addition to the PTO routing and independent AIV covered in the headlines, example target selection #3474 lets TILELANG_DEFAULT_TARGET determine the target, and the DeepGEMM JIT entry point supports execution_backend="auto"; the cross-warp allreduce grouping fix #3494 responds to community correctness feedback after #3469 merged, with the loop closed within two days.

MLIR Ascend (tilelang-mlir-ascend): Explicit Memory Control Landed, Knowledge Base Corrections

  • NPUIR explicit memory and pipeline control #190 (merged 10-13, 12 files, +1092/-102): supports dual-row GM→UB copy with signed pitch and contiguous GM/L1 ND copy, physical buffer views and mutable scalar storage, GEMM L0 ping-pong events and MMAD / Fixpipe unit flags (including explicit synchronization requirements), and T.vbrc regions with runtime dimensions; fixes Expert signed floor division/modulo, unsigned arithmetic, and lazy conditional lowering.
  • The full performance report from 10-12 (#197, 7 operators, 112 cases all passing, CANN 8.5.0 / 910B2C / msprof) and the knowledge base correction from 10-15 (#202, unifying the partial / merge description of ArgMax N-split as completed within a single device launch) were merged separately; T.Pipelined() parameterization (#199), FloorDiv / FloorMod codegen (#200), and the Cube memory allocation API (#201) are under review. Open PRs hold steady at 32.

Hygon: Three-Track Structure Takes Shape—Legacy Track Delivers, New Track Catches Up to Upstream, New Branch Builds Distributed

  • Register pipeline (#18): Under review all week, 49 files, +4144/-318, adding a register pipeline to the backend (coordinating with the shared-memory pipeline, inserting commits and barriers per pipeline stage) and warp-diverge when warp count exceeds 4; the author reports example_gemm has reached rocblas-level performance.
  • FP8 feature branch: On feat/hcu-mqa-fp8, MLS channelwise FP8 GEMM self-reports 432 TFLOPS; on 10-12, added “fp8 decode GEMM bandwidth surpasses hipblas when M≤32” and converged naming (all author self-measured within the branch, not tied to a PR).
  • Mainline and release lines: On 10-14, merged #20 (overall upgrade to upstream v0.1.15, retaining the HCU backend and build.sh workflow, adding scale buffer layout planning and matching LDS layout for HCU block-scaled GEMM), and created the v0.1.15-release branch; on 10-15, #21 merged the block-scaled async copy layout into the v0.1.12-release maintenance line the same day it was opened; on 10-16, merged #22 (K-major packed scale copy and native FP32 MLS GEMM, after the daily report cutoff).
  • Distributed track: #19 (+2577/-28, 44 files) and the distributed branch advanced twice during the week, covering a unified distributed process launcher, IPC metadata initialization validation, BF16 / full-peer IPC allreduce tests, an IPC GEMM allreduce example, propagation of IPC shutdown and initialization failures, invalid peer guards, STRIDE remote block copy, plus one “move distributed language APIs” refactor. Multi-GPU collective communication becomes Hygon’s next-phase mainline.

MetaX: Shifts to Dev-Line Convergence After Catching Up to Upstream

  • On 10-13, the main branch was pushed to the upstream v0.1.15 version node (mirror #3309), bringing the mirror line up to the release; dev (the main adaptation workline) had previously stalled at 09-24. On 10-16, dev merged upstream main (Merge branch 'main' ... into dev) and fixed one [fix bug][MetaXGPU] xfail case—that commit (10-16 12:35) falls after the 10-16 daily report cutoff and was backfilled through this week’s supplementary review. Open PRs hold steady at 16.

Moore Threads (MUSA) and Sunrise: A Week of Silence and Dependency Upgrades

  • Moore Threads has had no pushes all week since 09-30, with 6 open PRs, making it the only one of the four domestic backends not aligned to v0.1.15; v0.1.15+musa.1 remains the latest release (09-30).
  • Sunrise (the TANG backend repo for S2/S3) had only two Dependabot CI dependency upgrades (#7, #8) under review on 10-12, with 3 open PRs and no code-level activity.

IV. Ecosystem and Adopters

TileOPs: A Week of 52 Merges — Refactor Finalized, MoE Wrapped Up, All Operators Climbing the Leaderboard Daily

  • Governance: The Op base class refactor #2520 (merged 10-11, 363 files, +3362/-5227) was completed in ten commits following a “behavior first, mechanical rename later” approach: operators with and without compilation boundaries uniformly go through _run_call; on failure, rollback is decided by whether the target was selected by this call; if a sub-operator does not belong to any delegate_for stage, the composite call fails as a whole; _validate_dtypes is removed; key_for merges the two selection entry points; and the compilation boundary is now derived from the manifest. The documentation site merged the “Op Base Class Guide” (#69) the next day, keeping code and docs in lockstep.
  • MoE double landing: Masked FP8 grouped GEMM #2521 (20 files, +1788/-37, closes #2388) uses FP8 e4m3, 1x128 / 128x128 block scaling, and bf16 output aligned with deep_gemm masked semantics; the kernel is a persistent grid of TMA producer warps plus two WGMMA consumer warpgroups, where empty tiles occupy no CTA and each weight tile is read from HBM only once; the manifest is narrowed to the masked layout and paired with 14 load rows (two E=8 rows plus twelve EP=8 decode rows, covering DeepSeek-V3, Qwen3-235B-A22B, and Kimi-K2, batch 64 / 256), and a new moe.masked_routed_metadata generator simulates expert imbalance (DeepSeek-V3 b64 empty 4/32, Kimi-K2 b64 empty 13/48). DeepSeek grouped top-k #2535 (15 files, +1193/-69, closes #2268) adds num_expert_group / topk_group / routed_scaling_factor and aligns with vLLM grouped_topk, while also fixing the scheduling issue where the default TOKENS_PER_BLOCK at T=512 occupies only 32/132 SMs. The wrap-up refactor #2551 removes the dedicated TightRow kernel and extends layout coverage to SM80 / SM86.
  • SM89 becomes the second platform: Three merges on 10-12 (D256 dense GQA decode #2529, dense GQA prefill #2528, GDN / DeltaNet prefill #2527, with 21 “failure not dispatchable” cases turned passing), four on 10-13 (GLA backward #2546: shared memory 114688→81920 bytes; DeltaNet backward #2547: 147968→98816; KDA fused prefill #2548: 256 threads allocating 182528→101120; compact row-wise grouped GEMM #2549), plus GQA split log-sum-exp switched to FP32 accumulation (#2550, where split mixing under bf16 large scores deviates by at most 0.23, and autotune now times by the actually launched program) and D=256 decode extended to SM80/SM90 (#2563).
  • Attention family wrapped up: Three merges landed the same day on 10-15 — varlen GQA gather and pipelined sliding window (#2537, FP32 per-head sinks covering the varlen portion), paged GQA with read-only RoPE / two-sided sliding window / per-head sinks (#2516, and the paged KV write operator PagedKVCacheWriteFwdOp (#2539, in-place scatter by caller slot, skipping -1 slots, independent FP8 K/V scaling, preserving NaN and overflow saturation semantics, validated against FlashInfer and vLLM). Earlier, 10-12 had already merged MLA decode SM89 (4.6x / 7.2x), MLA tuning split expansion (candidates 24→40, cold tuning 348.6 s→151.6 s), WGMMA descriptor lane 0 broadcast (26-line benchmark 0.7%–4.1% faster), KDA prefill, NSA top-k bit sorting, and paged GQA TMA specialized kernel (the four rows taken over on H200 dropped to 0.44–0.88x of original).
  • The foundry performance batch enters a daily cadence: Eight merges plus eight new opens on 10-13, eleven wrapped up on 10-14, three on 10-15. Representative data — softmax register-resident _held_row plus warp shuffle folding (#2570: 39/42 rows ahead by 1.1%–78.1%, only the two lm-head rows behind at 0.909x/0.934x); row-by-row per-warp stores when TMA cannot address N non-multiple-of-8 outputs (#2566: 294.7→23.2 microseconds, 12.7x, 7.5x faster than cublaslt-best); GELU erf chain shortened by five instructions (#2557: 1.125x), SiluAndMul 16-bit gate fast division (#2565: 1.074x, torch-compile ratio flipped positive from 0.945x), grouped GEMM tiling wrap-up with alternating staging (#2582: all four MoE load rows ahead of quack, fwd 1.015x / dgrad 1.012x / wgrad 1.033x), W4A16 weight-first loading (#2586: decode-long-k reaches 1.047x of marlin-fp16, with 8 tile rows each 2.5%–7.6% faster), sigmoid without IEEE division (#2588: 1.020x–1.042x, test nodes +2). Pooling, normalization, reduction, and RoPE were rolled out together (MaxPool1d/3d, AvgPool3d, RMSNorm row-split by width, InstanceNorm full-vector rows up to 2048 elements, any/all per-word tests, grouped tile counting warp scan: 4096 groups at 32 threads use 62 registers instead of 152).
  • Linear attention fixes: KDA prefill inversion stabilization (#2584, where main failed on 6 chunk and 2 fused cases under related keys including NaN, changed to a 16-row diagonal-block FP32 solve reusing shared buffers), GLA backward memory reuse (#2569, 131072→98304 bytes falling under the SM89 limit, with the PR explicitly not claiming a speedup), GLA prefill state skip (#2540, eliminating allocation and reads of the entire FP32 initial-state tensor), single-tile decode state load to avoid TMA hangs (#2538), MoE expert search skip (#2575), and permute-align bounds (#2559).
  • Queue: Open PRs 9 (10-12) → 19 (10-13) → 26 (10-14) → 17 (10-15) → 16 (10-16), rising then falling within the week, with merge speed and review depth alternately dominating.

TileOPs Nightly Pipeline: Six Snapshots, Correctness 1032 → 1134

  • 10-12 03:40 — snapshot fc2a2a91 (baseline 70cfdf84): correctness 1032 items, benchmark 1947 items (52 suites), zero failures, zero errors, 1 skipped
  • 10-13 03:53 — snapshot 4cd9f968 (baseline 6ec0d086): correctness 1042 items, benchmark 1947 items (52 suites), zero failures, zero errors, 1 skipped
  • 10-14 04:18 — snapshot 76e8cac2 (baseline a79a21e4): correctness 1064 items, benchmark 1966 items (53 suites), zero failures, zero errors, 1 skipped
  • 10-15 05:15 — snapshot 56c2ab6b (baseline 35a25677): correctness 1105 items, benchmark 1970 items (53 suites), zero failures, zero errors, 1 skipped
  • 10-16 11:35 — snapshot d6ab1d14 (baseline cb15bce7): correctness 1129 items, benchmark 1982 items (54 suites), zero failures, zero errors, 1 skipped

  • 10-17 04:13 — snapshot d44ab6d3 (baseline 67250e81): correctness 1134 items, benchmark 1989 items (55 suites), zero failures, zero errors, 1 skipped

  • Net weekly gain: correctness +102 items, benchmark +42 items, suites +3; each of the six snapshots has one skip (SM89 tuning cases not applicable on H200, unsupported KDA configurations, etc.), with no failures and no errors. Evaluation environment: H200, CUDA 13.2, torch 2.13.0+cu132, tilelang 0.1.12; the tileops version in the latest snapshot is 0.0.1.dev1338+g67250e817.
  • Alignment with merges: the +10 on 10-13 corresponds to the SM89 series, the +22 on 10-14 to MoE and SM89 backward/prefill, and the +41 on 10-15 to TileOPs’ 16 merges (the performance batch generally carries test-node additions) — the rolling accounting of “one merge, one step up the baseline” continued throughout the week.
  • A window discrepancy to note: the 10-16 daily report was generated before the 10-15 nightly snapshot was visible; that snapshot actually landed at 10-16 11:35 (Beijing time, later than the daily report’s 07:00 cutoff) and has been backfilled this week; the 10-17 04:13 entry at the end of the table is the product of the 10-16 nightly run, i.e., the second snapshot of the day on 10-16.

TileFoundry: Ten Merges — From Sparse Decode to a Deliverable Engineering Form

  • Sparse decode threaded through TIR (#223, merged 10-12, 84 files, +4424/-1543): Taking over the DSA decode legacy issues from #218 — fixing lost loop work, excessive lookup billing, and staged update errors, landing indexed async gather and Bitcast and Where sinking; allocation constraints changed to a single accessor (returning Storage), captured updates written directly into tiles (16B shared memory), and carried values for parameter initialization given independent storage with a preceding copy; 16 FixtureCase guards each include CLI invocation and output checks.
  • Qwen3.8-27B prefill (#229, merged 10-13, 89 files, +38069): Text prefill for a 64-layer gated-delta-net / attention hybrid, faster than SGLang at all three lengths 1024 / 4096 / 8192; at 8192, scoring accounts for only 3.1% of FLOPs, with the rest GEMM, making it FLOP-bound with no traffic to save; the example uses analyze --roofline as a decision input. Boundary: the SGLang baseline is manually specified, and its two columns differ by 9.1% at 8192, so the example needs to justify which column it takes; previously the repo’s examples were all decode and reached only a fraction of SGLang.
  • Refactor and contracts: The instance-slot refactor (#232, merged 10-15) changes module subnodes to explicit shared instance slots (repeated layers share definitions while retaining independent resources and instance identity), with placement addresses shared by SSA leaves, live ranges cached by definition and translated at call sites, removing the old inlining mechanism and Program; the full source suite passes 1674 / 11 skipped. The lowering and printer contract (#233, 10-15) preserves author regions, storage definitions, update windows, and staged ownership, with instruction admission shared across inference, candidate generation, lowering, and TIR validation. 10-16 added the analysis access context (#238) and the allocation/lowering fixes for issue 237 (#241).
  • Engineering entry points: The scaffold standalone project (#227, merged 10-13, 47 files, +1356/-368) generates an editable standalone CMake project per Target codegen (parameter views, specialized dispatch, launcher, host registration, and placeholder CUDA bodies), with codegen artifacts and linking split into six module files; the schedule CLI hardening (#231, merged 10-14) unifies the instruction matcher, adds tf.empty, and adds schedule finalize --dim, freezing the full source suite at 1617 passing / 11 skipped.
  • Releases and in-review: The release page remains v0.0.2 (09-10), with no new version all week; open PRs 1→2→1→3→2. On the external audit side, the third-party tilelang-cuda-skills vendored TileFoundry as a submodule on 10-15 (pinning main and cutlass commits), publicly marked the compile() path as experimental and listed 4 emitter bugs (Cast emission, fill tensor suffix, tensor_view coordinates, etc.) and 2 runtime bugs (reduce-workspace finalization, warps_per_group dispatch), while also noting the missing host TMA tensor-map emitter and delineating the supported paths (HIR generation, check / analyze, schedule finalize, TileLang kernels).

TileSight, TileRT, and Adopters

  • TileSight: A dev branch was created on 10-13 with branch-level pushes; public branches include main and tilelang (the latter containing TileLang frontend commits), with no release content and 0 open PRs. As the tile-centric performance model open-sourced on 09-23, it is in a branch-organization phase this week.
  • TileRT: No pushes all week (most recent 09-24); the release page remains v0.1.5.post2 (08-06); no release PRs and no benchmark documentation updates this week.
  • TileKernels: v2.1.0 merged on 10-14 (see Top Stories); no new pushes from 10-14 until this report was compiled, and the open PR count fell back. Its version requirements (TileLang 0.1.15 / PyTorch 2.13 / Ascend 950 / CANN 9.2.0) make it the first downstream hard constraint on the “0.1.15 baseline”.
  • FlashQLA: The sm120 fix (#48, 10-14) restores block_DV=64 and adds aggregate_card_state, with all tests passing on RTX 5090 + tilelang 0.1.15 + CUDA 13.0; the PR proposes exploring intra-node / cross-node context parallelism next.

V. Community, Tutorials, and Events

PTO-ISA: Release cadence of the new tilelangGym repo and SuperNPUBench

  • tilelangGym was created on 10-14, positioned to “test the PTO lowering and performance sensitivity of different benchmarks / microbenchmarks”; on 10-15, seven commits (06:47 to 07:59) shaped the standalone SimtVF standard test suite: seed commits and version pins for SV / CF / SP plus PTO-DSL, regression (#1), script and layout cleanup, SV1 SIMD keynote and a single PASS table (#3), a full PASS table for remat vertices and a line-by-line Simt vs. SIMD-DSL comparison (#4), and linking the SIMD ~85% figure and the Simt IPC / bubble / ILP analysis chain into ANALYSIS — establishing a data workbench for performance sensitivity analysis of PTO lowering.
  • SuperNPUBench was high-frequency all week: four commits on 10-12 (rms_norm 16 KiB tile decomposition with R=8192 reduction, gfsim RES_CHECK file IO lockstep safety, matmul_test simplified to 4-PE, #225 merged) and two releases (ops-20261012, ops-20261013, the latter split into 2 small packages by suite and including all compiled ELF outputs); on 10-13, released ops-20261013.2 and advanced matmul_test direct-connect CUBE TCVT and the topk portable gfsim fixture; on 10-14, three archival commits (rms_norm_dynamic_simt_32k, group_norm_grad static kernel into V0, matmul reuseB kernel); on 10-15, group normalization backward single-pass reduction and gamma/beta balancing (#245).
  • The simt_compare branch of tilelang-puzzles-ascend advanced all week: T.reduce_max measured 8.94x faster than serial scan, and 12 kernels were switched to T.reduce_absmax folding and re-measured.

Third-party tools and materials: from list repos to external audits

  • tilelang-debugger: two commits on 10-10 (unified source access capture + offline HTML debug report with linked evidence), running 117 CPU / TIR tests each on TileLang 0.1.12 and 0.1.15, 42 collections and 66 baseline / instrumented launches on H200; no new pushes this week (since 10-12).
  • easy-tilelang tutorial repo: pushed “adapt tilelang new ascend” on 10-13, including entries such as lower-trace compilation observations for Ascend A5; silent after 10-14.
  • TileMC (third-party target for manycore architectures): one commit on 10-14, extending FP32 support, panel mapping, and workload scaling.
  • BM1690 pipeline repo (Sophgo TPU): eighteen commits on 10-14 and six board-level logs on 10-15 — Matmul / RMSNorm board-level smoke tests, Split-K board-level results, RoPE integration and boot timeout diagnosis, driver reinitialization and exit semantics, 7.0.0-34 kernel host build, etc.; these are integration records from a personal experimental repo.
  • SwHwCodesign material line did not take shape: TileLang-Awesome, created on 10-11, was already inaccessible on 10-12 (404, no new repo of the same name found in search); the same account created six other AI-* placeholder repos, and by 10-14 only 2 public repos remained (AI-Compiler, AI-Infra) with no pushes.
  • tilelang-cuda-skills: the first external audit of TileFoundry on 10-15 (content in Chapter IV), the first public sample of “the toolchain being actually used.”

Media and academia: continued silence after the wave of coverage

  • Chinese in-depth interpretations from 10-10 to 10-11 (Zhiwei, two versions on Fengwen and Zhihu) took TileLang as the narrative core, covering the Tile abstraction, the three-tier programming interface, and the autotuning cache mechanism, and provided a comparison of the Ascend adaptation against Ascend C with “almost no performance difference (A2 / A3)”; the overseas aggregation piece on 10-11 (tech-insider) is derivative in nature, not an independent source.
  • For four consecutive windows starting 10-12, multiple Google News queries in Chinese and English returned zero new items, Hacker News had no related entries, and arXiv had no new preprints (the most recent remains the 07-24 TileSight performance model paper). The media side entered a quiet period after the coverage wave from 09-29 to 10-11; all of this week’s main content came from GitHub organization activity.

VI. Trend Observations

  • “Static preparation” during the release quiet period is now in place across four directions simultaneously: TileOPs’ Op base class refactor claims to be closed out ahead of release; the nightly foundation’s six snapshots show zero-failure growth; TileFoundry’s examples extend from decode to prefill with full-length outperformance; and multi-backend alignment at v0.1.15 is complete — the main repo has gone 16 days without a tag since 09-30, but the static preparation for the next version is largely in place this week. Whether to release depends on the review gate, not on content.
  • Multi-backend is moving from “version alignment” to “semantic convergence”: Hygon completed the full v0.1.15 upgrade and separately established a v0.1.12 maintenance line; MetaX caught up with the mirror and shifted to dev merge; Ascend is focusing on documentation fact-checking, cache semantics, and real-hardware validation (#1900); Moore Threads is the only gap. The gap among the four has shifted from “whether a backend exists” to “whether semantics are consistent.”
  • ROCm has become a second line synchronized with new model releases: for four consecutive days, DeepSeek NSA, mHC, KDA, and GLM-5.3-related kernels landed, with technical debt paid down item by item against device budgets (64-lane wavefront, MFMA input types, LDS/VGPR limits); after merging with the multi-generation co-fix for SM121 / SM89, the backend topology has shifted from “NVIDIA-first” to “multi-device concurrent maintenance.”
  • TileOPs’ performance engineering has shifted from “targeted work on key operators” to “daily leaderboard runs across all operators”: 8 to 11 entries per day, each with external comparisons (torch-compile / cuBLASLt / quack / FlashInfer / FLA), and residual shortfalls are written openly into PRs (lm-head’s two lines at 0.909x; GLA backward explicitly makes no speedup claim) — quantifying and documenting “shortfalls” demonstrates engineering discipline better than isolated speedups.
  • Ascend’s governance stance is shifting from “all passing” to “precise assertions”: three documentation checks were rolled back wholesale and then trimmed and redone because of an exception-regex mismatch in low-priority cases, exposing the two-tier CI structure in which low_priority is not run at the PR stage and a full daily run serves as the fallback; such rollbacks are not regressions but a signal of treating “expected failures” as technical debt to be cleared.
  • TileFoundry is shifting from a compiler tool to a deliverable product form: the standalone scaffold project, instance slots and lowering contracts, and the cross-ridge prefill example argumentation — in the same window the refactor landed, third-party vendors listed it alongside a defect ledger — the typical trajectory of productization is “after foundation refactoring, interface contracts converge and defects become public.” The next issue needs to track whether these emitter / runtime defects are absorbed.
  • Watch items for the next issue: whether main repo v0.1.16 is released (16 days of silence); whether the dual-track SM120 block-scaled MMA (#3495 / #3099) can be merged; the cumsum warp specialization fix (#3536) and the seven-entry PTO family’s progress; Ascend #1900’s two commits and A5 real-hardware validation scheduling; whether Hygon’s distributed IPC produces its first merged multi-card PR; TileOPs has seen release-pipeline cleanup-type commits (weekend) — whether these lead to the first official version; whether TileFoundry’s external defect list is absorbed.

Appendix: Sources and Verification Notes

  • Sources: Five issues of this publication’s daily TileLang intelligence brief (10-12 to 10-16), covering the collection window from 10-10 07:00 to 10-16 07:00 (Beijing time); developments during the daytime of 10-16 and the night of 10-16 (early morning of 10-17 Beijing time) within the period were incorporated into this report after supplementary verification over a 168-hour window; organizational developments on 10-17 (Saturday) will be merged into next Monday’s brief.
  • Supplementary verification (168-hour window, as of the preparation of this report): of the 29 repositories in the tile-ai organization, 12 had pushes within the window (tilelang, TileOPs, TileFoundry, tilelang-ascend, tilelang-hygon, tilelang-metax, tilelang-mlir-ascend, TileSight, TileOPs-nightly, tilelang.github.io, TileOPs.github.io, tilelang-sunrise); PR merge and creation counts were measured by retrieval over the 10-12 to 10-16 Beijing-time window; the test_results.xml and bench_results.xml of the six nightly pipeline snapshots were recomputed one by one (test cases, failures, errors, skips, suite counts).
  • Scope and caveats: All performance figures are self-reported in PR descriptions or release notes (H100, H200, B300, RTX 5090, RTX 6000 Ada, etc.); this publication has no corresponding hardware and has not independently reproduced them; nightly snapshots are single pipeline records, not cross-sectional benchmarks; publication dates are based on verification of each repository’s tags and release pages, and release pages and branch progress for the adaptation repositories may lag; TileKernels’ Ascend performance is stated in its own README and is not a third-party evaluation.
  • Suggested next cycle: 2026-10-19 ~ 2026-10-23.

Source Verification Table

Source Verification Result
tile-ai organization (29 repos) 12 repositories had pushes within the 168-hour window; 109 PRs merged and 158 newly opened this week; 532 PRs currently open
Main repo tilelang 30 merged this week; open PRs 170→168→161→160→165; no additions to release page or tags all week (latest v0.1.15, 09-30)
TileOPs 52 merged this week; open PRs 9→19→26→17→16; Op base class refactor, MoE dual operators, attention trio, and foundry performance batch all landed in the same week
TileOPs-nightly Six snapshots, correctness 1032→1134, benchmarks 1947→1989 (52→55 suites), all with zero failures and zero errors
TileFoundry 10 merged this week (#223, #221, #227, #229, #231, #232, #233, #236, #238, #241); open PRs 1→2→1→3→2; release remains v0.0.2 (09-10)
Ascend (ascend / mlir-ascend) ascend: 8 merged (#1701, #1730, #1612, #1676, #1681, #1888 to #1890); open PRs 230→237. mlir-ascend: 2 merged (#190, #202); 32 open PRs
Hygon / MetaX / Moore Threads Hygon: 3 merged (#20, #21, #22), #19 and the distributed branch under review/in progress; MetaX: 2 merged (main mirror and dev merge); Moore Threads: no activity since 09-30, 6 open PRs
Sunrise Only two Dependabot CI dependency upgrades under review (#7, #8); 3 open PRs
Adopters (TileKernels / FlashQLA) TileKernels v2.1.0 (#38) and the FlashQLA sm120 fix (#48) were both merged on 10-14; no new pushes after 10-14
TileSight / TileRT TileSight created the dev branch and pushed on 10-13, no release; TileRT had no pushes all week (most recent 09-24)
PTO-ISA and third-party community New repo tilelangGym (10-14) and seven SimtVF suite entries; two SuperNPUBench releases plus several archival entries; 24 BM1690 board-level logs; 1 external audit of tilelang-cuda-skills; 1 TileMC entry; 1 easy-tilelang entry; no pushes within the window for tilelang-debugger or SwHwCodesign
Media and academia Google News has had zero new entries for four consecutive windows since 10-12; no relevant Hacker News items; no new arXiv preprints

Key References

Data sources: Daily TileLang intelligence briefs (five issues, 2026-10-12 to 2026-10-16) and measured verification during this cycle; reporting period is October 12 to October 16, 2026.