Research window: 2026-10-20 07:00 ~ 2026-10-21 07:00 (Beijing time, 24 hours).

Sources: Per-repo inspection of the GitHub tile-ai organization (full Atom commit feed, covering tilelang / TileOPs / TileFoundry / tilelang-ascend [default branch ascendc_pto] / tilelang-hygon / tilelang-metax [dev] / tilelang-musa / tilelang-mlir-ascend / TileRT / tilescale / DeepStack) + merged-and-in-review ground-truth search (is:merged / is:open, grouped by repository) + release page and VERSION file inspection + stats branch inspection + docs site commit inspection + adopter repo inspection (TileKernels / FlashQLA) + community new-repo search + multiple Google News queries in Chinese and English (via proxy) + Hacker News + arXiv.

This Issue’s Index

  • Today’s Highlights: Five compiler correctness fixes land in the main repo on the same day, Ascend-side backward and recurrent operators fill gaps, and TileOPs swaps three foundry attention operators for warp-specialized programs on SM90 (10-20)
  • I. Core Project Progress
    • 1.1 Main repo: Vectorization analysis incorporates nonzero loop lower bounds, fixes unit-step loops and mixed-precision guards (#3579) (10-21)
    • 1.2 Main repo: Shared-memory cross-thread WAW detection switches to a two-thread instance, restores a missing barrier (#2821) (10-20)
    • 1.3 Main repo: Unsupported MMA tiles require explicit K padding, avoiding silent K reduction and layout inference failures (#2818) (10-20)
    • 1.4 Main repo: Fragment reduce supports retained-dimension targets, fixes crash on (64,1) targets (#2815) (10-20)
    • 1.5 Main repo: TIR predicates rewritten in sync with integer bit-width promotion (#3550) (10-20)
    • 1.6 Main repo: CuTeDSL scan adds participating-thread offset parameter, fixes cumsum construction failure (#3576) (10-20)
    • 1.7 Main repo CI: Performance regression jobs pinned to H100, H20 machines must fail-fast (#3569) (10-20)
  • II. Multi-Backend Adaptation (Ascend / MetaX / Hygon / Moore Threads)
    • 2.1 Ascend main repo: L0 local copies support explicit pitch, a single GEMM tile can be assembled from multiple copies (#3511) (10-20)
    • 2.2 Ascend main repo CI: Build and test steps split within a single check, remaining suites continue after a failure (#3564) (10-20)
    • 2.3 Ascend repo: DSA sparse fine-tuning backward operator indexer_bwd lands, dual backend AscendC and PTO (#1887) (10-20)
    • 2.4 Ascend repo: SiTU-GLU backward operator checked in, validated against Kimi K3 gated activation and cross-checked on 910B3 (#1877) (10-20)
    • 2.5 Ascend repo: cann-bench adds LSTM and GRU, 12 / 8 jit kernels covering multi-layer bidirectional and projection (#1892 / #1902) (10-20)
    • 2.6 Ascend repo: Chinese version of CrossEntropy benchmark completed, continuing the en/zh paired convention (#1801) (10-20)
    • 2.7 Ascend under review: PTO vectorization framework enters review (#3512), tvm_ffi proposed as pto default execution backend (#3516), DeepGEMM heuristic alignment (#3577) (10-20)
    • 2.8 Hygon: MLS window constant K origin fix merged (#25), fp4 partitioning and distributed changes under review (#26 / #19) (10-20)
    • 2.9 MetaX / Moore Threads / MLIR-Ascend: No new pushes in this window, all three lines remain at existing versions (10-20)
  • III. Ecosystem and Adopters (TileOPs / TileFoundry / Operator Libraries)
    • 3.1 TileOPs: Paged GQA forward swapped for paged warp-specialized program, FP8 pool read via 16-bit page mirror (#2668) (10-20)
    • 3.2 TileOPs: FP8 lightning indexer switches to dual consumer warpgroups alternating on 64-key tiles (#2666) (10-20)
    • 3.3 TileOPs: MLA decode uses staggered seesaw program, keys segmented by SM count then merged via log-sum-exp (#2665) (10-20)
    • 3.4 TileOPs: Tensor core performance ceiling changed to operand-set envelope, fixes 105%/108% false positives in nightly batch runs (#2661) (10-20)
    • 3.5 TileOPs: Backend tests and torch-compile baselines can run on non-CUDA devices (#2658) (10-20)
    • 3.6 TileOPs: SM89 single-row single-column switches to vector GEMM path, candidates filtered by shared-memory budget (#2660) (10-20)
    • 3.7 TileOPs: Three builder cache and tuning contract fixes (#2662 / #2663 / #2664) (10-20)
    • 3.8 TileOPs 11 under review: SM89 NSA top-k, paged DSA, and W4A16 narrow tile lines advance in parallel (10-20)
    • 3.9 TileFoundry: 0.0.3 announcement written into README, test refactor reuses compilation cache (#247 / #246) (10-20)
    • 3.10 Adopters: TileKernels and FlashQLA have no pushes in this window (10-20)
  • IV. Community, Tutorials and Events
    • 4.1 Community repo: Chinese system tutorial tilelang-tutorial created, covering operators, compile-time, and both major backends (10-20)
    • 4.2 Community repo: CANN community ops-tilelang created, managing Ascend implementations and baselines as operator assets (10-20)
    • 4.3 Toolchain: devkit and VS Code extension active, main repo under review moves lower trace out entirely (#3583) (10-20)
    • 4.4 Community repo: tilelangGym tests PTO lowering sensitivity, Hexagon backend experimental repo appears (10-20)
    • 4.5 Docs and versions: Documentation site auto-updated four times, main repo VERSION still 0.1.15 (10-21)
  • V. Trend Observations

Today’s Highlights

26 changes merged in this window (tilelang 9, TileOPs 9, tilelang-ascend 5, TileFoundry 2, tilelang-hygon 1), with no new releases. Three lines advance simultaneously: the main repo places most of the day’s merges on compiler correctness (vectorized loop lower bounds, shared-memory cross-thread WAW, MMA tile K atomics, fragment reduce retained dimensions, TIR predicates with bit-width promotion), which is “silent error” cleanup rather than feature expansion; all five Ascend-side merges land on training-side and recurrent operators (DSA sparse fine-tuning backward, SiTU-GLU backward, LSTM, GRU), and a 21,000-line PTO vectorization framework is under review, with PTO becoming the second execution path alongside AscendC; TileOPs swaps three foundry operators — paged GQA forward, FP8 lightning indexer, and MLA decode — for warp-specialized programs on the same day on SM90, while changing the tensor core performance ceiling calibration to an operand-set envelope, fixing the 105% pseudo-overrun in nightly batch runs.

I. Core Project Progress

1.1 Main repo: Vectorization analysis incorporates non-zero loop lower bound (#3579)

Merged on 10-21 00:27, 10 files +818/-198, following up on the guard fix in #2819 and closing issues #2669 and #2616. The original implementation compared f(i) with f(floor(i / W) * W) to determine whether an expression has the same value within each vector group, which implicitly assumed the loop starts at 0; when the loop lower bound is non-zero, unit-step vectorization would compute addresses of different lanes as the same group, invalidating the proofs for broadcast loads and whole-group shared conditions. The new determination incorporates the loop minimum into the analysis and preserves nested guards when hoisting mixed-precision conversions. This is a compiler defect that would silently change numerical results.

Source: https://github.com/tile-ai/tilelang/pull/3579

1.2 Main repo: Cross-thread WAW detection for shared memory (#2821)

Merged on 10-20 23:41, 3 files +153/-19, fixes #2698. On shared memory, S[tx] and S[tx + 10] are two addresses for a single thread, but writes from different threads can overlap; the original WAW check reused the same thread variable for both accesses, thus missing detections and failing to insert barriers. The fix uses two distinct thread instances for same-iteration WAW and renames their respective Bind definitions, reusing the existing RAW/WAR model, while loop-carried WAW retains the original handling. Tests cover both “should insert” and “should not insert” cases, including guarded writes, Bind-derived indices, disjoint partitions, and threadIdx.y/z permutations; 95 cases pass across the thread-sync and issue test suites.

Source: https://github.com/tile-ai/tilelang/pull/2821

1.3 Main repo: Unsupported MMA tiles require explicit K padding (#2818)

Merged on 10-20 16:41, 5 files +57/-14, fixes #2715. The generic MMA emitter could silently shrink the K atom before constructing operand layouts, causing FP16 K=8 to produce incorrect results; irregular sizes such as K=20 and K=28 failed directly at the shared memory layout inference stage with unclear messages. Now the tile’s K is validated against the architecture-fixed K atom at emitter initialization, throwing ValueError if not evenly divisible, with the input dtype, the required divisibility relation, and the suggested padding value (e.g., FP16 K=20 on SM80 reports atom 16 and suggests padding to K=32 with zero-filled extra elements).

Source: https://github.com/tile-ai/tilelang/pull/2818

1.4 Main repo: fragment reduce supports keep-dim targets (#2815)

Merged on 10-20 16:35, 8 files +343/-63, fixes #2530. T.reduce_sum and similar crashed at compile time when reducing (64, 64) along dim=1 to (64, 1) (Check failed: vars.size() == InputDim() (2 vs. 1)). Yet the documented contract in reduce_op.py explicitly accepts both [X, Y] and [X, 1, Y] output shapes and already constructs the corresponding expected shapes, so this was a backend gap rather than misuse. The fix teaches both lowering paths and preserves the original behavior for targets without keep-dim.

Source: https://github.com/tile-ai/tilelang/pull/2815

1.5 Main repo: TIR predicates rewritten in sync with integer bitwidth promotion (#3550)

Merged on 10-20 09:59, 4 files +950/-27. After integer indices are promoted to a wider bitwidth, bounds checks guarding buffer accesses were still computed at the old bitwidth, theoretically allowing out-of-bounds accesses to pass. A new IndexPredicateRewriter records promotion information for each access in ConfigIndexBitwidth and FlattenBuffer, then rewrites the relevant guards after the access statement is processed; matching is restricted to equivalent addition and multiplication forms, preserving unrelated conditions, data-value expressions, and fixed-width bounds. Five new test categories are added: index promotion, guard rewriting, access scoping, vector endpoints, and conflicting promotions.

Source: https://github.com/tile-ai/tilelang/pull/3550

1.6 Main repo: CuTeDSL scan adds participating-thread offset (#3576)

Merged on 10-20 12:49, 2 files +30/-6. The shared memory scan lowering introduced a participating-thread offset in #3536, but the CuTeDSL-side helper still generated calls with the old constructor arguments, so tl.CumSum1D(32, False, 0).run(...) directly raised a constructor argument error; the codegen assertion that broke in the same batch was also the source of the two CUDA CI failures in #2815. The fix adds an optional thread_offset (defaulting to 0 for compatibility) to the 1D and 2D cumsum/cummax helpers, subtracts the offset before selecting participating lanes and warps, and marks CUDA-specific tests with requires_cuda.

Source: https://github.com/tile-ai/tilelang/pull/3576

1.7 Main repo CI: Performance regression job pinned to H100 (#3569)

Merged on 10-20 16:00, 1 file +15/-1. The PR regression bot compares per-kernel latency against a baseline, and the numbers are only meaningful on the same GPU model used to collect the baseline. The organization is introducing self-hosted H20 capacity machines for regular correctness CI, whose label set overlaps with the existing [self-hosted, nvidia]; without differentiation, benchmark jobs would be silently picked up: H20’s FP16 dense throughput is about 148 TFLOPS, roughly seven times lower than H100’s ~990 TFLOPS, and its FP64 path is also heavily cut down, so every benchmark would report non-existent regressions. The pr-regression job is now required to carry the h100 label and to verify before starting that the assigned GPU is indeed an H100, failing fast on a mislabeled runner rather than publishing misleading numbers.

Source: https://github.com/tile-ai/tilelang/pull/3569

II. Multi-Backend Adaptation (Ascend / MetaX / Hygon / Moore Threads)

2.1 Ascend Main Repo: L0 Local Copy Supports Explicit Pitch (#3511)

Merged on 10-20 14:16, 24 files +1458/-187, the largest Ascend-direction change in this window. Previously a GEMM tile could only be filled by a single L1→L0A/L0B copy, non-zero destination origins were rejected, and each copy derived a compact pitch from its own region, so two halves moved separately could not be assembled into the target whole block; MajorK/MajorMN transposed loads were also restricted. Adds an Ascend-specific parameter T.copy(..., l0_pitch=...) to specify the L0 pitch per fractal block, with the caller supplying the consumer GEMM’s compact pitch (including dynamic tail blocks); omitting the parameter preserves the original behavior for compact regions. In the example, both halves of the 64-row A tile specify l0_pitch=4. Also handles lowering of aligned destination offsets, physical boundary and transpose-group validation, and allocation and buffer version spacing.

Source: https://github.com/tile-ai/tilelang/pull/3511

2.2 Ascend Main Repo CI: Split Build and Test Within a Single Check (#3564)

Merged on 10-20 12:06, 1 file +61/-9. Consolidates Ascend build and test results into a single Test for Ascend PR check, presenting failure stages step by step and listing each stage’s conclusion in the workflow summary. The CANN environment is set up once and built once; the AscendC examples, PTO examples, and Ascend unit tests run as three separate steps of the same job. When the build succeeds and the workflow is not cancelled, a failing suite does not stop the remaining suites, and the overall result is still marked as failed. CANN variables are passed via GITHUB_ENV.

Source: https://github.com/tile-ai/tilelang/pull/3564

2.3 Ascend Repo: DSA Sparse Fine-Tuning Backward Operator indexer_bwd (#1887)

Merged on 10-20 15:26, 2 files +1294. Adds indexer_bwd for the Ascend NPU, serving DSA sparse fine-tuning, supporting both the AscendC and PTO backends. The operator computes gradients of the lightning-indexer KL fine-tuning loss with respect to dIndexQ, dWeights, and dIndexK, and supports variable-length packed sequences. The implementation has three tiers: a fast kernel with persistent GEMM targeting contiguous and shared-row index layouts, with pipelining and fewer transfers; a general kernel supporting arbitrary index layouts, including gradient accumulation for -1 invalid indices; and a separate cast kernel for precision conversion.

Source: https://github.com/tile-ai/tilelang-ascend/pull/1887

2.4 Ascend Repo: SiTU-GLU Backward Operator (#1877)

Merged on 10-20 15:22, 5 files +854. Semantics align with CANN ops-nn’s aclnnSituGluGrad, used for the gated-activation backward of Kimi K3 Stable LatentMoE: t = tanh(gate / beta), s = sigmoid(gate), situ_a = beta * t * s; the upstream branch takes tanh or passes through depending on whether linear_beta is positive, outputting grad_gate and grad_up. The accuracy baseline is an independently implemented fp64 PyTorch reference, cross-validated against the official aclnn on 910B3, with a maximum relative error of about 3e-3, consistent with bf16 rounding expectations.

Source: https://github.com/tile-ai/tilelang-ascend/pull/1877

2.5 Ascend Repo: cann-bench Adds LSTM and GRU (#1892 / #1902)

Both merged the same day, +2304 and +2267 respectively. LSTM covers the i/f/g/o four gates and cell-state temporal recurrence, supporting multi-layer stacking (numLayers ≤ 8), bidirectionality, batchFirst layout, projection dimensionality reduction (projSize > 0, LSTMP), and optional bias; weights are passed as a TensorList with “one tensor per layer per direction”, outputs are (y, hn, cn), and the implementation consists of 12 @tilelang.jit kernels. The main path uses the fused seq path, with one launch per (layer, direction); within the kernel, T.serial(S) iterates over time steps to complete the dual GEMM, bias broadcast, gating, and state update, while the x-side gating contribution unrelated to recurrence is precomputed in parallel across all time steps by a separate xgemm. GRU consists of 8 kernels: the combined z/r/n three-gate GEMM runs on Cube, gating and state updates run on Vector, cross-core data is relayed through a GM workspace, and AUTO_SYNC is manually disabled—according to the commit description, automatic mode generates about 58 PipeBarriers per time step.

Source: https://github.com/tile-ai/tilelang-ascend/pull/1892, https://github.com/tile-ai/tilelang-ascend/pull/1902

2.6 Ascend Repo: Chinese Version of CrossEntropy Benchmark (#1801)

Merged on 10-20 15:26, 2 files +91. Adds a Chinese version of the CrossEntropy benchmark documentation merged in #1567, following the en/zh pairing convention of FA (bench_mark.md, bench_mark_zh.md) and SFA (README.md, README_zh.md): in the examples/cross_entropy_loss/ directory it adds benchmark_summary_zh.md, fully translating the eight-step optimization path, internal performance comparison, CANN comparison, known limitations, and test coverage, and adds a language-switch link at the top of the English version. Documentation-only change.

Source: https://github.com/tile-ai/tilelang-ascend/pull/1801

2.7 Ascend Under Review: PTO Vectorization Framework, tvm_ffi Backend, and DeepGEMM Alignment

Three main lines are under review simultaneously. #3512 (50 files +21022/-72) lets users write scalar-parallel T.Parallel programs (element-wise, control flow, reductions) inside T.SimdVF(lanes=L), which the compiler vectorizes into PTO VMI instructions and runs on Ascend 950 after compilation via PTOAS; the full capability lands across multiple PRs, and this one is the milestone for the pipeline framework and element-wise support. #3516 (18 files +1473/-22) makes target="pto" with execution_backend="auto" resolve to tvm_ffi and sets it as the default, with the host side using MakePackedAPI and C host builds, and the Ascend runtime launching the aibin compiled by PTODSL via aclrtLaunchKernelWithHostArgs. #3577 (29 files +1392/-1036) completes DeepGEMM-Ascend’s configuration selection and epilogue, covering fused bias, Alpha, BF16 stochastic rounding, and FP8 quantization for dense, batched, and grouped GEMM. Also #3530 (partial UB→L1 copy of NZ buffers), and a group of #3573 / #3580 / #3581 / #3582 covering PTO predicates, MAD direction analysis, and redux signedness fixes.

Source: https://github.com/tile-ai/tilelang/pull/3512, https://github.com/tile-ai/tilelang/pull/3516, https://github.com/tile-ai/tilelang/pull/3577

2.8 Hygon: MLS Window Constant-K Origin Fix (#25)

Merged on 10-20 09:53, 2 files +346. After loop unrolling, MLS resource promotion drops the constant window offset, causing subsequent accesses to land in the wrong range. The fix validates the non-updated dimension before choosing single-axis update or forward incremental addressing, conservatively reinitializing the window when necessary; regression coverage is added on top of the existing MLS tests. Three PRs are under review in the Hygon repo within this window: #26 handles warp partitioning for fp4 MLS (14 files +261/-144), #18 adds register pipelining and warp-diverge support, and #19 covers distributed-related changes.

Source: https://github.com/tile-ai/tilelang-hygon/pull/25

2.9 MetaX / Moore Threads / MLIR-Ascend: No New Pushes in This Window

All three lines had no commits in this window. The MetaX repo’s most recent activity was 0.1.15 version preparation on 09-29, the Moore Threads repo stopped at 0.1.15 public release preparation on 09-30, and MLIR-Ascend’s most recent was a TVM isolation fix on 10-19 (outside this window). All three repos have zero open PRs and no new branch activity.

Source: https://github.com/tile-ai/tilelang-metax, https://github.com/tile-ai/tilelang-musa, https://github.com/tile-ai/tilelang-mlir-ascend

III. Ecosystem and Adopters (TileOPs / TileFoundry / Operator Libraries)

3.1 TileOPs: Paged GQA forward switched to paged warp-specialized program (#2668)

Merged 10-20 22:41, 8 files +901/-103. The new GQAPrefillPagedWSKernel (SM90) takes over GQAPrefillPagedWithKVCacheFwdOp: a single append launch writes chunks into pages (keys rotated under fused RoPE, both quantized on the FP8 pool) and rotates the query, after which the warp-specialized program in GQAPagedFwdOp performs attention over the enlarged cache. The program serves head dim 256 (single query slot) and query groups wider than 16 heads on a single KV head (flattening the (T * H, D) query into rows); pools of dims 64 and 256 not covered by the FP8 program are read via the 16-bit page mirror, capped at 4 GiB per call; when a request may be split, requests are sorted by cache length, longest first, up to 128 requests.

Source: https://github.com/tile-ai/TileOPs/pull/2668

3.2 TileOPs: FP8 lightning indexer switched to dual-warpgroup consumption (#2666)

Merged 10-20 22:41, 6 files +448/-2. The original implementation had one warpgroup multiply a 64-key tile, then ran an epilogue as long as the product (per-head key scale, FMUL and FADD separate); there was also a clean sweep writing -inf outside the window at 2.5 TB/s—per the commit message, this accounted for 425 of the 472 microseconds in chunk-prefill-kscale; in the decode call a single query occupies one CTA across all 16384 keys, taking 289 microseconds. The new FP8LightningIndexerWSKernel (SM90) uses a TMA warp to stream 64-key tiles to two consumer warpgroups in alternation, one m64n256 FP8 WGMMA per tile, with the consumer epilogue consolidated into a csrc helper.

Source: https://github.com/tile-ai/TileOPs/pull/2666

3.3 TileOPs: MLA decode moves to the offset seesaw program (#2665)

Merged 10-20 22:39, 7 files +881/-590. MLADecodeSeesawKernel (SM90, 512 + 64 latent, single KV head) takes over MLADecodeWithKVCacheFwdOp, following the offset seesaw approach of MLAPagedFwdOp and reading k and k_pe per request via TMA; the program body moves to
kernels/attention/mla/seesaw.py, providing both paged and dense entry points, and the split construction of MLAPagedFwdOp produces the same storage as before. A request’s keys are cut into a number of runs given by the smaller of the SM count per block and half the tile count, merged with log-sum-exp; the dense path keeps partial results per output dtype, with 16-bit outputs staged in a warpgroup-owned key buffer and then written out via TMA.

Source: https://github.com/tile-ai/TileOPs/pull/2665

3.4 TileOPs: Tensor core ceiling changed to the operand-set envelope (#2661)

Merged 10-20 22:27, 4 files +125/-82. Nightly run 39299002056 flagged GemmW4A8FwdOp at 105% and 108% of the tensor_core.fp8 ceiling; investigation showed the ceiling itself was too low: the original calibration took cuBLAS throughput on random operands, but under a 700 W power cap the operand values directly determine clocks, so a kernel drawing less power than random cuBLAS can run above that rate. gemm_throughput.py now also times all-zero operands, records the best rate per operand set in calibration_operands, and takes the maximum as the calibrated value—consistent with the existing envelope rule for HBM calibration; h200.yaml is re-labeled accordingly.

Source: https://github.com/tile-ai/TileOPs/pull/2661

3.5 TileOPs: Backend tests and torch-compile baseline runnable on non-CUDA devices (#2658)

Merged 10-20 13:17, 10 files +241/-48, fixing three TileOPs-side failures exposed by the MTT S5000 run in #2595. First, torch_musa renames PrivateUse1, so readers registered as "privateuseone" in test_backend.py and test_kernel_dispatch.py could not read it; they now resolve the device type through the privateuseone name directly. Second, torch_musa prints on import, breaking import checks that compare the entire stdout; a new tests/fresh_interpreter.py reads only a single marked result line, and seven such checks are switched over uniformly. Third, the torch-compile path without Triton is restored on non-CUDA environments.

Source: https://github.com/tile-ai/TileOPs/pull/2658

3.6 TileOPs: SM89 single-row single-column routed to vector GEMM (#2660)

Merged 10-20 10:35, 3 files +87/-11. Extends the existing CUDA-core GEMV implementation to SM89: the single-row left operand with transposed weights and the single-column right operand without transpose reuse the same kernel body, while the two-row crossover point remains calibrated for SM90. Tuning candidates are also filtered by the selected device’s shared memory budget, with the largest accepted staged ring at 96 KiB; the generated program declares at most 192 bytes of reduction scratch; single-row/single-column inputs whose contiguous storage starts at an unaligned element offset are handled by the existing alignment helper.

Source: https://github.com/tile-ai/TileOPs/pull/2660

3.7 TileOPs: Three builder cache and tuning contract fixes (#2662 / #2663 / #2664)

All three merged 10-20 13:16. #2662 adds a 32-entry LRU cache to the SM89 FP8 grouped GEMM builder, aligned with the existing SM90 builder and repo conventions, so repeated calls with the same four shape parameters reuse the JIT factory; #2663 adds the same 32-entry LRU to the two builders for dense GLA subchunk prefill, with the cache key retaining shape, scale, activation dtype, and gate dtype, and the launch thread config left as an inner factory parameter; #2664 restores the 12-input contract of the paged GQA ordinary tuning supplier—it previously expected 8 inputs but returned 9, missing three query/key/value scales, and removes the unsupported num_split candidate key. All three declare no device-side performance claims and unchanged compute bodies.

Source: https://github.com/tile-ai/TileOPs/pull/2662, https://github.com/tile-ai/TileOPs/pull/2663, https://github.com/tile-ai/TileOPs/pull/2664

3.8 TileOPs 11 PRs under review: SM89 advancing on three fronts

PRs updated in the window under review concentrate on SM89: NSA sparse attention top-k selection (#2675 extends selection to 2048 chunks, #2674 tiles by group48, #2673 fills in per-request top-k output slots), paged DSA (#2669 first support, #2670 reuses scale and shared value), and W4A16 narrow tiles (#2671 uses narrower tiles for small M, #2672 brings M64 in as well). Also #2667 drops GQA tuning tiles exceeding shared memory, #2654 reduces W4A8 work for small token counts, #2515 adds attention sinks to dense GQA, and #2490 proposes retiring the old GQA forward with KV cache append.

Source: https://github.com/tile-ai/TileOPs/pull/2675, https://github.com/tile-ai/TileOPs/pull/2669, https://github.com/tile-ai/TileOPs/pull/2672

3.9 TileFoundry: 0.0.3 announcement and test refactor (#247 / #246)

#247 adds three 10/2026 entries to the README’s Latest News: the 0.0.3 release, the Qwen3.8-27B prefill example (#229 / #236), and the Apple AMX prefill example (#244), and moves two 08/2026 entries into the collapsed Earlier list to keep the latest five. The commit message notes that the README is the PyPI long description (readme = "README.md" in pyproject.toml), so the announcement must land before tagging. #246 is a 51-file +655/-366 test refactor: local and CI reuse ccache and the torch extension cache (cache isolation between PRs, per-job statistics), two tests switch to comparing MMA layouts against a host-side compiled CuTe reference, replacing hand-written references and thousands of parameterized cases, and torch becomes a lazy proxy import that resolves dtypes on demand.

Source: https://github.com/tile-ai/TileFoundry/pull/247, https://github.com/tile-ai/TileFoundry/pull/246

3.10 Adopters: No pushes to TileKernels or FlashQLA in the window

DeepSeek’s TileKernels and Qwen’s FlashQLA had no commits in this window, last stopping at the 10-14 v2.1.0 release merge and the 10-14 SM120 fix merge, respectively. Both repos have zero PRs under review.

Source: https://github.com/deepseek-ai/TileKernels, https://github.com/QwenLM/FlashQLA

IV. Community, Tutorials, and Events

4.1 Community repo: Chinese systematic tutorial tilelang-tutorial created

huandu/tilelang-tutorial was created and pushed on 10-20, positioned as a “from zero to one TileLang Chinese systematic tutorial,” covering operator authoring, compile-time mechanisms, and both the NVIDIA and Ascend backends. Previously, Chinese-language material consisted mainly of individual blog posts and translations of official documentation; this is the first appearance of a systematic tutorial repo.

Source: https://github.com/huandu/tilelang-tutorial

4.2 Community repo: CANN community ops-tilelang created

Atlas-Ascend-Fork/ops-tilelang was created on 10-20, positioned as the CANN community’s TileLang high-performance operator repo for the Ascend NPU. It consolidates operator assets by “uniformly managing kernel implementations, automated test cases, standard workloads, and performance baselines,” with the goal of making Ascend-side TileLang operators reusable, verifiable, and sustainably evolving. This contrasts with the previous state in which Ascend operators were scattered across examples/ and cann-bench.

Source: https://github.com/Atlas-Ascend-Fork/ops-tilelang

4.3 Toolchain: devkit and VS Code extension active; lower trace moved out of the main repo entirely

easy-tilelang/tilelang-devkit (created in July) and tilelang-devkit-vscode (created 10-19, pushed 10-20) were both active in this window; the latter is positioned for exploring lowering passes, IR diffs, and CPU C JIT compilation within VS Code. Correspondingly, #3583 under review in the main repo (13 files, +106/-4390) removes the lower trace implementation, its dedicated environment configuration, and related tests from the main repo entirely, retaining only the shared compiler instrumentation interface so that the tracing tool can evolve independently. This continues the main repo’s “externalize debugging tools” direction since July.

Source: https://github.com/easy-tilelang/tilelang-devkit-vscode, https://github.com/tile-ai/tilelang/pull/3583

4.4 Community repos: tilelangGym and Hexagon backend experiments

PTO-ISA/tilelangGym (created 10-14, pushed 10-20) is used to test the performance sensitivity of different benchmarks and microbenchmarks under PTO lowering, in sync with progress on the Ascend PTO line. SoilSoi1/tilelang-hexagon was created on 10-20 as a community experiment for the Hexagon backend; the corresponding item in the main repo’s review queue is #2155 [feat] Add Hexagon HMX backend support (author Calaweh, who discussed the path forward around “decoupling the backends” back in May). In addition, sablin39/tilelang-cuda-skills (146 stars) continued to be updated during the window; it is a CUDA skill set for writing and debugging TileLang.

Source: https://github.com/PTO-ISA/tilelangGym, https://github.com/SoilSoi1/tilelang-hexagon, https://github.com/tile-ai/tilelang/pull/2155

4.5 Docs and versions: docs site auto-updated four times, VERSION still 0.1.15

tilelang.github.io was auto-updated four times during the window (10-20 12:16, 13:01, 16:08 and 10-21 00:49), all triggered by merges into the main repo. The main repo’s VERSION remains 0.1.15, and the latest milestone in the README is still the 09-30 Ascend 950 backend; TileOPs’ stats branch was refreshed at 10-20 22:42 with the last merge, with no new tag; TileFoundry’s 0.0.3 has yet to be tagged.

Source: https://github.com/tile-ai/tilelang.github.io, https://github.com/tile-ai/tilelang

V. Trend Observations

Compiler correctness became the main theme of this window, rather than feature expansion. Of the 9 merges into the main repo, 5 were silent-bug cleanups: vectorization assuming loops start at zero (#3579), missed shared-memory WAW detection (#2821), the MMA emitter silently shrinking the K atom (#2818), a crash in fragment reduce with retained dimensions (#2815), and predicates not following index bit-width promotion (#3550). What these defects share is that they do not raise errors—they only produce wrong results or miss barriers—making them the hardest class for users to locate in production. On the same day, TileOPs’ #2661 was also fixing the “performance ceiling definition,” indicating that the project now treats “trustworthy numbers” as an engineering goal on par with “running fast.”

The Ascend line is shifting from filling in examples to the training side. Three of the five merges are backward or recurrent operators (indexer_bwd, situ_glu_grad, LSTM/GRU), and situ_glu_grad directly aligns with the gated activation of Kimi K3 Stable LatentMoE and provides cross-validation data against aclnn on 910B3. Together with #3577’s alignment of DeepGEMM-Ascend configuration selection and the epilogue, Ascend-side coverage is expanding from inference forward passes to training backward passes, state recurrence, and large-model MoE gating.

PTO is becoming a second execution path alongside AscendC. #3512 under review is a 21k-line vectorization framework (T.Parallel → PTO VMI, targeting Ascend 950), #3516 proposes making tvm_ffi the default execution backend for the pto target, and together with a set of copy and predicate fixes in #3530, #3573, #3581, and #3582, the engineering effort on the PTO line has clearly exceeded the scale of isolated patches. At the same time, the main repo uses #3511 to add L0 local copy capability on the AscendC side—the two paths advance in parallel rather than one replacing the other.

The toolchain is spilling over into standalone repos. Within a single day, three new repos appeared (the Chinese tutorial, the CANN community operator repo, and the Hexagon backend experiment) along with a VS Code extension, and the main repo moved lower trace entirely to devkit (#3583, removing 4,390 lines). Community-side expansion is now outpacing the main repo’s module boundaries, consistent with the July “multi-backend language dialect” refactoring direction: the main repo narrows to semantics and IR, while tools and backend experiments move outside.

The explicit definition of CI criteria is worth noting. #3569 locks performance regressions to H100 and fails fast on mislabeled cards, #3564 splits the Ascend build and tests into separate steps of the same check, and #2661 relabels the tensor-core ceiling using an operand-set envelope—all three are about “making numbers comparable,” which directly affects the admission threshold for subsequent PRs.

Appendix: Sources and Verification Notes

Source Verification Table

Source Verification Result
tile-ai/tilelang (main) 8 commits and 9 merges within the window; VERSION still 0.1.15; 167 open PRs, of which 163 were updated within the window
tile-ai/TileOPs (main) 9 commits and 9 merges within the window; 16 open PRs, 11 updated within the window; stats branch refreshed at 22:42
tile-ai/tilelang-ascend (ascendc_pto) 5 commits and 5 merges within the window; 236 open PRs, 7 updated within the window
tile-ai/tilelang-hygon (main) 1 commit and 1 merge within the window; 3 open PRs
tile-ai/TileFoundry (main) 2 commits and 2 merges within the window; 1 open PR; 0.0.3 awaiting tag
tile-ai/tilelang-metax (dev) / musa / mlir-ascend No commits in any of the three repos within the window
tile-ai/TileRT / tilescale / DeepStack No commits in any of the three repos within the window (latest: 09-24, 08-03, 10-05 respectively)
deepseek-ai/TileKernels / QwenLM/FlashQLA No commits; latest activity in both remains at 10-14
tilelang.github.io docs site 4 automated updates within the window
Community and third-party repos 3 new repos (tilelang-tutorial, ops-tilelang, tilelang-hexagon), 3 active (devkit, devkit-vscode, tilelangGym)
Google News / Hacker News / arXiv Multiple queries in Chinese and English returned no reports directly related to TileLang; the latest related arXiv paper remains dated 2026-07-24

Additional notes: For the open-PR queue, the search API returned updated_at timestamps for 64 PRs clustered around 10-20 11:30. A spot check of three of these found no comments, reviews, or branch-push events at the corresponding times, so these were judged to be a platform-side batch recalculation and were not counted as development activity. Open-PR counts are based on each repo’s is:open count.

Full Source List