Research window: 2026-10-19 07:00 ~ 2026-10-20 07:00 (Beijing time, 24 hours).

Sources: GitHub (full check of pushes across 29 repos in the tile-ai org; 9 repos had pushes within the window: TileOPs, TileOPs-nightly, TileOPs.github.io, tilelang, tilelang.github.io, TileFoundry, tilelang-ascend, tilelang-hygon, tilelang-mlir-ascend; 36 merges within the org window [TileOPs 19, tilelang 11, TileFoundry 3, TileOPs.github.io 1, tilelang-ascend 1, tilelang-mlir-ascend 1], 52 under review [tilelang 24, tilelang-ascend 15, TileOPs 11, tilelang-hygon 2]; per-branch checks of non-default branches [ascendc_pto, snapshots, stats]) + release page and version file checks + spec statistics branch checks + adopter repo checks (TileKernels / FlashQLA) + community repo checks + nightly pipeline checks + multiple Google News queries in Chinese and English (via proxy) + Hacker News + arXiv.

This Issue’s Index

  • Today’s Highlights: Two SM89 GEMMs promoted in one day, TileOPs spec and benchmark coverage both report 205/205, main repo brings Windows ARM64 into CI (10-19)
  • I. Core Project Progress
    • 1.1 Main repo: Windows ARM64 enters CI, CUDA 13.4 arm64 package install and clang compatibility layer (#2962) (10-19)
    • 1.2 Main repo: T.cumsum on shared buffers adds thread offset under warp specialization (#3536) (10-19)
    • 1.3 Main repo: call_extern’s bare data variable conservatively marked as written (#2618) (10-19)
    • 1.4 Main repo: lower trace splits host and device source, switches to editable baseline (#3496) (10-19)
    • 1.5 Main repo: Autotuner passes through profiler params, ROCm FP4 constant printing, and two CI maintenance items (#3337 / #3548 / #3565 / #3567) (10-19)
  • II. Multi-Backend Adaptation (Ascend / MetaX / Hygon / Moore Threads)
    • 2.1 Ascend: Host operators and device kernels correlated under msprof (#3321) (10-19)
    • 2.2 Ascend: Out-of-VF scalar sqrt uses standard math library, PTO Ramp emits typed vectors (#3466 / #3535) (10-19)
    • 2.3 Ascend: Chinese API docs and test cases completed for four elementwise operators (#1657) (10-19)
    • 2.4 Ascend review queue at 15 items: GLM-5.3 compression operators and three backward operators (10-19)
    • 2.5 Hygon: Two items under review complete MLS window constant K and register pipeline (#25 / #18) (10-19)
    • 2.6 MetaX / Moore Threads / MLIR-Ascend: No new pushes on either side, MLIR line fixes TVM isolation (#204) (10-19)
  • III. Ecosystem and Adopters (TileOPs / TileFoundry / Operator Libraries)
    • 3.1 TileOPs: SM89 block-scaled FP8 grouped GEMM and INT8 W8A8 merged same day (#2659 / #2655) (10-19)
    • 3.2 TileOPs: Five foundry operators complete MLA paging, KV write, and fused normalization (#2642 / #2635 / #2639 / #2634 / #2651) (10-19)
    • 3.3 TileOPs: GQA paged FP8 forward promoted to implemented, 36 cases benchmarked against FA3 (#2648) (10-19)
    • 3.4 TileOPs: Per-point performance closure series for linear attention and GEMM (#2650 / #2645 / #2637 / #2636 / #2641 / #2640 / #2646 / #2652) (10-19)
    • 3.5 TileOPs: Mamba-1 selective scan lands, MoE routing enumeration adds convergence cap (#2638 / #2653) (10-19)
    • 3.6 TileOPs: Spec and benchmark coverage both report 205/205, nightly report adds operator column (#2656) (10-19)
    • 3.7 TileFoundry: Apple AMX support and Qwen prefill example run on M2 Pro (#244 / #240 / #245) (10-19)
    • 3.8 Adopters and nightly pipeline: TileKernels / FlashQLA no pushes, snapshot advances to 10-20 (10-20)
  • IV. Community, Tutorials, and Events
    • 4.1 Docs: Six new operators written into API pages, main repo docs site auto-updates (#77) (10-19)
    • 4.2 Community repos: W4A16 kernel practice repo and CUDA debugging skills repo come into view (10-19)
    • 4.3 Version lines: Main repo still on 0.1.15, TileOPs continues to pin 0.1.12 (10-19)
    • 4.4 Media and academia: Three news search hits all not directly relevant, no new arXiv papers (10-19)
  • V. Trend Observations
    • 5.1 SM89 becomes the default target for new operators
    • 5.2 Linear attention settles into “one matmul per chunk + strategy selected by SM wave”
    • 5.3 TileFoundry steps outside CUDA: Apple AMX and Qwen prefill
    • 5.4 Observability becomes the main line of compiler hardening
    • 5.5 Ascend operator library shifts toward dialogue-model-specific operators
  • Appendix: Sources and Verification Notes
  • Full Source List

Today’s Highlights: Two SM89 GEMMs promoted in one day, TileOPs spec and benchmark coverage both report 205/205, main repo brings Windows ARM64 into CI (10-19)

This window’s main activity is still during China-time night hours: 36 merges within the organization, with TileOPs accounting for 19 alone, among which SM89 (Ada-class) block-scaled FP8 grouped GEMM and INT8 W8A8 GEMM landed the same day, complemented by five new operators that complete MLA paging, KV cache write, QK-Norm-RoPE fusion, and per-token quantized RMSNorm in one pass; the organization spec statistics branch was then refreshed to “implemented 205/205, benchmarked 205/205,” meaning the operator library’s self-reported spec coverage and benchmark coverage are both at full marks simultaneously. The main repo tilelang merged 11 items, the heaviest being bringing Windows ARM64 into the release pipeline (12 files, CUDA 13.4 arm64 install script and clang compatibility headers), plus two correctness fixes (T.cumsum on shared buffers, call_extern write annotation) and one debugging infrastructure overhaul (lower trace splitting host and device source). On the backend side, Ascend correlates host operators with device kernels under msprof, Hygon has two items under review completing the register pipeline and constant K addressing, and TileFoundry for the first time runs the Qwen prefill example on the Apple M2 Pro’s AMX units for 128 tokens.

I. Core Project Progress

1.1 Main repo: Windows ARM64 enters CI, CUDA 13.4 arm64 package install and clang compatibility layer (#2962)

This PR brings Windows on ARM into the release pipeline as a formal build target: it adds a PowerShell install script that pulls the CUDA 13.4 windows_arm64 local installer from NVIDIA’s pre-release channel and places it at a fixed path; adds a CMake FindPipCUDAToolkit module and a windows_arm64_clang_compat.h compatibility header to resolve header and builtin differences of the MSVC toolchain on ARM64; and adjusts pyproject and both requirements files, along with changes to the layout module and MSVC helper module to adapt to the new platform. 12 files, 356 lines added, 45 lines removed. The organization had previously added ROCm and Ascend backends in succession; this PR makes Windows ARM64 the third non-x86 delivery surface, a direct usability improvement for users doing local kernel development on Snapdragon X-series laptops.

Source: tile-ai/tilelang#2962 (10-19)

1.2 Main repo: T.cumsum on shared buffers gets thread offset under warp specialization (#3536)

After warp specialization assigns producers and consumers to different warps, the thread ID computed by scan-type primitives on shared buffers is still based on the whole CUDA block, causing cumsum row attribution to be misaligned. The change introduces a thread_offset parameter into both the CUDA and HIP scan templates, passed in from the thread lower bound (the minimum of thread_bounds) in the underlying parameters, so the template can realign lane and row indices; the backend generic implementation and Python-side test cases are updated in sync. 4 files, 101 lines added, 38 lines removed. This kind of issue only surfaces when warp specialization is actually enabled and the buffer lands in shared memory—an edge condition fed back after scale-up usage.

Source: tile-ai/tilelang#3536 (10-19)

1.3 Main repo: Bare data variables in call_extern conservatively marked as written (#2618)

Read-only parameter annotation previously relied on alias analysis to determine whether a buffer is written, but when an external call (call_extern) writes through a bare pointer, the analysis cannot see the write, so it is misjudged as read-only and then constant-folded or reused early. The change specifically recognizes call_extern in this pass, conservatively marking all its bare data variables as written, and adds 69 lines of test cases covering the “call_extern writes output buffer” pattern. The direction is to forgo an optimization rather than perform an incorrect one, in line with a recent batch of correctness fixes in the main repo.

Source: tile-ai/tilelang#2618 (10-19)

1.4 Main repo: lower trace splits host and device source, switches to editable baseline (#3496)

The lower trace debugging tool previously emitted only one generated source file, mixing host-side wrappers with device-side kernels, making changes hard to roll back. The change splits the two sides into independent artifacts: the device side outputs codegen_device.cpp with its .original baseline and .latest version, while the host side emits codegen_host.cpp and baseline files of the same structure when host code generation runs, with report.html symlinked to the most recent run; documentation is rewritten in sync for the edit and recompile workflow. 6 files, 121 lines added, 63 lines removed.

Source: tile-ai/tilelang#3496 (10-19)

1.5 Main repo: Autotuner passes through profiler params, ROCm FP4 constant printing, and two CI maintenance PRs (#3337 / #3548 / #3565 / #3567)

#3337 is only three lines, but it fixes the measurement semantics of autotuning: warmup, rep, and timeout on the decorator were not previously passed to the tuner, so users changing these three parameters on the decorator had no actual effect; they are now passed through. #3548 adds printing of FP4 (e2m1) floating-point constants on the ROCm side; since this type can only be constructed from raw bytes, it is changed to generate constants on the device side via a helper function converting from float32, avoiding HIP codegen errors. The other two are maintenance changes: bumping cibuildwheel from 4.2 to 4.3, and adding a CodeRabbit reviewer for the ROCm line.

Source: tile-ai/tilelang#3337, #3548, #3565, #3567 (10-19)

II. Multi-Backend Adaptation (Ascend / MetaX / Hygon / Moore Threads)

2.1 Ascend: Host Operators and Device Kernels Correlated Under msprof (#3321)

Previously, the Ascend-side profiler could only report device kernel durations, with no correspondence between host operators and kernels, so samples obtained by auto-tuning could not be attributed to specific calls. This PR adds a native profiling channel: at build time it probes CANN’s profiling headers (compatible with both the msprof and profiling installation layouts), enabling it if present and skipping it if not, without introducing a user-facing compile switch; on the runtime side it adds ascend_profiling.h and a host-side profile module to correlate host operator dispatch with device kernel execution in call order, and lets the grouped compilation path reuse the same reporting. A total of 13 files, 676 lines added, 13 lines removed — a structural completion of the Ascend line’s measurement capability.

Source: tile-ai/tilelang#3321 (10-19)

2.2 Ascend: Out-of-VF Scalar sqrt Routed to the Standard Math Library, PTO Ramp Emitted as Typed Vectors (#3466 / #3535)

#3466 handles the case where scalar sqrt falls outside the vectorized domain (VF): the lower layer previously lowered it uniformly to sqrtf, but that implementation is unavailable on scalar cores; the change routes it to AscendC::Std::sqrt when outside the domain and the type is float32, pulling in the standard math headers as needed, with 126 lines added including test cases. #3535 fixes how Ramp expressions are emitted in PTO code generation, assembling typed vectors from per-lane expressions instead, with test cases covering vectorized store generation and execution for both parallel-index and explicit-stride Ramps.

Source: tile-ai/tilelang#3466, #3535 (10-19)

2.3 Ascend: Chinese API Docs and Test Cases Completed for Four Elementwise Operators (#1657)

The Ascend adaptation repo completes Chinese API documentation for the four elementwise operators under T.tile — relu, leaky_relu, sigmoid, and silu — specifying functionality, parameters, return values, and typical usage (e.g., the negative-slope semantics of leaky_relu), along with matching test cases and documentation entry points: 6 files, 451 lines added, 19 lines removed. This is a rare documentation-centric merge on the Ascend line, indicating that the repo’s operator surface has reached the stage of needing to commit to semantics externally.

Source: tile-ai/tilelang-ascend#1657 (10-19)

2.4 Fifteen Ascend PRs Under Review: GLM-5.3 Compression Operator and Three Backward Operators (10-19)

The Ascend repo is the most concentrated area of review activity in this window (15 PRs). The operator side shows a clear conversational-model orientation: GLM-5.3’s kpool compression operator (#1910), KDA’s chunk backward (#1895), indexer backward (#1887), and situ_glu plus its gradient (#1891 / #1877). On the example side, two cann-bench entries are added for lstm and gru (#1892 / #1902). Two compiler-side PRs concern stability: #1907 preserves block annotations and ND offsets in UB-to-L1 staging, and #1903 fixes publication of the concurrent kernel cache and recovery after the cache is deleted. Another five PRs verify API facts for bitwise operators (#1651 / #1655 / #1656 / #1659 / #1893), of which #1893 is a resubmission after being reverted last week and the other four are new verifications.

Source: tile-ai/tilelang-ascend#1910, #1895, #1887, #1891, #1907, #1903 (10-19)

2.5 Hygon: Two PRs Under Review Complete the MLS Window Constant K and Register Pipeline (#25 / #18)

The Hygon repo had no merges on its default branch in this window, but both PRs under review made substantive progress. #25 fixes MLS resource promotion losing the constant window offset after loop unrolling: it first verifies the non-updated axis before deciding between single-axis update and forward-difference addressing, conservatively rebuilds the window when necessary, and adds a regression to the existing MLS tests. #18 adds a register pipeline to the HCU backend that can be layered on the existing shared-memory pipeline, inserting the corresponding commit and barrier instructions per pipeline stage, and enabling warp_diverge when the warp count exceeds 4; the PR states that example_gemm performance is already close to rocblas.

Source: tile-ai/tilelang-hygon#25, #18 (10-19)

2.6 MetaX / Moore Threads / MLIR-Ascend: No New Pushes on the First Two, MLIR Line Fixes TVM Isolation (#204)

tilelang-metax’s last push was on 10-16 and tilelang-musa’s on 09-30; neither had commits in this window, which is normal silence. tilelang-mlir-ascend merged a TVM isolation fix (#204) addressing mutual contamination between the repo and TVM’s namespaces and symbol visibility — small in scope but directly affecting link stability when multiple backends coexist.

Source: tile-ai/tilelang-mlir-ascend#204 (10-19)

III. Ecosystem and Adopters (TileOPs / TileFoundry / Operator Libraries)

3.1 TileOPs: SM89 block-scaled FP8 grouped GEMM and INT8 W8A8 merged the same day (#2659 / #2655)

#2659 extends block-scaled FP8 grouped GEMM (MoE scenario) to SM89: four explicit configurations, six benchmark cases including copies, with tests covering unknown keys, illegal tile sizes, masked counts and slab tail blocks, tuning, output aliasing, unaligned inputs, idle expert preservation, and input immutability; 35 items each pass on two TileLang baselines (0.1.12 and the 0.1.15 dev build); cases grow from 42 to 77, with 12 new SM89 cases. #2655 enables INT8 W8A8 GEMM on the same architecture; 13 SM89 interface cases and the existing 29 INT8 benchmark workloads all pass correctness checks against vLLM, and it explicitly does not claim SM90 results. Together, the two mean TileOPs’ low-precision GEMM no longer targets Hopper as its sole target.

Sources: tile-ai/TileOPs#2659, #2655 (10-19)

3.2 TileOPs: Five foundry operators fill in MLA paging, KV writes, and fused normalization (#2642 / #2635 / #2639 / #2634 / #2651)

This batch all comes out of TileFoundry’s spec pipeline: each operator first has an HIR spec and reference implementation, then placement, scheduling, and a runtime twin. #2642 adds MLA paged forward, walking the page table per request, fp32-accumulated scoring, online softmax, returning output and lse; six rows of cases align with the reference within 4e-3 absolute error, and the row is judged compute-bound by two multiply-accumulates at 576 and 512 columns. #2635 adds MLA KV cache writes, concatenating kv_c and k_pe per token, rotating in fp32 before storing, scaling by scale and clamping to E4M3; six rows of cases pass against vLLM’s same-named interface. #2639’s QK-Norm-RoPE fusion covers seven row/precision combinations and supports both NeoX and adjacent-pair rotation layouts. #2634’s per-token quantized RMSNorm fuses residual addition; 12 workloads align with vLLM’s same-named interface, implemented as one row per CTA, 128 threads within 4096 columns, and 512 threads for longer ones. #2651 adds the INT8 W8A8 operator wrapper.

Sources: tile-ai/TileOPs#2642, #2635, #2639, #2634, #2651 (10-19)

3.3 TileOPs: GQA paged FP8 forward moves to implemented, 36 cases benchmarked against FA3 (#2648)

This PR lets GQA paged forward accept FP8 Q and KV directly and advances the operator status from spec to implemented. The reference implementation writes HIR by request and KV head dimension, stacks query heads in groups into scoring rows, treats each visible page as a key tile, and multiplies FP8 operands after dequantizing by their respective scales; all 36 cases pass, including NaN and Inf checks. The comparison target is FA3’s equivalent paged implementation, expanded into corresponding shapes by “per request, per KV head” descale. The accompanying change touches 17 files and adds 2,601 lines, including multiple kernel paths for paged decode, batch-1 decode, FP8 decode, warp specialization, and RoPE preprocessing.

Source: tile-ai/TileOPs#2648 (10-19)

3.4 TileOPs: Series of per-point performance closures for linear attention and GEMM (#2650 / #2645 / #2637 / #2636 / #2641 / #2640 / #2646 / #2652)

Eight [Perf] PRs continue last week’s closure rhythm with a highly consistent pattern: compress each chunk’s matrix multiply into one, move or merge synchronization points, and choose strategies by hardware wave count. #2650 changes GDN prefill chunk inversion to warp-group solving, bounded by “about seven warp-group solvers per SM,” with single-warp still more worthwhile below one wave; #2645 makes DeltaNet forward state do only one matrix multiply per chunk; #2637 stops GLA backward state gradients from inserting matrix multiplies along their chain; #2636 moves each tile’s store in batched GEMM under the next tile’s first WGMMA to overlap writeback; #2641 switches long-row reductions to 512-thread folding; #2640 makes the row of the 2D max-pooling index kernel read into L2 with evict-last; #2646 bypasses the full-range bf16 division scaling when the scale factor is exactly 1; #2652 implements float32 remainder and floor division rounding-down using approximate reciprocals.

Sources: tile-ai/TileOPs#2650, #2645, #2637, #2636, #2641, #2640, #2646, #2652 (10-19)

3.5 TileOPs: Mamba-1 selective scan lands, MoE routing enumeration gains a convergence cap (#2638 / #2653)

#2638 adds Mamba-1 selective scan forward; nine rows of workloads cover Mamba-2.8B’s 4096-token prefill and single-token decode, 2.8B batch-64 decode, 1.4B prefill, 130M without gating, packed prefill with sequence indices, grouped state, and bare scan; the reference implementation is checked in together with placement and scheduling generators, marking state-space models’ formal entry into the operator list. #2653 fixes MoE grouped GEMM’s routing enumeration: previously it enumerated grouped routes in full, wasting time when the combination count exceeded limits; now it stops enumerating once the union exceeds the cap.

Sources: tile-ai/TileOPs#2638, #2653 (10-19)

3.6 TileOPs: Spec and benchmark coverage both report 205/205, nightly report adds an operator column (#2656)

The org spec stats branch refreshed immediately after the last merge, with badge data reading “implemented 205/205, benchmarked 205/205,” both full, corroborating the operators continuously added this period. #2656 adds two things to the nightly report: listing operators not measured in the current period as a separate “new operators” column, and changing historical data item reads from the old string representation to JSON parsing, discarding any non-mapping content; cases grow from 43 to 47. A piece of historical data #2656 itself recounts is also worth recording: the 10-18 nightly report (stats window 10-05 to 10-17) listed 109 improvements, 6 new operators, 121 rows total, of which W4A8 GEMM accounted for 98 rows.

Sources: tile-ai/TileOPs#2656, TileOPs spec stats branch (10-19)

3.7 TileFoundry: Apple AMX support and Qwen prefill example run on M2 Pro (#244 / #240 / #245)

#244 brings four AMX operations (X/Y load, FP16 outer product with FP32 accumulation, Z store) into TileFoundry, and lets Copy and Fill land on Apple core and AMX executor scopes; the example directory provides whole-model HIR, scheduled HIR, a Python runtime twin, and a C++ projection kernel, building and caching local kernels on first use, with weights reusing a prepared GGUF Q8_0. Measured on M2 Pro, both Qwen3-1.7B and Qwen3.5-4B complete 128-token prefill, with finite output logits and next-token IDs of 1813 and 306 respectively. This is the first time the TileLang ecosystem has put a whole-model inference example on a non-CUDA accelerator. #240 fixes four CUDA-side lowering gaps (effect-form Cast with no generating handler, Fill writing to a kernel-parameter raw pointer, slice coordinates going through Dim arithmetic that cannot be resolved), changing only the codegen directory, 45 lines added and 10 removed. #245 unifies the analysis layer’s valuation context and scope snapshots.

Sources: tile-ai/TileFoundry#244, #240, #245 (10-19)

3.8 Adopters and nightly pipeline: TileKernels / FlashQLA no pushes, snapshot advances to 10-20 (10-20)

deepseek-ai/TileKernels remains at the 10-14 v2.1.0 release merge, and QwenLM/FlashQLA at the 10-14 fix commit; neither had pushes in the window, so the adopter side is silent today. TileOPs-nightly’s snapshots branch added one snapshot in the window (10-20 05:39), the previous one at 10-19 05:41, with nightly benchmarks holding to a once-daily cadence.

Source: TileOPs-nightly snapshots (10-20)

IV. Community, Tutorials, and Events

4.1 Docs: Six new operators added to the API page, main repo docs site auto-updated (#77)

As operators were merged, the TileOPs docs site added six new implementations to the API page (#77), documenting the calling conventions and current status for each, following the “implemented means it goes on the page” rule established last week. The tilelang main repo docs site had one automated build push during the window, with no manual content changes.

Source: tile-ai/TileOPs.github.io#77 (10-19)

4.2 Community repos: W4A16 kernel practice repo and CUDA debugging skills repo come into view (10-19)

Several third-party repos around TileLang appeared on the community side: fanyuxiao-ui/w4a16-tilelang, created 10-10, uses TileLang plus hand-written CUDA to do GEMM and GEMV for W4A16 quantized inference on A800 (SM80); sablin39/tilelang-cuda-skills, created this May and already at 145 stars, provides a skills pack for writing TileLang and debugging with the CUDA toolchain, and its author is also an active TileFoundry contributor; localizethedocs/tilelang-docs-l10n does official docs localization; chaigua/tilelang-agent was newly created on 10-19. All four are community-initiated and are not official organization repos.

Source: fanyuxiao-ui/w4a16-tilelang, sablin39/tilelang-cuda-skills, localizethedocs/tilelang-docs-l10n (10-19)

4.3 Version line: Main repo still on 0.1.15, TileOPs continues to pin 0.1.12 (10-19)

The main repo version file is still 0.1.15, corresponding to the 09-30 release; there were no new tags or releases during the window. TileOPs’s dependency declaration still hardcodes 0.1.12; last week’s PR attempting to upgrade to 0.1.15 has been closed, and the newly merged SM89 cases this period also ran against both 0.1.12 and the 0.1.15 dev build, indicating the upgrade gate still requires dual-baseline validation.

Source: tile-ai/tilelang VERSION, tile-ai/TileOPs pyproject (10-19)

4.4 Media and academia: Three news search hits, none directly relevant; no new arXiv papers (10-19)

Multiple Google News queries in Chinese and English (TileLang, tile-ai, TileOPs, TileFoundry, tilelang operators, etc.) returned only three hits during the window: two industry reports on DeepSeek and Huawei chips (The Information, Business Upturn), and Prime Intellect’s prime-rl 0.10.0 release post; after checking each one, no specific TileLang facts were found in the readable content, so they are treated as not directly relevant and not counted as items. Hacker News searches for tilelang returned no relevant hits, and the most recent relevant paper from an all-field arXiv search is still TileSight (a tile-centric GPU performance analysis model) from 07-24, with nothing new during the window.

Source: Google News TileLang search, arXiv TileLang search (10-19)

V. Trend Observations

5.1 SM89 becomes the default target for new operators

Yesterday TileOPs’s focus was still W4A8 on Hopper and SM90 cluster collaboration; in this window both new GEMMs target SM89 first and explicitly state in their PRs that they do not claim SM90 results. Ada-class cards (L40S, 4090 and the like) are the main hardware in the hands of domestic developers, so landing low-precision GEMM on SM89 first means the operator library is starting to prioritize by “availability” rather than just “peak performance.”

5.2 Linear attention settles into “one matmul per chunk + strategy chosen by SM wave count”

GLA, GDN, KDA, and DeltaNet together saw eight performance changes this period, and the techniques converged on two: compressing the matmuls along the chunk chain to one per block, and deciding between a grouped solve and a single warp based on how many warp groups an SM can hold. This “compute the wave count first, then pick the kernel” approach was previously seen only in hand-written GEMM libraries; it has now entered the default path of the operator library.

5.3 TileFoundry steps outside CUDA: Apple AMX and Qwen prefill

TileFoundry has always positioned itself as “an operator factory for agents,” but previously all examples were on NVIDIA. This period’s AMX support plus a full Qwen prefill running on an M2 Pro show that its three-layer abstraction of spec, layout, and scheduling is not tied to CUDA and can be lowered to Apple’s matrix coprocessor. If this line continues, TileFoundry’s positioning will shift from “a frontend for TileLang” to “a cross-accelerator spec-to-kernel compiler.”

5.4 Observability becomes the main line of compiler hardening

Three changes this window point to the same thing: making compiler output measurable and attributable. Lower trace writes host and device source to separate files, Autotuner actually passes decorator parameters through to measurement, and Ascend matches host operators with device kernels under msprof. Now that operator coverage is nearly complete (spec statistics already report 205/205), the remaining gaps must be found through measurement rather than by adding operators.

5.5 Ascend operator library turns to dialogue-model-specific operators

In Ascend’s review queue appear GLM-5.3’s kpool compression, the backward passes for KDA and indexer, and situ_glu plus its gradient; these are not general-purpose operators but components of specific dialogue model architectures. Together with last week’s PTO auto-vectorization, the focus of the Ascend line has shifted from “running TileLang on Ascend” to “building the key operators of mainstream domestic models on Ascend first.”

Appendix: Sources and Verification Notes

  • This window is a regular 24-hour window covering 10-19 07:00 to 10-20 07:00, and does not overlap with the previous issue (the three-day window from 10-16 07:00 to 10-19 07:00).
  • The organization-level repository list and push status were fully retrieved via the GitHub API; 9 of the 29 repositories had pushes within the window. Commits on each repository’s main branch were checked one by one via the Atom feed, and non-default branches (ascendc_pto in tilelang-ascend, snapshots in TileOPs-nightly, stats in TileOPs) were verified separately.
  • The merged and in-review counts were taken from ground-truth searches via the GitHub search API (one each for is:merged and is:open, with the window start timestamp), rather than accumulated from per-repository pull lists, to avoid double counting.
  • The anonymous quota for the organization API was exhausted in the later part of collection, so PR bodies and change statistics were read from web pages and patch files instead; this did not affect fact-checking of the items. Merged status is always based on the is:merged search results.
  • The spec and benchmark coverage numbers were taken from badge data on the organization’s stats branch, which was refreshed after the last merge within the window; these are the project’s self-reported figures.
  • Nightly snapshot counts were determined by converting UTC times from the snapshots branch Atom feed to Beijing time and checking whether they fall within the window.
  • The three news-side hits were each checked individually; two of the industry reports could not be confirmed in their readable content to have a specific connection to TileLang, so they were treated as unverified and excluded from this issue’s items. Both arXiv and Hacker News had zero new items.
  • The report contains no local environment information.

Full Source List