Research window: 2026-10-15 07:00 ~ 2026-10-16 07:00 (Beijing time, 24 hours).

Sources: GitHub (full check of pushes across 29 repos in the tile-ai organization; 7 repos had pushes within the window: tilelang, TileOPs, TileFoundry, tilelang-hygon, tilelang-mlir-ascend, tilelang.github.io, TileOPs.github.io; 15 merges, 24 new opens, and 172 in-review updates within the organization window; per-branch checks of non-default branches [distributed / v0.1.12-release / v0.1.15-release / snapshots]) + release page checks + adopter repo checks (TileKernels / FlashQLA) + community repo checks (tilelangGym, SuperNPUBench, puzzles-ascend, BM1690 pipelines, tilelang-cuda-skills, TileMC, easy-tilelang, tilelang-debugger, SwHwCodesign) + overnight pipeline checks + Google News multi-query searches in Chinese and English (via proxy) + Hacker News + arXiv.

Index

  • Today’s Highlights: Main repo PTO execution routing merged, TileOPs attention hat-trick and TileFoundry instance slots land — Hygon patches folded into the v0.1.12 line (10-15)
  • I. Core Project Progress
    • 1.1 Main repo: Ascend PTO execution routing — ascend × pto direct connection to PTO codegen (#3316) (10-15)
    • 1.2 Main repo: JIT rejects unhashable compile-time parameters (#3417); test compile-time elimination (#3517) (10-15)
    • 1.3 Main repo in review: cumsum shared buffer warp specialization fix newly opened (#3536); seven PTO family items advancing (10-15)
  • II. Multi-Backend Adaptation (Ascend / MetaX / Hygon / Moore Threads)
    • 2.1 Hygon: block-scaled async copy layout opened and closed same day (#21, landed in v0.1.12-release); distributed branch continues pushing (10-15)
    • 2.2 Ascend: four new opens in the ascend repo — dav-3510 gemm_v0 silent numerical error in review (#1900); open PRs 233 to 237 (10-15)
    • 2.3 MetaX and Moore Threads: no pushes within the window; MLIR Ascend knowledge base correction merged (#202) (10-15)
  • III. Ecosystem and Adopters
    • 3.1 TileOPs: attention hat-trick merged — varlen GQA aggregation, paged GQA full features, and paged KV write (10-15)
    • 3.2 TileOPs: three foundry performance items — W4A16 load reordering, sigmoid without IEEE division, SM89 scan widening (10-15)
    • 3.3 TileFoundry: instance slot refactor (#232), lowering contract (#233), and Qwen3.8-27B prefill example (#236) merged (10-15)
    • 3.4 Overnight pipeline: no new snapshots observed within the window (10-15)
  • IV. Community, Tutorials, and Events
    • 4.1 PTO-ISA: tilelangGym SimtVF suite takes shape; SuperNPUBench group normalization single-pass reduction (10-15)
    • 4.2 Third-party community: six BM1690 board-level diagnostics; tilelang-cuda-skills’ first external audit of TileFoundry (10-15)
    • 4.3 Media and academia: zero new items on Google News / Hacker News / arXiv within the window (10-15)
  • V. Trend Observations
    • 5.1 PTO moves from “standalone target” to “first-class execution path”
    • 5.2 Attention family consolidation: long-context inference operator surface completed
    • 5.3 Hygon dual-line maintenance and distributed direction
    • 5.4 TileFoundry enters external audit phase
  • Appendix: Materials and Verification Notes
  • Complete Source List

Today’s Highlights: Main-repo PTO execution routing merged, TileOPs attention hat-trick and TileFoundry instance slots land — Hygon patch folded into the v0.1.12 line (10-15)

Date: 2026-10-15　Sources: PTO execution routing (#3316) / varlen GQA gather (#2537) / instance slot refactor (#232) / block-scaled async copy layout (#21) / dav-3510 gemm_v0 (#1900) / TileOPs PR list / TileFoundry PR list

Within the 24-hour window, the org merged 15 PRs (3 in the main repo, 6 in TileOPs, 3 in TileFoundry, 1 in Hygon, 1 in MLIR Ascend, 1 in the docs site), opened 24 new ones, and updated 172 under review; 7 repositories saw pushes. Three main threads run through this window: the main repo’s PTO execution path opening up, TileOPs’ attention hat-trick closing out alongside two core TileFoundry refactors landing, plus Hygon folding its block-scaling patch into the v0.1.12 release line.

  • Main-repo PTO execution routing (#3316): the target="ascend" and execution_backend="pto" combination now takes effect, with compilation wired directly to the PTO device code generator; the auto path keeps AscendC/TVM-FFI unchanged (see 1.1).
  • TileOPs attention hat-trick (#2537 / #2516 / #2539): varlen GQA gather with pipelined sliding window, paged GQA’s RoPE / window / gather, and the paged KV write operator PagedKVCacheWriteFwdOp all merged in the same window (see 3.1).
  • TileFoundry dual refactor (#232 / #233): module child-node instance slotting and the lowering / printer contract land, plus a Qwen3.8-27B cross-ridge-line prefill example (#236) (see 3.3).
  • Hygon #21 lands in the v0.1.12 line: the block-scaled GEMM async copy layout was opened and merged the same day, targeting the v0.1.12-release maintenance line (see 2.1).
  • Ascend key PR under review #1900: a silent numerical error in gemm_v0 on dav-3510 — a precision-failure class of problem with no exceptions, no NaNs, and a numerical distribution that is nearly indistinguishable (see 2.2).

I. Core Project Progress

1.1 Main Repo: Ascend PTO Execution Routing — ascend × pto Direct PTO Codegen (#3316) (10-15)

Date: 2026-10-15　Source: PTO Execution Routing (#3316) / Main Repo PR List

  • Execution Routing (#3316): Makes the combination of target="ascend" and execution_backend="pto" actually take effect — an explicit PTO execution backend specializes the native Ascend target into a PTO target variant (preserving target attributes such as arch) before backend resolution, and compilation accordingly selects the PTO backend and PTO device code generator (CodeGenTileLangPTO, i.e. codegen_pto.cc). The implementation adds an execution-aware target normalization hook attached at BackendContext creation; the Ascend-specific normalizer handles the mapping, and device code generation switches to PTO_CODEGEN and target.build.tilelang_pto_without_compile.
  • Path Semantics (PR behavior table): ascend × auto maintains the AscendC + TVM-FFI path; ascend × tvm_ffi / cython goes through AscendC; ascend × pto and the existing target="pto" shorthand both go through the PTO backend. The documentation provides the equivalent environment configuration: TILELANG_DEFAULT_TARGET=ascend plus TILELANG_EXECUTION_BACKEND=pto. Tests cover direct context resolution, target attribute preservation, cache dispatch, and environment variable selection.
  • Connections: Continues from the example target selection merged on 10-14 (#3474, CI runs all Ascend examples once for each of the ascend and pto targets) and the in-review PTO family (tvm_ffi execution backend #3516, VMI vectorization #3512, SS buffer #3514, partial L0 copy pitch #3511) — the Ascend side’s “dual-path coexistence” is moving toward “one target, two execution backends.”

1.2 Main Repo: JIT Rejects Unhashable Compile-Time Arguments (#3417); Test Compile Time Elimination (#3517) (10-15)

Date: 2026-10-15　Source: JIT Hash Validation (#3417) / Test Compile Time (#3517)

  • JIT Rejects Unhashable Compile-Time Arguments (#3417): JIT specialization now requires compile-time arguments and default values to be hashable — unhashable default values raise TypeError at JIT wrapper creation, and explicitly passed unhashable arguments are rejected before kernel lookup or factory execution; this prevents mutable default values from silently reusing stale kernels and unifies the lazy and eager argument contracts. Validation uses hash() (including tuples containing unhashable values); the call-form cache checks hashability first before taking the “last call equality” shortcut; container content normalization is removed, and runtime tensor arguments still do not enter the specialization key. Verification: native source rebuild passes, argument binding and related suites total 91 passed, no skips.
  • Test Compile Time Elimination (#3517): Four packed-type CUDA source helper functions in
    test_tilelang_issue_2994.py now use target.build.tilelang_cuda_without_compile (only fetch generated source, no full build); these helpers only ever checked generated source and no longer bear the regular build overhead.

1.3 Main Repo In Review: cumsum Shared Buffer Warp Specialization Fix Newly Opened (#3536); Seven PTO Family Advances (10-15)

Date: 2026-10-15　Source: cumsum Fix (#3536) / PTO tvm_ffi (#3516) / VMI Vectorization (#3512) / SS buffer (#3514) / Partial L0 Copy (#3511) / UB to L1 Partial Copy (#3530) / PTO Ramp Values (#3535) / SIMT VF Access (#3523)

  • cumsum Shared Buffer Warp Specialization Fix (#3536, newly opened early 10-16): Under warp specialization, consumer threads are numbered starting from 128, but the shared memory scan template did not receive the thread range lower bound — CumSum1D / CumSum2D returned early on every consumer thread and the buffer remained unwritten; the fix passes the thread range minimum to the scan template (AllReduce already does this), with the HIP-side scan template modified in sync (LowerSharedScan is shared by both backends). Adds pipelined T.cumsum test cases for 1D / 2D shared buffers. Verification: 19 passed on H100 (the new pipelined cases fail 2 on main); the #3528 reproduction case is fully correct across 131072 items after the fix (129019 items wrong on main). Fixes #3528.
  • Seven PTO Family Advances: #3516 (PTO target tvm_ffi execution backend), #3512 (T.Parallel to PTO VMI vectorization), #3514 (SS buffer), #3511 (partial L0 copy explicit pitch), #3530 (UB to L1 partial copy for NZ buffers, newly opened), #3535 (PTO Ramp values emitted as vectors by type, newly opened), #3523 (vector local access fix within SIMT VF, newly opened).
  • Other In Review: TMA producer qualification (#3503), shared buffer double-expansion prevention (#2342), SM120 MXFP8 / MXFP4 block-scaled MMA (#3495) and the mxf8f6f4 full-operand family (#3099) continue to be updated; profiler L2 read-only flush (#3534) and shared scan thread count diagnostics (#3532) newly opened. Main repo open PRs total 165 (160 in the previous issue).

II. Multi-Backend Adaptation (Ascend / MetaX / Hygon / Moore Threads)

2.1 Hygon: Block-Scaled Async Copy Layout Opened and Merged Same Day (#21, landed in v0.1.12-release); distributed Branch Continues (10-15)

Date: 2026-10-15　Source: Block-Scaled Async Copy Layout (#21) / distributed (#19) / distributed branch

  • #21 Block-Scaled GEMM Async Copy Layout: opened 05:56, merged 06:58 (UTC), opened and merged into the v0.1.12-release line the same day — i.e., the 0.1.12 delivery line Hygon continues to maintain alongside the v0.1.15 mainline; the PR carries no description, with changes focused on the async copy layout for HCU block-scaled GEMM (continuing the block-scaled scale buffer layout work introduced in the 10-14 upgrade PR #20).
  • distributed Branch Continues: the branch head advanced twice within the window — the 10-15 08:14 batch (unified distributed process launcher, BF16 and all-peer IPC allreduce tests, propagation of IPC shutdown and initialization failures, IPC metadata validation, STRIDE remote block copy, etc.) and the 09:46 “refactor(hcu): move distributed language APIs”; #19 remains open (updated 09:53). Multi-card IPC collective communication remains Hygon’s main thrust for the next phase.
  • Hygon open PRs total 2 (flat).

2.2 Ascend: Four New PRs in the ascend Repo — dav-3510 gemm_v0 Silent Numerical Error Under Review (#1900); Open PRs 233 to 237 (10-15)

Date: 2026-10-15　Source: dav-3510 gemm_v0 (#1900) / KDA chunk_delta_bwd (#1895) / KDA chunk_delta_h_fwd (#1896) / bitwise_xor docs (#1899) / Ascend PR list

  • Window Overview: no code pushes in the ascend repo during the window; four new PRs opened, with open PRs rising from 233 to 237: KDA chunk_delta backward / forward migration (#1895 / #1896), bitwise_xor documentation fact-check rework (#1899), and dav-3510 gemm_v0 fix (#1900). For PTO routing landing on the main repo, see 1.1.
  • Focus Under Review #1900 (dav-3510 Silent Numerical Error): on dav-3510, tl::ascend::gemm_v0 returns wrong products for a well-defined set of tilings — no exceptions, no NaN / Inf, no zeros; the numerical distribution is nearly indistinguishable from correct results, manifesting only as precision failures on the remote end; size, shape, finiteness, and even multiset checks all pass. Two separable commits: ① --npu-arch now taken from the platform — LibraryGenerator previously passed dav-2201 unconditionally, so A5 kernels compiled this way silently targeted the wrong architecture (the same flash-attention kernel generates a 14656-byte, 2-symbol .aicore_binary under dav-2201 versus 18 to 19 symbols and roughly 24000 bytes under dav-3510; the ND2NZ structs and copy overloads in CANN headers that discriminate 3510 / 5102 by __NPU_ARCH__ therefore never took the A5 branch); ② gemm_v0 staging constraints — the actual numerical fix, reachable only once the former is in place. Measurement method: a single kernel (two copy_gm_to_l1 plus gemm_v0 plus copy_l0c_to_gm) compared directly on a single card.

2.3 MetaX and Moore Threads: No Pushes in Window; MLIR Ascend Knowledge Base Correction Merged (#202) (10-15)

Date: 2026-10-15　Source: MetaX repo / Moore Threads repo / Knowledge base correction (#202)

  • MetaX: no pushes in the window (last push was 10-13, when main caught up to the upstream v0.1.15 node); open PRs total 16 (flat).
  • Moore Threads: no activity since 09-30; open PRs total 6.
  • MLIR Ascend Knowledge Base Correction (#202): corrected the partial / merge description of ArgMax N-split in the autotuning knowledge base, unifying it to the implementation pattern of “completing partial, synchronization, and final merge within a single device launch”; updated the pattern library, cases, and reproduction scripts; added usage constraints for Expert mode and T.block_barrier; cleaned up report file formatting issues. Open PRs total 32 (flat).

III. Ecosystem and Adoption

3.1 TileOPs: Attention Triple Merge — varlen GQA sink, full-featured paged GQA, and paged KV write (10-15)

Date: 2026-10-15　Source: varlen GQA sink (#2537) / full-featured paged GQA (#2516) / PagedKVCacheWriteFwdOp (#2539) / MoEGroupedGemmFP8 docs (#71)

  • varlen GQA sink and pipelined sliding window (#2537): Adds optional FP32 per-head sinks for FP16 / BF16 / FP8 varlen GQA — a sink is an unscaled, untruncated logit that enters the softmax denominator; covers the varlen portion of the “attention sink” issue (#2269), while also folding in the pipelined sliding window.
  • Full-featured paged GQA (#2516): GQAPagedFwdOp gains read-only RoPE, two-sided sliding window, and optional per-head sinks, completing the paged path portion of the attention sink issue.
  • PagedKVCacheWriteFwdOp (#2539): New paged KV write operator — scatters K / V in place to caller-specified physical slots, skips -1 slots, and quantizes the FP8 cache with independent K / V scales; a single kernel handles both writes, with dynamic token count; preserves NaN, finite overflow, and infinity with native FP8 conversion saturation; the workload validates both written rows and untouched cache contents; accepted against FlashInfer and vLLM; exports PagedKVCacheWriteKernel from the attention package.
  • All three belong to the attention family; the previous window was already under review, and this window merged them together. Also: the docs site merged #71, adding API entries for PagedKVCacheWriteFwdOp and MoEGroupedGemmFP8FwdOp.

3.2 TileOPs: Three foundry performance PRs — W4A16 load reordering, sigmoid without IEEE division, SM89 scan widening (10-15)

Date: 2026-10-15　Source: W4A16 weight-first load (#2586) / sigmoid without IEEE division (#2588) / SM89 scan widening (#2574) / TileOPs PR list

  • W4A16 weight-first (#2586): GemmW4A16Kernel previously copied each K tile’s activations before the packed weights, and the warp-specialized producer issued in that order and waited stage by stage, so weights actually loaded from DRAM one K tile late; now weights go first (their stage is released immediately after the decode read). The 8-row decode tile replaces three operations with one shift (w4a16_dequant_word_one_shift masks the odd/even nibbles in place and centers with a single FMA, multiplying weights by 1/16). decode-long-k reaches 1.047x marlin-fp16 (previously 0.996x), the 8-row tile speeds up each row by 2.5% to 7.6%, and prefill-mlp-up is 5.7% faster (0.992x versus torch dequantized matmul, on par); no row is slower.
  • sigmoid without IEEE division (#2588): make_unary_regcopy supports evict_last loads — threads handling a full 16-byte vector use tileops::load16_evict_last, with the tail block guarded per vector; only SigmoidFwdKernel enables this path (the other 37 unary kernels generate identical CUDA, with 357 kernels compared per dtype). float16 sigmoid switches to refined_reciprocal (__fdividef reciprocal plus one Newton step, branchless), replacing the per-element range check and slow-path call; float16 / bfloat16 results are bit-identical to torch.sigmoid, and float32 keeps IEEE division. The forward input uses vector_aligned, fixing a misaligned address error when the starting element crosses a 16-byte boundary. 16M rows lead torch-compile by 1.020x to 1.042x; test nodes +2.
  • SM89 scan widening (#2574): The existing 16-column prefill scan is extended from 8 value heads to 16 value heads over the 4096 to 16384 token range (calls with ≤8 value heads keep the original strategy); it shares the same scan program and build identity, benefiting GDN and DeltaNet while leaving KDA unchanged. After a full A/B of the manifest, 19 affected workloads ultimately speed up by 2.5% to 19.7%.
  • TileOPs has 16 open PRs (17 last period); five newly opened: raster persistent tiles (#2589), GemmW4A8FwdOp (#2590, INT4 weights times FP8 activations), read-only paged GQA FP8 (#2591), SM89 long-prefill 32-column scan (#2592), and others.

3.3 TileFoundry: Three merges — instance slot refactor (#232), lowering contract (#233), and Qwen3.8-27B prefill example (#236) (10-15)

Date: 2026-10-15　Source: instance slot refactor (#232) / lowering contract (#233) / Qwen3.8-27B prefill example (#236) / analysis context (#238)

  • Instance slot refactor (#232, merged 03:02): Module child nodes become explicit shared instance slots — duplicate layers share a definition while retaining independent resources and instance identity (ownership copies would duplicate the definition, and inlining would lose instance identity, so both are abandoned). Retained calls are analyzed stepping through the callee, IR records are stored once per definition with call records equal to the callee summary; placement addresses are shared per SSA leaf, live ranges are cached per definition and translated at call sites, and reachable index weights are counted via ISL set union; check_program clones only once. The old inlining mechanism and Program are removed. Validation: full source suite 1674 passed, 11 skipped; installed version 161 passed.
  • Lowering and printer contract (#233, merged 05:12): Preserves author regions, storage definitions, update windows, tiled carry, staged ownership, and linear iteration indices; instruction admission is shared across ScheduleOp inference, candidate generation, lowering, and TIR validation; unifies logical layout and sharded window inference, and fixes MMA fragment declarations and physical register packing; SymbolRef.nested is defined as a child slot path relative to the caller’s Module, with validation and code generation sharing the same resolver.
  • Qwen3.8-27B prefill example (#236, merged 07:45): Adds prefill examples from 128 to 1024 tokens, deliberately crossing the roofline ridge — 128 tokens falls on the memory-bound side (51.4 GB of weights at 4.8 TB/s is about 10.71 ms), and from 256 tokens onward it is compute-bound, with the ridge at about 206 FLOP / byte; the SGLang baseline is measured empirically (fixed serving-path overhead exceeds the forward pass itself at short lengths); it is meant to answer whether multiple prompt lengths can share a single implementation.
  • 2 open PRs (3 last period); #238 (analysis evaluating definition facts per access context) is newly opened.

3.4 Nightly pipeline: No new snapshot seen in this window (10-15)

Date: 2026-10-15　Source: nightly snapshot branch / nightly workflow

  • As of this report’s generation, no new snapshot push for 10-15 has been seen in the window — the usual landing time is 19:38 to 21:15 UTC (03:38 to 05:15 Beijing time); the latest snapshot remains 35a25677 (10-14: 1105 correctness items across 65 suites, 1970 benchmark items across 53 suites, zero failures and zero errors).
  • The nightly workflow’s most recent completed run is in normal status; whether the snapshot was pushed late or the run failed needs to be rechecked next period.

IV. Community, Tutorials, and Events

4.1 PTO-ISA: tilelangGym SimtVF suite takes shape; SuperNPUBench group normalization single-pass reduction (10-15)

Date: 2026-10-15　Source: tilelangGym / SuperNPUBench / simt_compare branch

  • tilelangGym seven commits (06:47 to 07:59 within the window): A seed commit establishes an independent SimtVF standard test suite (SV / CF / SP plus PTO-DSL, with version pins and regression, #1); followed by script and layout cleanup, SV1 SIMD keynote and a single PASS table (#3), a remat vertex full PASS table with line-by-line Simt vs SIMD-DSL comparison (#4), linking the SIMD ~85% and Simt IPC / bubble / ILP analysis chain into ANALYSIS, pruning charts, and flagging Simt overhead as pending. Establishes a data bench for performance sensitivity analysis of PTO lowering.
  • SuperNPUBench (#245): perf(normalization): single-pass reduces and balanced gamma/beta for group_norm_grad — single-pass reduction and gamma / beta balancing for group normalization backward.
  • puzzles-ascend (simt_compare): per_token/04 splits the hybrid scheme into independent functions and folds them into demo materials (08:35).

4.2 Third-party community: six BM1690 board-level diagnostics; tilelang-cuda-skills’ first external audit of TileFoundry (10-15)

Date: 2026-10-15　Source: BM1690 pipelines / tilelang-cuda-skills / TileMC / tilelang-debugger

  • BM1690 pipelines repo (Sophgo TPU): Six board-level diagnostics within the window — bounded RoPE window diagnostics (preserving target strides), installed legacy SDK initialization and poll disassembly records, RoPE launch timeout and source scaling audit after reload, BM1690 driver reinitialization records, constrained recovery preparation, and board pre-check after releasing the holder. These are integration records from a personal experimental repo.
  • tilelang-cuda-skills: One commit — vendors TileFoundry as a submodule (pinning the main commit and cutlass commit), and publicly flags its compile() path as experimental: lists 4 emitter bugs (Cast emission, fill tensor suffix, tensor_view coordinates) and two runtime bugs (reduce-workspace finalization, warps_per_group dispatch), plus a missing host TMA tensor-map emitter; gives supported paths (HIR generation, check / analyze, schedule finalize, TileLang kernels), and recalibrates the skill suite to tilelang 0.1.15. This is the first external audit record of TileFoundry.
  • Silent items: TileMC (latest 10-14), easy-tilelang (10-13), tilelang-debugger (10-10), and SwHwCodesign (10-12) all had no pushes within the window.

4.3 Media and academia: zero new items from Google News / Hacker News / arXiv within the window (10-15)

Date: 2026-10-15　Source: Google News / Hacker News search / arXiv search

  • Zero new items across multiple Google News queries in both English and Chinese within the window — an English query hit a 10-14 commentary piece, which falls outside the window; Chinese queries returned zero hits. Hacker News had zero relevant entries (two Show HN items were fuzzy-match noise). arXiv had no new preprints (the latest relevant one remains TileSight from 07-24).

V. Trend Observations

5.1 PTO moves from “standalone target” to “first-class execution path”

  • #3316 lets the ascend target directly select the PTO execution backend, and together with #3474 from before the window (environment-variable target selection, CI dual-target parallelism) and the in-review #3512 / #3514 / #3516 / #3511, it turns PTO from a “standalone target with a separate pipeline” into a “composable execution path on the Ascend target.” In contrast, ascend repo #1900 reveals that silent numerical error class issues on dav-3510 (A5) are beginning to be systematically captured — with interface convergence on one end and verification entering deep water on the other, engineering on the Ascend side is advancing on both fronts simultaneously.

5.2 Attention family consolidation: long-context inference operator surface filled out

  • One window merged sinks (varlen and paged), bilateral sliding window, read-only RoPE, and paged KV writes, plus in-review read-only paged FP8 and 32-column scan — TileOPs’ paged / long-context attention matrix is being filled out, with FlashInfer, vLLM, and FLA external comparisons as acceptance criteria. The next observation point is the migration of same-family capabilities to Ascend (in-review Sparse MLA, KDA chunk series).

5.3 Hygon dual-line maintenance and distributed direction

  • Hygon simultaneously maintains v0.1.12-release (absorbing block-scaling patches) and the v0.1.15 mainline (upgrades merged and a release branch established), while advancing IPC collective communication on the distributed branch — the three-line structure of “old line for delivery, new line chasing upstream, new branch for distributed” is clear. If multi-card communication lands, Hygon will move from single-card adaptation into the multi-card system stage.

5.4 TileFoundry enters its external audit period

  • In the same window that the core refactor (instance slots #232, lowering contract #233) just landed, a third-party skills repo vendored TileFoundry into its workflow, listed emitter and runtime bugs, and delineated supported paths — the toolchain is beginning to undergo external auditing under the pressure of real use. A typical productization trajectory: after the chassis refactor comes interface contract convergence and public defect ledgers.

Appendix: Sources and Verification Notes

Source Verification Result
tile-ai organization (29 repos) 7 repos had pushes within the window: tilelang (3 merged, 10 opened), TileOPs (6 merged, 5 opened), TileFoundry (3 merged, 2 opened), tilelang-hygon (1 merged, 1 opened), tilelang-mlir-ascend (1 merged, 1 opened), tilelang.github.io (1 automated update), TileOPs.github.io (1 merged); organization-wide totals for the window: 15 merged, 24 opened, 172 in-review updates
Main repo tilelang 3 merged (#3316, #3417, #3517); 10 opened (#3518, #3520 to #3523, #3530, #3532, #3534 to #3536); 165 open PRs (160 in the previous issue); no new releases within the window (latest v0.1.15, 09-30)
TileOPs 6 merged (#2516, #2537, #2539, #2574, #2586, #2588); 5 opened (#2588 to #2592); 16 open PRs (17 in the previous issue)
Hygon / MetaX / Moore Threads Hygon: 1 merged (#21, landed in v0.1.12-release), distributed branch pushed twice within the window (#19 in review); 2 open PRs (flat). MetaX: no pushes within the window (last 10-13); 16 open PRs (flat). Moore Threads: no activity since 09-30; 6 open PRs
Ascend repos (ascend / mlir-ascend) ascend: no pushes within the window, 4 opened (#1895, #1896, #1899, #1900); 237 open PRs (233 in the previous issue). mlir-ascend: 1 merged (#202); 32 open PRs (flat)
TileFoundry 3 merged (#232, #233, #236); 2 opened (#236, #238); 2 open PRs (3 in the previous issue); no new releases (latest v0.0.2, 09-10)
TileOPs-nightly No new snapshot within the window (previous 35a25677, 10-14: 1105 correctness items / 1970 benchmark items, zero failures)
Adopters TileKernels and FlashQLA had no pushes within the window (last activity early 10-14, outside the window)
PTO-ISA and third-party community tilelangGym 7 (SimtVF suite taking shape); SuperNPUBench 1 (#245); puzzles-ascend simt_compare 1; BM1690 pipelines 6; tilelang-cuda-skills 1 (TileFoundry external audit); TileMC / easy-tilelang / tilelang-debugger / SwHwCodesign no pushes within the window
Google News / Hacker News / arXiv Google News zero new items within the window (one 10-14 commentary piece outside the window); HN zero relevant entries; arXiv no new preprints

Full Source List