Research window: 2026-10-14 07:00 ~ 2026-10-15 07:00 (Beijing time, 24 hours).

Sources: GitHub (full check of pushes across 29 repos in the tile-ai organization; 8 repos had pushes within the window: tilelang, TileOPs, TileFoundry, tilelang-ascend, tilelang-hygon, TileOPs-nightly, tilelang.github.io, TileOPs.github.io; 32 merges, 27 new opens within the organization window {of which 16 under review}, 40 under-review updates; main repo 10 merges, TileOPs 16 merges, Ascend repo 3 rollbacks, Hygon 1 merge; per-branch checks of non-default branches {distributed / feat/hcu-mqa-fp8 / coderabbit-auto-apply-labels / v0.1.15-release / simt_compare, etc.}; 1 new nightly pipeline snapshot, 1 deployment each for the two sub-sites) + release page checks + adopter repo checks (TileKernels v2.1.0 release, FlashQLA sm120 fix) + community repo checks (PTO-ISA SuperNPUBench / tilelangGym / tilelang fork / tilelang-puzzles-ascend, TileMC, BM1690 pipelines, easy-tilelang, SwHwCodesign, tilelang-debugger) + multiple Google News queries in Chinese and English (via proxy) + Hacker News + arXiv.

In This Issue

  • Today’s Highlights: Ten merges to the main repo, Hygon v0.1.15 landed, and TileKernels v2.1.0 released — overnight baseline +41 items (10-14)
  • I. Core Project Progress
    • 1.1 Main Repo: Four Ascend-side items wrapped up — standalone AIV execution (#3485), PTO DeepGEMM codegen (#3330), cross-warp allreduce fix (#3494), example target selection (#3474) (10-14)
    • 1.2 Main Repo: Three infrastructure items — CPU OpenMP parallel grid loops (#3109), C-family codegen shared emission (#3289), Windows NVCC switched to MSVC (#3510) (10-14)
    • 1.3 Main Repo: ROCm scan wavefront fix (#2326), test infrastructure caching (#3502), and governance configuration (#3513) (10-14)
    • 1.4 Main Repo Under Review: Four new PTO family items opened, TMA barrier and shared buffer fixes updated (10-14)
  • II. Multi-Backend Adaptation (Ascend / MetaX / Hygon / Moore Threads)
    • 2.1 Hygon: v0.1.15 upgrade merged (#20), release branch established, distributed IPC line opened (#19) (10-14)
    • 2.2 Ascend: Three fact-check rollbacks and reworks (#1888 to #1890, #1893); three new example and operator items opened (10-14)
    • 2.3 MetaX: No pushes in window; Moore Threads and Sunrise silent (10-14)
  • III. Ecosystem and Adopters
    • 3.1 TileOPs: Foundry performance batch of 11 items closed out — softmax / pooling / normalization / reduction all rolled out (10-14)
    • 3.2 TileOPs: Linear attention and MoE four items — KDA prefill inversion, GLA backward memory, expert search skip, permute bounds (10-14)
    • 3.3 TileOPs: D=256 decode extended to SM80 / SM90 (#2563); attention family and new GEMM batch under review (10-14)
    • 3.4 Adopters: Two items — TileKernels v2.1.0 released (#38) and FlashQLA sm120 fix (#48) (10-14)
    • 3.5 TileFoundry: Schedule CLI hardening merged (#231); module representation and lowering under review (10-14)
    • 3.6 Overnight Pipeline: New snapshot 35a25677 — 1105 correctness items (+41), 1970 benchmark items (+4), zero failures (early 10-15)
    • 3.7 Docs and Site: TileOPs site render timestamp moved forward (#70) and routine updates to two sub-sites (10-14)
  • IV. Community, Tutorials, and Events
    • 4.1 PTO-ISA: tilelangGym new repo established, SuperNPUBench archive batch and SIMT comparison advancing (10-14)
    • 4.2 Third-Party Community: TileMC target expansion, BM1690 board-level log batch; tutorials and debug repos silent (10-14)
    • 4.3 Media and Academia: Zero new items across Google News / Hacker News / arXiv in window (10-14)
  • V. Trend Observations
    • 5.1 All-backend v0.1.15 alignment nearing completion
    • 5.2 Main Repo’s “Infrastructure Day”: Compilation-side refactoring and platform rollout
    • 5.3 Overnight Baseline +41: Tests expanding in sync with merges
    • 5.4 Ascend Repo’s Rollback Discipline: Even low-priority cases are being guarded
  • Appendix: Sources and Verification Notes
  • Complete Source List

Today’s Highlights: Ten Merges in the Main Repo, Hygon v0.1.15 Landed, and TileKernels v2.1.0 Released — Nightly Baseline +41 (10-14)

Date: 2026-10-14　Sources: Independent AIV execution (#3485) / Hygon v0.1.15 upgrade (#20) / TileKernels v2.1.0 (#38) / Nightly snapshot 56c2ab6b / TileOPs PR list

Within the 24-hour window, the organization merged 32 PRs (10 in the main repo, 16 in TileOPs, 3 rollbacks in the Ascend repo, 1 in Hygon, 1 in TileFoundry, 1 in the docs site) and opened 27 new ones; 8 repositories had pushes. Three threads dominate this window: a wave of merges in the main repo, the landing of the Hygon backend upgrade, and the first version iteration by an adopter.

  • Ten merges in the main repo: covering Ascend (independent AIV execution #3485, PTO DeepGEMM codegen #3330, cross-warp allreduce fix #3494, example target selection #3474), CPU (OpenMP parallel grid loops #3109), codegen shared refactor (#3289), Windows MSVC (#3510), ROCm scan wavefront fix (#2326), test infrastructure (#3502), and governance configuration (#3513) — the highest single-window merge count in recent memory (see 1.1–1.3).
  • Hygon v0.1.15 upgrade merged (#20): the Hygon backend is fully upgraded to upstream v0.1.15, adding scale buffer layout planning for HCU block-scaled GEMM; a v0.1.15-release branch was also created, and #19 “Distributed” (+2577/-28, 44 files) opened an IPC allreduce distributed workstream (see 2.1).
  • Sixteen merges in TileOPs: the foundry performance batch of 11 PRs wrapped up (softmax / pooling / normalization / reduction rolled out across the board) plus four KDA / GLA / MoE fixes and D=256 decode extension (see 3.1–3.3).
  • TileKernels v2.1.0 released (#38): the first version iteration by the DeepSeek adopter repo since adding Ascend support on 09-30 — Ascend-side norm / SwiGLU / Engram rewrites and test updates (see 3.4).
  • Nightly baseline +41: new snapshot 35a25677 — 1105 correctness items (65 suites, +41), 1970 benchmark items (53 suites, +4), zero failures and zero errors (see 3.6).

I. Core Project Progress

1.1 Main Repo: Ascend Wraps Up Four Areas — Independent AIV Execution (#3485), PTO DeepGEMM Codegen (#3330), Cross-Warp Allreduce Fix (#3494), Example Target Selection (#3474) (10-14)

Date: 2026-10-14　Source: Independent AIV (#3485) / PTO codegen (#3330) / allreduce fix (#3494) / example target selection (#3474)

  • Independent AIV execution (#3485): Extends Ascend AutoSchedule so that AIV0 and AIV1 can execute different work under sid-dependent control flow — supporting alternating epilogues, dequantization/epilogue division of labor, disjoint input partitioning, and in-loop role switching. The implementation moves AssignCore ahead of latency estimation and scheduling, establishes independent identities for AIV-local UB buffers and scalar state, and models pipeline resources, special register dependencies, UB capacity, and synchronization flag banks per participating core; the unified-kernel collective path and one/two-AIV launch geometry are preserved. L0C→UB copies still execute on the AIC.
  • PTO DeepGEMM codegen (#3330): Tracks tl.ascend_set_mmad_direction across control flow and encodes the effective direction onto MAD instructions, rejecting MADs reachable under conflicting directions; supports SIMD post-increment loads (returning both data and an updated pointer), UB address-to-PTODSL pointer conversion in mixed AIC/AIV kernels, dynamic L0C→UB dimensions and strides, and int16 signed packed MX scale; improves code generation for conditional expressions and runtime loops. Reports 14 of 15 DeepGEMM PTO cases passing, with test_bf16_m_grouped_padding still blocked because the PTOAS VPTO backend cannot legalize FP32→BF16 conversion.
  • Cross-warp allreduce fix (#3494): When a cross-warp allreduce call covers multiple independent reduction groups, the ascend and pto targets incorrectly delivered the first group’s results to all groups; this fix addresses the correctness issue (follow-up to #3469).
  • Example target selection (#3474): Removes hardcoded target="ascend" from Ascend examples and tests, deferring instead to the TILELANG_DEFAULT_TARGET environment variable; the DeepGEMM JIT entry point supports execution_backend="auto"; CI runs the Ascend example suite once each with the ascend and pto targets, and documentation spells out how selection works.

1.2 Main Repo: Three Infrastructure Items — CPU OpenMP Parallel Grid Loops (#3109), C-Family Codegen Shared Emission (#3289), Windows NVCC Switches to MSVC (#3510) (10-14)

Date: 2026-10-14　Source: CPU OpenMP (#3109) / codegen sharing (#3289) / Windows MSVC (#3510)

  • CPU OpenMP parallelization (#3109): Adds optional OpenMP parallelization of grid loops for the CPU backend — introduces MaterializeCPUParallelGrid to convert annotated CPU grid loops into parallel loops, with loop collapse, thread count configuration, minimum trip count thresholds, and allocation sinking; adds OpenMP compile flags and pass configuration options for Linux / macOS / Windows; tests cover correctness, pragmas, allocation sinking, thresholds, and the single-dimension case. The CPU backend gains grid-level parallelism for the first time.
  • C-family codegen sharing (#3289): Introduces CodeGenTileLangCBase to unify CUDA, HIP, CPU C, Ascend C++, Metal, and C host code generation; fixes an issue where T.import_source, T.Kernel(prelude=...), and pragma_import_c swallowed the next generated line when the source text lacked a trailing newline or ended with a backslash; imported content is ordered as “headers → imports → generated declarations and functions” with two separating newlines guaranteed. Verification: 83 focused regression tests pass, 405 related codegen and launch suite tests pass.
  • Windows NVCC switches to MSVC (#3510): NVCC rejects the clang-cl selected by get_cplus_compiler() — instead selects cl.exe from the NVCC subprocess environment (without changing host C++ compiler selection), adds a VS 2026 18/* fallback path, and no longer passes -ccbin=None on non-Windows platforms; under CUDA 13.3 the reproduction case fails before the fix and compiles successfully after.

1.3 Main Repo: ROCm Scan Wavefront Fix (#2326), Test Infrastructure Caching (#3502), and Governance Configuration (#3513) (10-14)

Date: 2026-10-14　Source: ROCm scan (#2326) / test infrastructure (#3502) / CodeRabbit labels (#3513)

  • ROCm scan wavefront fix (#2326): HIP’s cumsum / cummax default to executing in 64-lane segments, producing incorrect results on Wave32 GPUs — the existing run entry point now selects segment width based on the target wavefront width (bounded by the block thread count limit), and 32-thread blocks exclude the 64-lane template at compile time; adds coverage for 32-thread forward/reverse scans and differing source/destination strides; the gfx950 MXFP4 example and tests switch to the {"kind": "hip", "mcpu": "gfx950"} target form. Verification: the CUDA scan suite passes 17 tests on B300, and 2 CuTeDSL source generation tests pass; AMD-side runtime verification is left to ROCm CI.
  • Test infrastructure caching (#3502): Caches call data from recently queried IR bodies for use by collect_calls / assert_call_count; replaces recursive visitors and generated-script text checks in transformation tests with structured IR assertions, and extends structural checks for software pipelining, scheduling, synchronization, barriers, and Hopper intrinsics.
  • Governance configuration (#3513): Enables CodeRabbit auto-labeling for PRs and issues (13 PR labels, 14 issue labels), retains all 11 review routing rules, and does not add, rename, or remove any labels.

1.4 Main Repo Under Review: Four New PTO-Family PRs, TMA Barrier and Shared Buffer Fix Updates (10-14)

Date: 2026-10-14　Source: PTO/tvm_ffi (#3516) / PTO VMI vectorization (#3512) / TMA barrier (#3503) / shared buffer double-expansion guard (#2342) / main repo PR list

  • Four new PTO-family PRs: tvm_ffi execution backend support for the PTO target (#3516), T.Parallel vectorization to PTO VMI (pipeline framework and elementwise support, #3512), SS buffer support (#3514), and explicit pitch for partial L0 copies (#3511).
  • TMA and pipelining: All-producer-thread arrival TMA forward barrier (#3503, updated), guard against double expansion of shared buffers across sibling pipelines (#2342), and recording only verified TMA descriptor names (#3484).
  • Other under-review updates: Test compile-time elimination (#3517), safe guard flattening for constant divisors (#3488), torch_npu task queue (#3324), SimdVF dim=1 reduction (#3437), manually scheduled FlashMLA example (#3464), Windows ARM64 CI (#2962). The main repo has 160 open PRs (161 in the previous issue).

II. Multi-Backend Adaptation (Ascend / MetaX / Hygon / Moore Threads)

2.1 Hygon: v0.1.15 upgrade merged (#20), release branch created, distributed IPC line opened (#19) (10-14)

Date: 2026-10-14　Source: v0.1.15 upgrade (#20) / Distributed (#19) / distributed branch / v0.1.15-release branch

  • v0.1.15 upgrade merged (#20): The codebase was upgraded in full to upstream TileLang v0.1.15, retaining HCU backend support and the existing build.sh workflow; adapted to the upgraded backend, lowering pipeline, language API, and test interfaces; added scale buffer layout planning for HCU block-scaled GEMM along with supporting LDS layout; README release info updated accordingly. After merging, the v0.1.15-release branch was created (same head as main) to archive the release line.
  • Distributed IPC line opened (#19): Opened “Distributed” at +2577/-28 across 44 files — the distributed branch contains a series of HCU IPC (inter-process communication) work: a unified distributed process launcher, IPC metadata initialization validation, BF16 / full peer-to-peer IPC allreduce tests, an IPC GEMM allreduce example, propagation of IPC shutdown and initialization failures, invalid peer guards, etc. Multi-card collective communication has become a new work direction for the Hygon backend.
  • Register pipeline (#18): Still under review (no new pushes since 10-13). Open PRs in the Hygon repo total 2 (1 in the previous issue). The feat/hcu-mqa-fp8 and feat/hcu-gemm-blockscaled-async-copy-layout branches saw no new pushes during the window.

2.2 Ascend: Three fact-check rollbacks and redo (#1888 to #1890, #1893); three new examples and operators opened (10-14)

Date: 2026-10-14　Source: Rollback #1888 / Rollback #1889 / Rollback #1890 / Redo (#1893) / Ascend PR list

  • Three rollbacks (#1888 / #1889 / #1890): The three “documentation fact-check” PRs merged in the previous window — round semantics (#1612), bitwise_rshift (#1676), bitwise_xor (#1681) — were rolled back one by one. The redo #1893 explains the cause: when the daily full suite ran low-priority cases, the exception regex for expected-failure cases did not match (what was actually thrown was an InternalError from AscendVectorInstructionSelection, not the asserted "Compilation Failed"); these cases were marked low_priority, and PR-stage CI (-m "not (low_priority or ci_skip)") does not execute them, so the issue was caught by the daily full run as a backstop after merging.
  • Redo (#1893): bitwise_rshift redone — per review feedback, all expected-failure cases were removed (dtypes outside the support table are now covered by the documentation dtype support table rather than expected-failure assertions), while the docstring rewrite and on-device tests were retained. The redos for round and bitwise_xor have not yet been submitted.
  • New examples and operators: situ_glu operator (#1891), cann-bench/lstm example (#1892), indexer_bwd operator and tests (#1887); updates under review: situ_glu_grad (#1877), sparse_mla_topk_reducesum (#1884), MHA example (#1879), Sparse MLA SeeSaw / Pipelined (#1869 / #1870). Open PRs in the Ascend repo total 233 (229 in the previous issue).

2.3 MetaX: No pushes during the window; Moore Threads and Sunrise silent (10-14)

Date: 2026-10-14　Source: MetaX repo / Moore Threads repo

  • MetaX: No pushes during the window (the last push was on the morning of 10-13, when main caught up to the upstream v0.1.15 node); the dev branch remains at 09-24. Open PRs total 16 (unchanged).
  • Moore Threads: No activity since 09-30; the Sunrise repo also saw no activity during the window. MLIR Ascend (tilelang-mlir-ascend) had zero pushes during the window (latest commit 10-10), with open PRs totaling 32 (unchanged).

III. Ecosystem and Adoption

3.1 TileOPs: Foundry performance batch closes out 11 PRs — softmax / pooling / normalization / reduction all rolled out (10-14)

Date: 2026-10-14　Source: softmax (#2570) / three pooling PRs (#2572 / #2573 / #2579) / three normalization PRs (#2576 / #2581 / #2585) / two reduction PRs (#2571 / #2578) / two GEMM and Elementwise PRs (#2582 / #2577)

  • softmax (#2570): Added 16-byte L2 evict-last load tileops::load16_evict_last; whole-vector rows (up to 64 elements per thread) now use register-resident _held_row, folding max and sum via warp shuffle; SoftmaxWarpRowsKernel covers rows up to 2KB, and both the register and shared-memory paths of SoftmaxOnChipKernel use the new load. 39 of 42 SoftmaxFwdOp rows lead the fastest baseline by 1.1% to 78.1%, with (32768, 65536) float32 matching quack; the two lm-head rows still trail (0.909x / 0.934x).
  • Three pooling PRs: #2572 MaxPool1dIndices — new load_evict_last scalar load, adjacent outputs stored as vectors, sincnet-local at 1.009x / 1.006x versus torch-compile and 1.049x faster than the older kernel (float32); #2573 AvgPool3d — windows with fixed divisor and taps ≤32 now read all taps in one pass (L1/L2 evict-last) and use select to exclude out-of-domain values, while non-power-of-two fixed divisors go through float32(float64(sum) * float64(1/divisor)) with no slow-path branch, producing bit-identical results to PyTorch; #2579 MaxPool3dIndices — float32 tile-aligned windows process two adjacent outputs per thread, with values/indices stored as vectors, cutting c3d-pool1 from 170.1 µs to 166.0 µs.
  • Three normalization PRs: #2576 RMSNorm — split into four bodies by row width (256 to 2048 elements use warp row splitting, above 4096 use whole-vector register residency, above 16384 use two passes, the rest use fragments), with both the jit builder and autotune selecting tuning spaces by body; #2581 InstanceNorm — whole-vector rows (up to 2048 elements) use one warp per row and 8 rows per block, with all 12 InstanceNormFwdOp rows matching or leading, and three wider-channel rows rising from 0.980x-0.988x to 1.042x-1.108x; #2585 follow-up — warp rows capped at 1024 columns, fewer rows per block for small batches (down to 1 row) to guarantee at least 128 blocks per grid, and three training paths switched to reciprocal division to align with torch mean.
  • Two reduction PRs: #2578 any/all — float16 / bfloat16 / float32 rows are read as 32-bit words and tested with bitwise ops (sign-bit mask, with -0.0 treated as 0 and NaN as non-zero), and warps of 16 or fewer are folded serially by lane 0; #2571 group tile counting — the GroupTiling prefix sum for varlen and grouped grids now uses intra-CTA inter-warp shuffle scan (keeping the loop for 8 groups or fewer), using 62 registers instead of 152 for 4096 groups at 32 threads, benefiting all GroupTiling callers (GQA / MLA / FP8 varlen, paged GQA, varlen key RoPE, grouped GEMM, GLA/GDN/KDA varlen).
  • GEMM and Elementwise: #2582 grouped GEMM — tile epilogue can alternate between two staging buffers (continuing to the next tile while stores are in flight), and the producer warp-group keeps only one warp issuing copies, with all four MoE workloads leading quack (fwd 1.015x, dgrad 1.012x, wgrad 1.033x; previously main was 0.936x-0.968x and 0.869x); #2577 SiluAndMul — both halves use load16_evict_last, and fixes an error when input is not 16-byte aligned (vector_aligned).

3.2 TileOPs: Four linear attention and MoE PRs — KDA prefill inversion, GLA backward memory, expert search skip, permute bounds (10-14)

Date: 2026-10-14　Source: KDA prefill (#2584) / GLA backward (#2569) / MoE search skip (#2575) / permute bounds (#2559)

  • KDA prefill inversion stabilization (#2584): KDA prefill failed under correlated keys — main failed on 6 chunk cases and 2 fused cases (including NaN); the fix solves in FP32 using 16-row diagonal blocks and reuses existing shared buffers for block products, keeps gated prefixes in FP32 registers, stores only reference rows in shared metadata, and removes mixed-dtype shared views that went out of bounds under TileLang 0.1.12; chunk and fused prefill share the inversion helper, with 4 regression cases added (two half-precision types × two paths × partial chunks). sm89 benchmarks (against the FLA 0.5.2 external baseline) pass FP64 comparison for both outputs and final state.
  • GLA backward memory reuse (#2569): On SM89, the shared memory request for FP32 chunk32/K64/V192 drops from 131072 to 98304 bytes, falling within SM89’s 101376 limit (reusing the state buffer after both dh consumers finish, adding a block barrier before loading h); an asymmetric FP32 regression was added. Note: this fixes a launch failure, but speed remains slower than FLA (0.0942 / 0.4164 ms versus FLA’s 0.0550 / 0.1494 ms at 256 / 2048 tokens), and the PR explicitly does not claim a speedup.
  • MoE expert search skip (#2575): Once the tight per-row MMA tile finds its owning expert, binary search over the remaining expert boundaries stops (the old logic still ran a lookup for every remaining expert); group sentinels are reused, tiles that miss still search all experts, and the physical prefix-sum / alignment / masked path behavior is unchanged. sm89 (RTX 6000 Ada) benchmarks cover the K512/N256 tight-row scenario.
  • permute-align bounds (#2559): Bounds and correctness fixes for the case where all 12 rows trailed vLLM’s moe_align_block_size — errors out instead of producing wrong results when threads is not a multiple of 32, empty routing calls return num_tokens_post_pad=0 for any expert count, out-of-range expert_ids are padded to values beyond the expert count, the verifier and docs align on the result set, and the expert loop gains bounds and per-block scatter range reservation.

3.3 TileOPs: D=256 decode extended to SM80 / SM90 (#2563); attention family and new GEMM batch under review (10-14)

Date: 2026-10-14　Source: D=256 decode (#2563) / attention under review (#2515 to #2541) / new GEMM batch (#2586 / #2587) / TileOPs PR list

  • D=256 decode extension (#2563): Extends D=256 FP16/BF16 dense decode from SM89 to SM80 / SM90 (reusing the 64-head × 64-key single-stage program and shared-memory split selection), adding B=1 / B=16 workloads for Gemma-2B 8K cache; it also fixes the dense RoPE split consumer ignoring softcap (the cap=2 regression previously failed), covering D=128 and the new D=256 path. Closes #2420.
  • Attention family under review: dense GQA attention sink (#2515), paged GQA RoPE / window / sink (#2516), paged KV cache gather (#2519), PagedKVCacheWriteFwdOp (#2539), LSE-weighted attention state merge (#2530), varlen GQA sink and pipelined sliding window (#2537), dense FP8 GQA long causal KV pipeline (#2541) — superAngGao’s batch attention family update.
  • New GEMM batch and tests: K-512 FP8 prefill 256-row wave tile (#2587), W4A16 weight preload and 8-row tile single-shift decode (#2586), MoE rounding budget acceptance (#2583), FlashInfer fused-MoE baseline per-activation autotuning (#2580). TileOPs has 17 open PRs (26 in the previous issue).

3.4 Two adopter PRs: TileKernels v2.1.0 release (#38) and FlashQLA sm120 fix (#48) (10-14)

Date: 2026-10-14　Source: TileKernels v2.1.0 (#38) / TileKernels repo / FlashQLA (#48)

  • TileKernels v2.1.0 (#38, 16 files, +352/-382): A release from the DeepSeek adopter repo (version commit 4d5ad0f5 “Release tile-kernels v2.1.0”). Changes center on the Ascend side: norm_forward_asc heavily rewritten (+166/-207), norm forward/backward kernels and tests updated, SwiGLU forward and backward modified on both asc / cuda sides, Engram gating forward/backward (asc + cuda) and tests aligned, and cast.py trimmed (+12/-36). README requirements are bumped to TileLang 0.1.15, PyTorch 2.13, Ascend 950 NPU, and CANN 9.2.0. Ascend support was added on 09-30 (one-to-one with the NVIDIA path, with runtime backend selection), and this is the repo’s first version iteration since moving to Ascend.
  • FlashQLA sm120 fix (#48, 5 files, +82/-5): Since 0.1.13 the Blackwell sm120 forward and backward paths were unusable — the root cause was block_DV mistakenly changed to 128 (the sm120 implementation requires 64) plus a missing aggregate_card_state; the fix restores block_DV=64, adds the aggregate_card_state handling, and updates sm120.csv. All tests pass on RTX 5090 (sm120) + tilelang 0.1.15 + CUDA 13.0; intra-node / cross-node context parallelism support is planned for follow-up exploration.

3.5 TileFoundry: schedule CLI hardening merged (#231); two module representation and lowering PRs under review (10-14)

Date: 2026-10-14　Source: schedule CLI (#231) / module instance slots (#232) / lowering contract (#233)

  • #231 merged: Unified instruction matcher (shared by type inference and candidates, covering execution grids, operand scopes, field matching, tile projection, and validation); added tf.empty and migrated schedule fixtures / tutorial sources and notebooks; fixed facts for dependent atoms, added schedule finalize --dim, shared attribute rendering, and non-finite constant round-tripping; computes may-access footprint using deterministic address unions and coordinate budget statistics. Validation: the frozen full source suite passes 1617 / skips 11. Addresses multi-section issues from #222 / #224 / #226 (some items moved to the lowering domain, as noted in the PR).
  • Two PRs under review: #232 represents module child nodes as shared instance slots; #233 preserves storage scopes and the printer contract. TileFoundry has 3 open PRs (1 in the previous issue).

3.6 Nightly pipeline: new snapshot 35a25677 — 1105 correctness items (+41), 1970 benchmark items (+4), zero failures (early 10-15)

Date: 2026-10-15　Source: nightly snapshot 56c2ab6b / snapshot metadata

  • New snapshot 35a25677 (run 38611488940, snapshot date 10-14, pushed 10-15 05:15 Beijing time): 1105 correctness items (65 suites, +41 versus the previous snapshot, 0 failures, 0 errors, 1 skipped), 1970 benchmark items (53 suites, +4, 0 failures); environment H200, CUDA 13.2, driver 595.71.05, image cu132-torch2.13-tl-0.1.12, with tileops 0.0.1.dev1330+g35a25677c in the snapshot (+16 dev number versus the previous snapshot), tilelang 0.1.12, torch 2.13.0+cu132.
  • The snapshot corresponds to TileOPs 35a25677, the merge point of #2576 (RMSNorm row splitting) — the +41 correctness gain is the largest single-day increase in the past week, coinciding with 16 merges in the window (most with added tests).

3.7 Docs and sites: TileOPs site render time moved earlier (#70) and routine updates to two subsites (10-14)

Date: 2026-10-14　Source: render time moved earlier (#70) / TileOPs docs site / main site

  • TileOPs site render moved earlier (#70): The daily refresh cron in render-benchmarks.yml moves from 0 22 * * * (22:00 UTC, 06:00 Beijing) to 30 20 * * * (20:30 UTC, 04:30 Beijing); the rationale is that nightly snapshots land between 19:38 and 20:18 UTC (over the past seven nights), so the new time queues at worst 12 minutes after them. One gh-pages deployment in the window (Deployed 8f46bef, MkDocs 1.6.1).
  • Routine main site updates: two automatic doc updates on tilelang.github.io (10-14 19:15 / 19:34 UTC). Releases page: main repo latest v0.1.15 (09-30), TileFoundry v0.0.2 (09-10), TileRT v0.1.5.post2 (08-06), with no additions in the window.

IV. Community, Tutorials, and Events

4.1 PTO-ISA: tilelangGym New Repo Established, SuperNPUBench Archive Batch and SIMT Comparison Advance (10-14)

Date: 2026-10-14　Source: tilelangGym / Archive PR (#242) / SuperNPUBench / simt_compare branch / PTO-ISA/tilelang fork

  • tilelangGym (new repo): Established by the PTO-ISA organization on 10-14, positioned as a testbed for “testing PTO lowering and performance sensitivity across different benchmarks / microbenchmarks” (first commit 10-14 06:21).
  • SuperNPUBench, 3 commits in window: rms_norm_dynamic_simt_32k archived into V2 (#242), group_norm_grad static kernel archived into V0 (#239), matmul added reuseB kernel (valid-tail handling, no PR).
  • tilelang-puzzles-ascend (SIMT comparison): simt_compare branch, 2 commits in window — T.reduce_max measured 8.94× faster than serial scan, 12 kernels switched to T.reduce_absmax folding and re-benchmarked.
  • PTO-ISA/tilelang fork: Tracking upstream main (synced to latest merge within window).

4.2 Third-Party Community: TileMC Target Expansion, BM1690 Board-Level Log Batch; Tutorials and Debug Repos Quiet (10-14)

Date: 2026-10-14　Source: TileMC / BM1690 pipelines / easy-tilelang / SwHwCodesign / tilelang-debugger

  • TileMC (third-party TileLang target for manycore architectures): 1 commit — extended FP32 support for the TileMC target, panel mapping, and workload scaling.
  • BM1690 pipeline repo (Sophgo TPU): 18 development-log-style commits in window — Matmul / RMSNorm board-level smoke tests and 1024 handover validation, Split-K board-level results, RoPE integration and timeout diagnosis, driver exit semantics and 7.0.0-34 kernel host build, etc. These are board-level debugging records from a personal experimental repo.
  • Quiet items: easy-tilelang tutorial repo has no pushes in window (last 10-13); SwHwCodesign public repos (AI-Compiler / AI-Infra) have no pushes (since 10-12); tilelang-debugger has no updates (since 10-10).

4.3 Media and Academia: Zero New Items in Window for Google News / Hacker News / arXiv (10-14)

Date: 2026-10-14　Source: Google News / Hacker News search / arXiv search

  • Google News: zero new items across multiple Chinese and English queries (TileLang operators / Ascend / tile-ai / exact terms) in window — the most recent wave of coverage stopped at 09-29 to 10-02 (DeepSeek×Ascend TileLang topic, already covered in previous issues); one general AI industry commentary piece matched query terms but contained no mention of TileLang or tile-ai in its body, removed as noise.
  • Hacker News: zero relevant entries in window (one Brainfuck compiler Show HN was a fuzzy-match noise item); arXiv: no new preprints (latest relevant remains the 07-24 TileSight analytical model paper).

V. Trend Observations

5.1 All-Backend v0.1.15 Alignment Nearing Completion

  • After upstream v0.1.15 (09-30) was released, MetaX caught main up to the v0.1.15 node on 10-13, and Hygon completed a full upgrade via #20 in this window and established a release branch — both backends aligned within two weeks of each other, with Hygon bringing block-scaled GEMM layout planning into the new baseline during the upgrade. Moore Threads remains stalled after 09-30, while Ascend is subsequently filling in API documentation item by item through “documentation fact-checking.” The multi-backend “same version, same semantics” foundation is converging.

5.2 The Main Repo’s “Infrastructure Day”: Compilation-Surface Refactoring and Platform Rollout

  • More than half of the 10 merges in a single window are compilation and platform infrastructure: C-family codegen sharing (unified base classes for CUDA / HIP / CPU / Ascend / Metal), CPU OpenMP grid parallelism, Windows MSVC toolchain, test infrastructure caching, ROCm scan wavefront — plus four new PTO/Ascend repos opened. During the release quiet period (15 days without a new version after v0.1.15), firepower is clearly directed at low-level extensibility and new platform support, which is mutually reinforcing with the rhythm of “MoE/performance merges → foundation growth → new version.”

5.3 Nightly Foundation +41: Tests Expand in Sync with Merges

  • The single-day +41 correctness items mark the largest increase in the past week, corresponding one-to-one with the 16 TileOPs merges (performance batches generally carry test-node additions, attention extensions carry new workload rows). The rolling accounting of “one merge, one foundation increment” continues to deposit verification of each change into nightly snapshots — static preparation before release continues to accumulate steadily.

5.4 Ascend Repo’s Rollback Discipline: Even Low-Priority Cases Are Guarded

  • The first three “documentation fact-checking” PRs were rolled back entirely due to abnormal regex mismatches in low-priority expected-failure cases, then redone in trimmed form — exposing a two-tier verification structure where “CI does not run low-priority cases at the PR stage, with the daily full suite as backstop.” This “rollback—redo” rather than “push forward with wounds” handling shows that CI governance in the Ascend adaptation repo is shifting from “all pass” to “precise assertions, unified criteria,” and also means that merge quality within the window is continuously constrained by daily full runs.

Appendix: Sources and Verification Notes

Source Verification Result
tile-ai org (29 repos) 8 repos had pushes in the window: tilelang (10 merged), TileOPs (16 merged), TileFoundry (1 merged, 2 opened), tilelang-ascend (3 reverted, 3 opened), tilelang-hygon (1 merged, 1 opened, 1 branch created), TileOPs-nightly (1 snapshot), tilelang.github.io (2 auto-updates), TileOPs.github.io (1 merged, 1 deployed); org total for the window: 32 merged, 27 opened (16 of them under review), 40 under-review updates
Main repo tilelang 10 merged (#3109, #3289, #3330, #3474, #3485, #3494, #3502, #3510, #2326, #3513); 160 open PRs (161 last period); no new releases in the window (latest v0.1.15, 09-30)
Ascend repos (ascend / mlir-ascend) ascend: 3 reverted (#1888 to #1890), 3 opened (#1891 to #1893); 233 open PRs (229 last period). mlir-ascend: zero pushes in the window (latest commit 10-10); 32 open PRs (flat)
Hygon / MetaX / Moore Threads Hygon: 1 merged (#20 upgrade to v0.1.15), v0.1.15-release branch created, distributed branch pushed (#19 under review); 2 open PRs (1 last period). MetaX: no pushes in the window (last 10-13); 16 open PRs (flat). Moore Threads: no activity since 09-30
TileOPs 16 merged (#2559, #2563, #2569, #2570 to #2573, #2575 to #2579, #2581, #2582, #2584, #2585); 17 open PRs (26 last period)
TileOPs-nightly New snapshot 35a25677 (run 38611488940, pushed 10-15 05:15): 1105 correctness items (65 suites, +41), 1970 benchmark items (53 suites, +4), zero failures and zero errors (1 skipped)
TileFoundry 1 merged (#231); 2 opened (#232, #233); 3 open PRs; no new releases (latest v0.0.2, 09-10)
Adopters TileKernels: 2 merged (v2.1.0 release PR #38 and version commit); FlashQLA: 2 merged (#48 sm120 fix); TileRT no activity
PTO-ISA org and third-party community tilelangGym new repo (first commit 10-14); SuperNPUBench 3 commits in the window; tilelang-puzzles-ascend simt_compare branch 2 commits; PTO-ISA/tilelang fork synced upstream; TileMC 1 commit; BM1690 pipelines 18 commits; easy-tilelang / SwHwCodesign / tilelang-debugger no pushes in the window
Google News / Hacker News / arXiv Google News zero new hits in the window (one generic AI commentary piece filtered as noise); HN zero relevant items; arXiv no new preprints

Full Source List