Research window: 2026-10-12 07:00 ~ 2026-10-13 07:00 (Beijing time, 24 hours).

Sources: GitHub (full review of pushes across 29 repos in the tile-ai organization; 9 repos had pushes within the window: tilelang, TileOPs, TileFoundry, tilelang-ascend, tilelang-hygon, tilelang-sunrise, TileOPs-nightly, tilelang.github.io, TileOPs.github.io; 20 merges, 41 new opens, and 59 in-review updates within the organization window; 7 merges in the main repo, 10 merges in TileOPs, TileFoundry #221 landed, Ascend NSA dual migration merged, Hygon three-branch progress, 1 new nightly pipeline snapshot, 3 builds of the main docs site), community repo review (PTO-ISA SuperNPUBench submission and release, tilelang-debugger, SwHwCodesign account), Google News RSS multi-query in Chinese and English (via proxy), Hacker News, arXiv, docs site and release page review.

In This Issue

  • Today’s Highlights: ROCm double merge and Ascend NSA major migration finalized — TileOPs lands 10 PRs in a single day, making SM89 its second platform (10-12 ~ 10-13)
  • I. Core Project Progress
    • 1.1 Main repo: ROCm double merge — DeepSeek NSA forward/decode and flash-decoding feasible tiles (10-13)
    • 1.2 Main repo: thread_storage_sync precise thread boundaries (#3291) and fix for #2954 (10-13)
    • 1.3 Main repo: Autotune structured experiment reports, CodeRabbit auto-assignment, and test specification docs (10-12 ~ 10-13)
    • 1.4 Main repo: Ascend PTODSL SIMT reduction helper vendoring (#3469) fixes CANN Weekly compilation (10-12)
    • 1.5 Main repo under review: SM120 MXFP8/MXFP4 block-scaled MMA, L2 prefetch, and Host IR double merge, etc. (10-12)
  • II. Multi-Backend Adaptation (Ascend / MetaX / Hygon / Moore Threads)
    • 2.1 Ascend: NSA Decode / NSA Bwd two major migrations merged — 48 layered tests (10-12)
    • 2.2 Ascend: cross-warp allreduce grouping fix opened (#3494) and copy/precision/cache fix batch (10-12)
    • 2.3 Hygon: FP8 branch advances (432 TFLOPS caliber), upstream v0.1.15 upgrade branch, and registration pipeline (10-12)
    • 2.4 MLIR Ascend two PRs under review; Sunrise only CI dependency upgrades; MetaX / Moore Threads silent (10-12)
  • III. Ecosystem and Adopters
    • 3.1 TileOPs: SM89 platform expansion batch — GQA prefill/decode, GDN / DeltaNet, and Norm (10-12)
    • 3.2 TileOPs: foundry performance batch — NSA persistent CTA, W4A16 GEMM, and 16-bit division (10-12)
    • 3.3 TileOPs: linear attention fixes — TMA hang avoidance and GLA prefill state skip (10-12)
    • 3.4 TileOPs under review: SM89 four-PR series, paged KV / attention cluster, and MoE two PRs (10-12)
    • 3.5 TileFoundry: parser op attributes and lexical layout sugar merged (#221); scaffold standalone project under review (#227) (10-12)
    • 3.6 Nightly pipeline: new snapshot — 1042 correctness items (+10), 1947 benchmark items (52 suites) zero failures (10-13)
    • 3.7 Adopters and docs: TileKernels / FlashQLA silent; main docs site 3 builds (10-12 ~ 10-13)
  • IV. Community, Tutorials, and Events
    • 4.1 PTO-ISA: SuperNPUBench four commits and two releases (ops-20261012 / ops-20261013) (10-12)
    • 4.2 Community accounts: SwHwCodesign six AI-* placeholder repos; TileLang-Awesome no longer accessible (10-12)
    • 4.3 Media and academia: Google News / HN / arXiv zero new items within window (10-12)
  • V. Trend Observations
    • 5.1 ROCm catch-up: two fixes with device budget awareness
    • 5.2 SM89 becomes second platform: 6 merges plus 4 under review in a single day
    • 5.3 Ascend migration line shifts to correctness wrap-up
    • 5.4 Baseline growth during release quiet period
  • Appendix: Sources and Verification Notes
  • Complete Source List

Today’s Highlights: ROCm Double Merge and Ascend NSA Major Migration Land — TileOPs Closes 10 PRs in a Single Day, Making SM89 a Second Platform (10-12 ~ 10-13)

Dates: 2026-10-12, 2026-10-13　Sources: ROCm NSA (#3152) / ROCm flash-decoding tiles (#3149) / Ascend NSA Decode (#1701) / Ascend NSA Bwd (#1730) / TileOPs PR list / nightly snapshot (6ec0d086)

Within the 24-hour window, the organization merged 20 PRs (7 in the main repo, 10 in TileOPs, 1 in TileFoundry, 2 in the Ascend adaptation repo) and opened 41 new ones; 9 repositories received pushes, with merges spanning the entire day and converging in the early hours of 10-13 (4 main-repo merges landed in the Beijing time early morning).

  • Main repo ROCm double merge lands: DeepSeek NSA forward/decode switches to 64-lane single-wave on the HIP side (#3152); the flash-decoding kernel automatically selects between 128x64 and 64x64 tiles based on device LDS/VGPR budgets (#3149) — respectively fixing “sub-wavefront block rejected” and “tile over budget fails to launch” on gfx942 (see 1.1).
  • Ascend NSA double migration merged: Decode (#1701) and backward (#1730) together add +2348 lines of examples, both implemented as Developer mode hybrid with 28 / 20 layered test suites attached (see 2.1).
  • TileOPs merges 10 PRs in a single day: SM89 picks up GQA prefill/decode, GDN / DeltaNet prefill, InstanceNorm, and Norm refactoring within one day; the foundry performance batch (NSA persistent CTA, W4A16, 16-bit division) advances the same day (see Chapter 3).
  • Hygon advances three branches: The new-feature branch FP8 MQA (commits claim channelwise GEMM reaches 432 TFLOPS), the upstream v0.1.15 upgrade branch merges adaptations, and registration pipeline #18 remains under review (see 2.3).
  • Nightly snapshot and docs site: 1042 correctness items (+10 vs. the previous snapshot), 1947 benchmark items (52 suites) with zero failures; 3 builds of the main docs site.

I. Core Project Progress

1.1 Main Repo: ROCm Double Feature — DeepSeek NSA Forward/Decode and flash-decoding Feasible Tiles (10-13)

Date: 2026-10-13 (merged in the early hours of Beijing time)　Source: ROCm NSA (#3152) / ROCm flash-decoding tiles (#3149)

  • DeepSeek NSA on ROCm (#3152, +111/-2): gfx942 has a wavefront size of 64, and TileLang rejects HIP blocks smaller than the wavefront, while the two NSA examples hardcoded 32 threads; this PR selects a single 64-lane wave for the forward and single-token decode kernels, preserves CUDA’s existing 32-thread launch configuration, and adds correctness coverage for causal forward and single-token decode on gfx942 (against the PyTorch NSA reference, FP16, 16 Q heads / 1 KV head, sequence 64).
  • flash-decoding tile adaptation (#3149, +82/-5): on gfx942, the 128x64 tile generation kernel requires 66048 bytes of dynamic LDS (exceeding the 65536 device limit) and hits the 256 VGPR ceiling, causing an “invalid argument” launch failure; this PR checks the generated HIP LDS and VGPR usage before launch and falls back to the existing 64x64 tile only when over budget (not hardcoded by device name), leaves the CUDA path unchanged, and adds a gfx942 runtime regression.

1.2 Main Repo: thread_storage_sync Exact Thread Bounds (#3291) and Fixes #2954 (10-13)

Date: 2026-10-13　Source: Exact thread bounds (#3291)

  • Computes exact thread bounds for thread_storage_sync (4 files, +292/-96); the author verified that this PR fixes #2954; adds a test case verifying that “equivalent partial-thread guards reduce to the same barrier,” along with a before/after compilation artifact comparison on SM89 (4060 Ti).

1.3 Main Repo: Autotune Structured Trial Reports, CodeRabbit Auto-Assign, and Testing Style Guide (10-12 ~ 10-13)

Date: 2026-10-12, 2026-10-13　Source: Trial reports (#3393) / CodeRabbit auto-assign (#3487) / Testing style guide (#3489)

  • Autotune trial reports (#3393, +98/-7): adds an experimental AutoTuner.run(on_trial=...) observer interface (corresponding to RFC #3375), emitting per-trial config index, JSON config, result, latency, validation label, and truncated error text; the callback runs on the aggregation thread, outside the shared cache lock; report/serialization errors only disable that report and do not affect tuning, and candidate generation, timeouts, and cache identity are unchanged. The author notes that “callback vs. fixed JSONL artifact” remains an open API decision.
  • Review guardrails (#3487, +1/-1): sets CodeRabbit’s reviews.auto_assign_reviewers to true so that it actually issues review requests (previously it only listed suggestions in the walkthrough); the 11 reviewer rules and their order remain unchanged.
  • Testing style guide (#3489, 8 files): adds a Testing Style Guide — when to rely on existing coverage, when to minimally extend it, and when to add focused coverage; renames tilelang-cpp-style to tilelang-dev-guide, converts the C++ rules into on-demand reference, and trims CONTRIBUTING with links.

1.4 Main Repo: Ascend PTODSL SIMT Reduction Helper Vendoring (#3469) Fixes CANN Weekly Compilation (10-12)

Date: 2026-10-12　Source: PTODSL reduction helper vendor (#3469)

  • PTOAS upstream removed ptodsl/_allreduce.py and expects TileLang to vendor it itself, but the main repo’s contrib/ptodsl/simt.py still references that module — compiling any PTO-targeted operator with the latest CANN Weekly (09-30) fails with ModuleNotFoundError; this PR vendors the helper as tilelang/contrib/ptodsl/allreduce.py (+555/-115), folds the integer-symbol compatibility from a monkey patch into the reduction table and dtype dispatch, and restores PTO target availability.

1.5 Main Repo Under Review: SM120 MXFP8/MXFP4 Block-Scaled MMA, L2 Prefetch, and Two Host IR PRs, etc. (10-12)

Date: 2026-10-12　Source: SM120 MX block-scaled MMA (#3495) / L2 prefetch (#3490) / Host IR direct JIT (#3481) / Host IR execution unification (#3473) / Windows ARM64 CI (#2962)

  • #3495 (+884/-51): T.gemm_blockscaled extends the block-scaled MMA family on SM120/SM121 from NVFP4 to MXFP8 (kind::mxf8f6f4, 1X, UE8M0) and MXFP4 (mxf4nvf4, 2X, UE8M0), with FP32 accumulation and one scale per 32 K elements; following the SM121 enablement merged on 10-10 (#3430), it continues to expand the hardware matrix.
  • #3490 (+87/-1): adds tl.prefetch_l2(addr, eviction_policy=...), supporting evict_normal / evict_last, requiring sm_80 or above; CUDA codegen emits the policy as a compile-time template parameter.
  • Two Host IR PRs (#3481 / #3473): direct Host IR JIT and caching, and unification of CUDA and CuTeDSL execution via Host IR, remain under review.
  • Other items under review: adding Windows ARM64 to CI (#2962), JIT parameter hashability validation (#3417), partial-wave scalar reduction (#3478), safe guard flattening for positive constant divisors (#3488), cast combination validation (#3350), TMA descriptor name validation (#3484), etc.

II. Multi-Backend Adaptation (Ascend / MetaX / Hygon / Moore Threads)

2.1 Ascend: Two Major Migrations Merged — NSA Decode / NSA Bwd — with 48 Layered Tests (10-12)

Date: 2026-10-12　Source: NSA Decode (#1701) / NSA Bwd (#1730)

  • #1701 (+755): example_tilelang_nsa_decode.py implements NSA Decode single-core decoding (seq_q=1) via Developer mode hybrid (four pass_configs: combineCV + auto_cv_sync + auto_sync + memory_planning), with explicit L1/L0C/UB allocation and 5-segment GM workspace auto-assigned through workspace_idx=[6..10]; the compiler automatically splits Cube/Vector scopes and inserts cross-core flag synchronization (no manual barrier/Scope/set_flag needed). 28 layered tests: L0 thresholds, L1 functionality (including DeepSeek-V3 typical config D=128, S=16, BS=64), L2 exceptions and boundary special values; measured on 910B3, fp16 (B=2, SEQ_LEN=64).
  • #1730 (+1593): example_tilelang_nsa_bwd.py provides two JIT kernels — nsa_fwd (online softmax + sparse K block selection, for end-to-end) and nsa_bwd_single (single-core backward: 5 GEMM + softmax + Delta + dS on-chip fusion); the backward pass follows the flashattn_bwd paradigm using on-chip direct T.copy (L0C→UB, UB→L1) to eliminate 9 GM workspaces, retaining two-level compensation GEMM (ds_delta / ds_delta2); 20 layered tests. The migration batches for both spanned the National Day holiday period, and this window saw them land on the adaptation repo’s default branch.

2.2 Ascend: Cross-Warp Allreduce Grouping Fix Opened (#3494) and a Batch of Copy/Precision/Cache Fixes (10-12)

Date: 2026-10-12　Source: cross-warp allreduce grouping (#3494) / example precision alignment (#1867) / situ_glu_grad example (#1877) / copy_ub_to_gm fix (#1795)

  • #3494 (main repo, +145/-26, under review): When a single cross-warp allreduce covers multiple independent reduction groups, the ascend and pto targets send the first group’s result to all groups — a correctness regression reported by the community after #3469 merged (with a minimal reproduction); the fix dispatches per group. The Ascend line’s “migrate a batch, audit a batch” cadence is evident.
  • Adaptation repo under review: example precision check alignment standard (#1867), situ_glu_grad operator example (#1877), fix for copy_ub_to_gm failing to express compact sub-32B rows causing corrupted keepdim reduction output (#1795); cache split into three (#1871 to #1873: JIT specialization key incorporating tuning parameters, autotune key aligned with effective profile parameters, NPU and simulator caches separated).
  • Main repo Ascend under-review cluster: SimdVF T.fill multi-buffering (#3455), SimtVF remat_idx / vector gather pack (#3492), SimdVF dim=1 reduction per-row single-element store (#3437), L0C fp32→f16/bf16 dual_copy in-flight cast (#3468 and #3328, two parallel PRs), independent AIV execution (#3485), T.PersistentKernel and AutoPersistent (#3325), hand-scheduled FlashMLA example (#3464), scalar sqrt outside VF scope (#3466), PTO codegen for DeepGEMM (#3330), example target selection (#3474), etc.

2.3 Hygon: FP8 Branch Advances (432 TFLOPS Figure), Upstream v0.1.15 Upgrade Branch, and Registration Pipeline (10-12)

Date: 2026-10-12　Source: register pipeline (#18) / feat/hcu-mqa-fp8 branch / upgrade/upstream-v0.1.15 branch

  • Register pipeline (#18): The registered branch gcy_merge_main (49 files, +4144/-318) received two pushes within the window and remains under review — adding a register pipeline (coordinated with the shared-memory pipeline) to the Hygon backend plus warp-diverge handling beyond 4 waves; the author claims example GEMM reaches performance parity with the reference library.
  • FP8 feature branch feat/hcu-mqa-fp8: The commit chain covers MLS channelwise FP8 GEMM — commits from 10-10 stating “reaches 432 TFLOPS,” with 10-12 adding “fp8 decode GEMM bandwidth surpasses hipblas at M≤32” and converging file and naming conventions (all author self-reported figures within the branch, no PR linkage yet).
  • Upgrade branch upgrade/upstream-v0.1.15: On 10-12, “Merge upstream v0.1.15 and adapt HCU backend” was merged, aligning the Hygon backend with main repo v0.1.15.
  • MetaX (last push 09-24) and Moore Threads (09-30) had no activity in this window.

2.4 Two MLIR Ascend PRs Under Review; Sunrise Only CI Dependency Upgrades; Remaining Backends Silent (10-12)

Date: 2026-10-12　Source: T.Pipelined parameterization (#199) / FloorDiv / FloorMod codegen (#200) / tilelang-sunrise

  • MLIR Ascend: T.Pipelined() support for num_stages / stage / order / group parameters under review (#199); TileLangIR FloorDiv / FloorMod codegen under review (#200).
  • Sunrise (TANG backend repo for Sunrise S2/S3): only two Dependabot CI dependency upgrades under review in the window (upload-artifact, download-artifact), no code-level activity.
  • All other organization-level repos (TileRT, tilescale, DeepStack, tilelang-puzzles, etc.) had no commits in the window.

III. Ecosystem and Adopters

3.1 TileOPs: SM89 platform expansion batch — GQA prefill/decode, GDN / DeltaNet, and Norm (10-12)

Date: 2026-10-12　Source: D256 GQA decode (#2529) / dense GQA prefill (#2528) / GDN / DeltaNet prefill (#2527) / InstanceNorm fix (#2526) / Norm config refactor (#2544)

  • D256 dense GQA decode (#2529): Opens 256-dim dense GQA decode on SM89 — reuses the 64×64, single-stage, 128-thread partition program; 16 candidate partitions occupy 98304 bytes (below the SM89 limit of 101376); excludes single-split candidates and keeps the two-split candidate for short KV; tests expanded to 61 nodes (+6), covering KV lengths 1 / 63 / 2048. Measured on RTX 6000 Ada.
  • dense GQA prefill (#2528, +260/-43): Adds FP16/BF16 and native FP8 prefill on SM89 (reusing the packed attention program, head dim 128); 14 cases fail on main and pass here (10 FP16/BF16 + 4 FP8); preserves rectangular masks, grouped heads, custom scale, softcap, RoPE, and FP8 dequantization; shares default config and memory accounting to avoid duplicate implementations.
  • GDN / DeltaNet prefill (#2527, 11 files): Reuses KDA’s chunk prepare and scan programs to implement SM89 prefill; 21 general prefill cases go from “failing, non-dispatchable” to passing; preserves raw-beta rounding, packed sequence boundaries, grouped heads, FP32 initial/final states, and GDN’s value-major state layout; the stable triangular solve is reused, and correlation-key cases do not relax tolerances.
  • Two Norm PRs: #2526 fixes InstanceNorm training compilation for 192×192 spatial inputs (six batch / precision combinations go from failing to passing, reusing GroupNorm’s width boundary and two-pass reduction); #2544 relocates the shared shift-reduction width constant (32768) into the norm config module (all 87 cases pass, no performance claims).

3.2 TileOPs: foundry performance batch — NSA persistent CTA, W4A16 GEMM, and 16-bit division (10-12)

Date: 2026-10-12　Source: NSA persistent CTA (#2531) / W4A16 GEMM (#2534) / 16-bit division (#2543)

  • NSA compressed persistent CTA (#2531, +391/-2): On SM90, NSACompressedVarlenFwdOp switches to the new kernel NSACompressedFwdVarlenTMAKernel — the old kernel used one 32-thread CTA per (token, KV head), reloading compressed K/V per token; the new kernel uses 512 persistent CTAs, each walking 64-row tiles (4 tokens × 16 heads), with queries fed through a double-stage TMA ring, requested K/V blocks resident in shared memory, QK via n=16 SS WGMMA and PV via n=64 RS WGMMA, and O written out via TMA together with log-sum-exp after QK reads complete; four 48KB CTAs reside per SM.
  • W4A16 GEMM (#2534, +24/-0): _legal_configs constrains the K tile to not exceed K and the ring depth to not exceed the number of K tiles, so K<512 no longer pads with zeros; single-tile (K=128) and multi-tile (K=256) rows switch to 8x64 tiles with 128/256-wide K tiles (two stages), leading torch dequantized matmul; the other 13 rows keep their configs unchanged, and 3 rows still lag (limitations self-listed by the author).
  • 16-bit division (#2543, 9 files): Reciprocal and bf16 sigmoid switch from IEEE float32 division to __fdividef fast division (range-scaled version for bf16); at 16M rows, fp16/bf16 latency is 17.86 / 17.79 microseconds, 1.02x the previous version and 0.991x / 0.995x of torch-compile.

3.3 TileOPs: linear attention fixes — TMA hang avoidance and GLA prefill state skip (10-12)

Date: 2026-10-12　Source: single-tile decode state load (#2538) / GLA prefill state skip (#2540)

  • #2538 (+66/-6): On SM90, the GLA / DeltaNet recurrent decode program with k_tile == dim_k hangs on first launch — TileLang 0.1.12 downgrades the single-step state copy to a 1D bulk copy, whose producer never reaches the barrier under warp specialization; after the four builders switch to non-TMA loads, any k_tile that evenly divides dim_k can run, and k_tile < dim_k behavior is unchanged; a FIXME is left in the code to reclaim the workaround once TileOPs pins TileLang 0.1.13+.
  • #2540 (+77/-67): The four GLAFwdOp prefill implementations are specialized on has_initial_state — when there is no initial state, the local recurrent tile is cleared and an unread scalar placeholder is used, eliminating allocation, zeroing, and reading of the entire FP32 initial-state tensor; the device source built with state is byte-for-byte identical to main, and the public interface and dispatch domain are unchanged (closes #2380).

3.4 TileOPs under review: SM89 quartet, paged KV / attention cluster, and two MoE PRs (10-12)

Date: 2026-10-12　Source: SM89 quartet (#2546 to #2549) / varlen sinks and sliding window (#2537) / PagedKVCacheWrite (#2539) / masked FP8 grouped GEMM (#2521) / DeepSeek grouped top-k (#2535)

  • SM89 quartet (#2546 to #2549): GLA backward state lifetime, DeltaNet backward shared-memory adaptation, KDA fused prefill, MoE compact row-wise grouped GEMM — SM89 coverage extends from merged PRs to those under review.
  • Paged KV / attention cluster (six PRs): varlen GQA head sinks and pipelined sliding window (#2537 — window rows are 1.03 to 1.13x faster than the current best baseline, sink mixing is 1.51 to 1.53x faster than FlashInfer, though partial RoPE and two FP8 rows remain below reference); PagedKVCacheWriteFwdOp (#2539, in-place scatter by caller slot, independent FP8 K/V scales with saturating rounding, with a vLLM benchmark adapter); paged GQA with RoPE/window/sinks (#2516), paged KV gather (#2519), LSE-weighted attention state merge (#2530), dense FP8 GQA pipeline for long causal KV (#2541).
  • Two MoE PRs: masked FP8 grouped GEMM (#2521, aligns with deep_gemm masked semantics, corrects the MoE roofline formula’s traffic overestimate caused by moving the entire tile, 14 workload rows); DeepSeek grouped top-k routing (#2535, aligns num_expert_group / topk_group / routed_scaling_factor with vLLM grouped_topk, and fixes the scheduling issue where only 32 / 132 SMs are occupied at T=512).
  • GEMM performance batch (four PRs): FP8 tile reordering and 1x128 B scale wave kernel (#2533), filling SMs for short tight groups (#2536), module constant scope consolidation (#2542), W4A16 scoring with K slicing (#2545) remain under review.

3.5 TileFoundry: parser op attributes and lexical layout sugar merged (#221); scaffold standalone project under review (#227) (10-12)

Date: 2026-10-12　Source: parser attributes and layout sugar (#221) / scaffold standalone project (#227)

  • Merged #221 (222 files, +4473/-4951): Establishes a unified authoring surface for op attributes and layouts — parses schema-based op attributes, layout composition, and explicit value states, migrates fixtures and tutorials, and regenerates printer goldens; mesh selection is now built via composition and supports specialize(mesh=...); parser grammar/rules are generated from executable schemas with pre-commit validation; after rebasing onto the buffer-alias changes, aligns Reshard aliases and region memory records.
  • Under review #227 (47 files): Adds tilefoundry scaffold SOURCE OUT_DIR — generates an editable standalone CMake project per Target codegen (parameter views, specialization dispatch, launcher, host registration, and placeholder CUDA bodies), letting authors take over the kernel body without breaking the calling convention; codegen artifacts and linking are split into six module files, with LinkedModule.functions replacing the single entry.

3.6 Nightly pipeline: new snapshot — 1042 correctness items (+10), 1947 benchmark items (52 suites) with zero failures (10-13)

Date: 2026-10-13　Source: nightly snapshot (6ec0d086) / snapshot run metadata

  • New snapshot 6ec0d086 (run 38288018755, 10-13 03:53): 1042 correctness items (61 suites, +10 vs. the previous snapshot, 0 failures, 0 errors, 1 skipped), 1947 benchmark items (52 suites, 0 failures); environment H200, CUDA 13.2, driver 595.71.05, with tileops 0.0.1.dev1296+g6ec0d086d and tilelang 0.1.12 in the snapshot.
  • The correctness increment lands in step with the SM89 series merged within the window, as the evaluation baseline continues its rolling rhythm of “one merge, one notch up.”

3.7 Adopters and docs: TileKernels / FlashQLA quiet; main docs site built 3 times (10-12 to 10-13)

Date: 2026-10-12, 2026-10-13　Source: main docs site / TileKernels / FlashQLA

  • Adopters: TileKernels (DeepSeek) and FlashQLA (Qwen) had no pushes within the window (both quiet since 09-30); no in-window activity for TileRT.
  • Docs sites: 3 builds for the main site (two on 10-12, one in the early hours of 10-13); 1 gh-pages deployment for the TileOPs site (morning of 10-12).

IV. Community, Tutorials, and Events

4.1 PTO-ISA: Four Commits and Two Releases for SuperNPUBench (ops-20261012 / ops-20261013) (10-12)

Date: 2026-10-12　Source: SuperNPUBench / ops-20261013 release

  • Four commits in the window: rms_norm decomposes the R=8192 reduction into 16 KiB tiles (#223), a lockstep-safety fix for gfsim RES_CHECK file IO, simplification of matmul_test to 4-PE (Local-A / Shared-B, #222), and merge of #225.
  • Two ops releases: ops-20261012 and ops-20261013 — the latter based on main 4c66c2ab, split into 2 small packages by suite, containing all compiled ELF artifacts (no gfrun gate); the release notes explicitly state that “the four toolchain items are unchanged, and all output differences from the previous version come from code.”

4.2 Community Accounts: Six AI-* Placeholder Repos Under SwHwCodesign; TileLang-Awesome No Longer Accessible (10-12)

Date: 2026-10-12　Source: SwHwCodesign account / original TileLang-Awesome link

  • The third-party curation repo TileLang-Awesome that appeared on 10-11 (covered in the previous reporting period) is now inaccessible (404, and no new repo with the same name appears in search); the same account created 6 placeholder repositories on the evening of 10-12 (AI-Chip / AI-Compiler / AI-Infra / AI-Instruction / AI-Kernel / AI-Model, all initial commits) — third-party resource building has yet to take shape.
  • tilelang-debugger (superAngGao) had no updates in the window (most recent commit 10-10); no other new third-party tool repos were found.

4.3 Media and Academia: Zero New Additions Across Google News / HN / arXiv in the Window (10-12)

Date: 2026-10-12　Source: Google News / Hacker News search / arXiv search

  • Multiple Chinese and English query sets returned zero new hits in the window: the 10-11 tech-insider aggregation piece and the 10-10 / 10-11 Zhiwei in-depth analyses were both covered in the previous issue, with no follow-up pieces in this window.
  • Hacker News: zero entries over 96 hours; arXiv: no new preprints (the most recent relevant item remains the 07-24 TileSight analytical model paper).

V. Trend Observations

5.1 ROCm Catch-Up: Two Fixes Driven by Device-Budget Awareness

  • The two ROCm changes in this window point to the same theme — “adapting to device reality”: the 64-lane wavefront on gfx942 (#3152) and the LDS/VGPR budget (#3149). Both are fixed on the use-case side (examples) without touching in-kernel generation strategy, indicating that ROCm support is still in the “get it running and add regressions” stage; combined with the main repo’s recent multi-generation concurrent fixes for SM121 and SM89, TileLang’s backend topology is shifting from “NVIDIA-first” to “maintaining multiple devices simultaneously.”

5.2 SM89 Becomes a Second Platform: 6 Merges Plus 4 Under Review in a Single Day

  • TileOPs saw 6 SM89 merges in one day (attention prefill/decode, linear attention, full Norm coverage) plus 4 SM89 PRs under review; RTX 40-series and L40 / 6000 Ada-class workstations have become routine targets alongside Hopper on the operator library side. Evaluation-side synchronization (nightly baseline +10 items) means SM89 correctness coverage is moving from “it compiles” to “it has regressions.”

5.3 The Ascend Migration Line Enters Correctness Wrap-Up

  • Two major NSA migrations merged (forward/backward, 48 layered tests combined), followed by cache three-way splitting and a cross-warp allreduce grouping fix — the focus of the Ascend line has shifted from “example and operator porting” to a wrap-up audit of “correctness, cache semantics, and compilation usability”; a community-contributed correctness fix (#3494) appeared immediately after the #3469 fix, indicating the collaboration loop is functioning normally.

5.4 Baseline Growth During the Release Quiet Period

  • The main repo has had no new release since v0.1.15 on 09-30; the organization shows 507 open PRs (498 in the previous period), with 41 newly opened and 20 merged in a single window — the structure of “tighter merge gates, thicker review queue” continues. TileOPs’ SM89 expansion and the nightly baseline +10 indicate that although official releases are quiet, “static preparation” on both the merge and evaluation fronts continues to accumulate, and the judgment that a release window is approaching remains unchanged.

Appendix: Sources and Verification Notes

Source Verification Result
tile-ai org (29 repos) 9 repos had pushes in the window: tilelang (7 merged, 29 open-PR updates), TileOPs (10 merged, 16 open-PR updates), TileFoundry (1 merged, 1 open), tilelang-ascend (2 merged, 7 open-PR updates), tilelang-hygon (pushes to three branches, #18 updated), tilelang-sunrise (2 CI dependency PRs open), TileOPs-nightly (1 snapshot), tilelang.github.io (3 builds), TileOPs.github.io (1 deployment); org totals for the window: 20 merged, 41 newly opened, 59 open-PR updates; 507 open PRs total (498 last issue)
Main repo tilelang 7 merged (#3152, #3149, #3291, #3489, #3487, #3393, #3469); 29 open-PR updates; 168 open PRs (170 last issue); no new releases or tags in the window (latest v0.1.15, 09-30)
Ascend repos (ascend / mlir-ascend) ascend: 2 merged (#1701, #1730); 7 open-PR updates; 228 open PRs (230 last issue). mlir-ascend: #199, #200 open-PR updates
Hygon / MetaX / Moore Threads Hygon: pushes to three branches (gcy_merge_main, feat/hcu-mqa-fp8, upgrade/upstream-v0.1.15); #18 open. MetaX (last push 09-24) and Moore Threads (09-30) had no activity
Sunrise Only two Dependabot CI dependency upgrades (#7, #8) open in the window; 3 open PRs total
TileOPs 10 merged (#2526 through #2529, #2531, #2534, #2538, #2540, #2543, #2544); 16 open-PR updates; 19 open PRs
TileOPs-nightly One new snapshot 6ec0d086 (10-13 03:53): 1042 correctness items (61 suites, +10), 1947 benchmark items (52 suites), zero failures and zero errors
TileFoundry 1 merged (#221); 1 open (#227); 2 open PRs
Adopters and community TileKernels and FlashQLA had no pushes in the window (both 09-30); TileRT had no activity in the window; tilelang-debugger has no updates (after 10-10); SwHwCodesign has six AI-* placeholder repos (10-12); TileLang-Awesome is no longer accessible (404)
PTO-ISA org SuperNPUBench had 4 commits and 2 releases in the window (ops-20261012 / ops-20261013); tilelang-puzzles-ascend has no updates
Google News / Hacker News / arXiv Google News had zero new hits in the window; HN had zero items over 96 hours; arXiv had no new preprints

Full Source List