Research window: 2026-10-10 07:00 ~ 2026-10-12 07:00 (Beijing time, 48 hours; Monday morning report, window starts from the cutoff of the previous daily report (10-10 make-up report for the adjusted holiday), covering all of Saturday and Sunday plus early Monday morning).

Sources: GitHub (full review of pushes across 29 repositories in the tile-ai organization; 8 repositories had pushes within the window: tilelang, TileOPs, TileFoundry, TileOPs-nightly, tilelang-hygon, tilelang-mlir-ascend, tilelang.github.io, TileOPs.github.io; 34 merges and 42 new opens within the organization window; 9 merges and 9 new opens in the main repo, 21 merges in TileOPs, 2 in TileFoundry, per-repo review of the Ascend / Hygon / MLIR adaptation repos, 3 new snapshots from the nightly pipeline, 2 builds of the documentation site), community repository review (tilelang-debugger, TileLang-Awesome, PTO-ISA teaching and benchmark repos), Google News RSS multi-query searches in Chinese and English (via proxy), Hacker News, arXiv, documentation site and release page review.

Issue Index

  • Today’s Highlights: Full-scale weekend push — 21 TileOPs merges (Op base class refactor finalized, MLA decode speedup batch), main repo SM121 landed, TileFoundry sparse decode threaded through TIR (10-10 ~ 10-12)
  • I. Core Project Progress
    • 1.1 Main repo: SM121 (DGX Spark) lights up block-scaled MMA; CuTeDSL fence election and parameter identity fixes (10-10 ~ 10-11)
    • 1.2 Main repo: GEMM dtype whitelist finalized — unsupported combinations rejected before CUDA codegen (10-12)
    • 1.3 Main repo: For step size, JIT output indexing, popcount, bit reduction, and test infrastructure — five items landed (10-10 ~ 10-11)
    • 1.4 Main repo new items: Host IR JIT two items plus parallel compilation, partial wave reduction, and nine others (10-10 ~ 10-11)
    • 1.5 TileFoundry: Sparse decode threaded through TIR (#223) and mesh scope fix (#220) (10-10 ~ 10-12)
  • II. Multi-Backend Adaptation (Ascend / MetaX / Hygon / Moore Threads)
    • 2.1 Ascend: Sparse MLA migration opens SeeSaw and Pipelined items; long-running migration batch updated in bulk (10-10 ~ 10-11)
    • 2.2 Ascend: Cache fixes x4 — JIT specialization keys, autotune keys, NPU and simulator cache separation (10-10)
    • 2.3 Ascend: Full MLIR path performance report merged — 7 operators, 112 cases all passing; NPU profiling support under review (10-10)
    • 2.4 Ascend: Main repo PTO / CANN review cluster — reduction helper vendor, documentation requirements, and example target selection (10-10 ~ 10-11)
    • 2.5 Hygon: Register pipeline update; MetaX / Moore Threads silent (10-10 check)
  • III. Ecosystem and Adopters
    • 3.1 TileOPs: 21 merges — one-shot Op base class refactor finalized (-5200 lines) (10-10 ~ 10-11)
    • 3.2 TileOPs: MLA / KDA / NSA performance batch — SM89 decode speedup up to ~4.6x, top-k bit sorting and WGMMA descriptor unification (10-10 ~ 10-11)
    • 3.3 TileOPs: attention sinks x5 and masked FP8 GEMM newly opened (10-10)
    • 3.4 TileOPs: DSA / paged GQA fix batch — shared memory race and stale row exclusion (10-10)
    • 3.5 Nightly pipeline: Three new snapshots — 1032 correctness items, 1947 benchmark items (52 suites) zero failures (10-10 ~ 10-12)
    • 3.6 Docs and adopters: Op base class guide published alongside refactor; two main docs site builds; TileKernels / FlashQLA silent (10-10 ~ 10-11)
  • IV. Community, Tutorials, and Events
    • 4.1 tilelang-debugger: Offline HTML debug report launched, validated on 0.1.12 / 0.1.15 dual versions (10-10)
    • 4.2 PTO-ISA: SuperNPUBench eight items advanced — mega-moe and tail_ocp_fp8 specials (10-10 ~ 10-11)
    • 4.3 Community: TileLang-Awesome new repo established (10-11)
    • 4.4 Media and academia: Chinese in-depth analysis article published; overseas aggregation continues; no new HN or arXiv items (10-10 ~ 10-11)
  • V. Trend Observations
    • 5.1 Full weekend: 34 merges executed across Saturday, Sunday, and early Monday
    • 5.2 Refactor finalized and version silence: release window in sight
    • 5.3 Hardware coverage expands in the same week: SM121 lit up, SM89 performance policy batched
  • Appendix: Sources and Verification Notes
  • Full Source List

Today’s Highlights: Full-Steam Weekend Push — TileOPs Closes Out 21 Merges, Main Repo Lands SM121, TileFoundry Connects the Sparse Pipeline End to End (10-10 ~ 10-12)

Date: 2026-10-10 ~ 2026-10-12　Sources: TileOPs PR list / Op base class refactor (#2520) / SM121 block-scaled MMA (#3430) / Sparse decode through to TIR (#223) / Nightly snapshot (fc2a2a91)

Within the 48-hour window, the org merged 34 PRs (main repo 9, TileOPs 21, TileFoundry 2, MLIR path 1, docs 1) and opened 42; 8 repos saw pushes, with activity running through all of Saturday, Sunday, and early Monday — merges split 23 on Saturday, 9 on Sunday, and 2 in the early hours of Monday, a notably higher weekend merge volume than the previous window (Friday)’s 21.

  • TileOPs merges 21 PRs in a single weekend: the Op base class “one policy per role” mega-refactor (#2520, 363 files, net ~1,865 lines removed) was finalized ahead of release; the MLA, KDA, and NSA performance tracks all converged simultaneously, with new PRs opened for the five-part attention sinks series and masked FP8 GEMM (see Chapter 3).
  • The main repo’s 9 merges focus on platform expansion and fixes: SM121 (GB10 / DGX Spark) block-scaled MMA lit up (#3430), the GEMM dtype whitelist wrapped up (#3245, merged in the early hours of 10-12), CuTeDSL fence election and NVRTC / CuTeDSL parameter identity fixes (#3400 / #3414), plus a batch of fixes for For step sizes and JIT output indexing (see Chapter 1).
  • TileFoundry pushes sparse decoding all the way to TIR: #223 (84 files, +4424/-1543) fixes lost loop work, excessive lookup billing, and incorrect staged updates in DSA decoding, landing subscript-style async collection, Bitcast, and Where (see 1.5).
  • The nightly pipeline produced three consecutive snapshots (latest merge point #2525): 1,032 correctness items and 1,947 benchmark items (52 suites), with zero failures and zero errors; up 2 items each versus the previous snapshot, and three snapshots in two days with no gaps.
  • Media coverage: a Chinese in-depth piece centered on TileLang as its narrative core appeared (Zhiwei, 10-10 Fengwen / 10-11 Zhihu), while overseas aggregators continued the wave of coverage (see 4.4).

I. Core Project Progress

1.1 Main Repo: SM121 (DGX Spark) Lights Up Block-Scaled MMA; CuTeDSL Fence Election and Parameter Identity Fixes (10-10 ~ 10-11)

Dates: 2026-10-10, 2026-10-11　Sources: SM121 block-scaled MMA (#3430) / CuTeDSL fence election (#3400) / NVRTC / CuTeDSL parameter identity (#3414)

  • SM121 lights up (#3430, merged 10-11 00:32): SM121 (GB10, DGX Spark) actually supports SM120-class warp block-scaled MMA, but the SM120 helper only checked the CUTLASS SM120A macro guard (defined only when the device arch is 12.0), so on sm_121a every block-scaled MMA compiled to BPT.TRAP instead of OMMA.SF; this PR accepts both SM120 / SM121 targets by arch and family, gates NVF4 tests by the SM12x family, and allows sm_121 / sm_121a in the CuTeDSL TMA architecture table. The author verified it on a DGX Spark (driver 580.178.04, CUDA 13.0).
  • Fence election (#3400, merged 10-10 10:47): sync_grid() previously elected all threads with tid.x == 0, so under 2D / 3D thread blocks multiple threads repeatedly published the same block arrival and the fence could release early; it now elects only the physical thread (0, 0, 0), with the counter / generation protocol and cooperative launch unchanged. Regression covers 1D / 2D / 3D grids and repeated reuse (RTX 5090, CuTeDSL 4.7.0).
  • Parameter identity (#3414, merged 10-10 13:58): NVRTC and CuTeDSL host wrappers previously generated signatures from raw Var names and matched parameters by printed name, so duplicate names (stream, device_id, etc.) and device-side renames caused crosstalk; they now assign wrapper parameter names by Var identity while preserving positional ABI, and CuTeDSL allows the same kernel to be invoked repeatedly with different scalar bindings, so identically named shape / stride symbols can be distinguished.

1.2 Main Repo: GEMM dtype Whitelist Finalized — Unsupported Combinations Rejected Before CUDA Codegen (10-12)

Date: 2026-10-12　Source: GEMM dtype whitelist (#3245)

  • Some T.gemm operand dtype combinations (e.g. bf16 x bf16 to fp16) were previously accepted at the frontend and only failed inside nvcc with an opaque static_assert (issue #3004); this PR adds an explicit dtype whitelist for the Ampere / Ada mma.sync path, enforced on both the frontend (tileop/gemm) and C++ instruction selection, so unsupported combinations are rejected before CUDA codegen with a clear message.
  • Includes 1 negative and 3 positive regression cases; supported combinations and non-Ampere target behavior are unchanged. Merged 10-12 01:21, the latest merge before this window’s cutoff.

1.3 Main Repo: Five PRs Landed — For Step, JIT Output Index, popcount, Bit Reduction, and Test Infrastructure (10-10 ~ 10-11)

Dates: 2026-10-10, 2026-10-11　Sources: For loop step (#3427) / JIT output index (#3318) / popcount (#3300) / bit reduction (#3332) / test infrastructure (#3313)

  • For step (#3427, merged 10-10 12:54): Loop-carried conflict analysis previously treated the step as always 1 (contradicting the comment “defaults to 1, when unspecified”), distorting valid iteration-pair determination under non-unit / signed steps; it now shrinks the iteration-pair range by the explicit step, with both CUDA and HIP codegen preserving the step and delegating emission to CodeGenC, while respecting lexical allocation scopes for unrolled loops.
  • JIT output index (#3318, 10-10 12:02): out_idx=[-1] was polluted by normalization when reused across kernels with different parameter counts (a two-parameter kernel normalized [-1] to [1], and a four-parameter kernel then mistakenly occupied an input slot); it now copies the caller’s list before normalization, rejects scalar indices equal to the parameter count, and reports the valid range.
  • popcount (#3300, 10-10 12:02): Completes CUDA lowering for signed and 8 / 16-bit narrow integers — convert to unsigned at the original width before widening (int8(-1) counts 8 bits rather than 32), with 64-bit going through __popcll; covers 8 dtype regressions; fixes #2984, with all 16 tests passing on H100 (CUDA 13.0).
  • Bit reduction (#3332, 10-11 14:13): reduce_bitand / bitor / bitxor previously checked only the destination buffer and allowed floating-point sources ([1.0, 2.0, 4.5, 8.9] was silently truncated to 1 2 4 8 = 15 with no warning); source and destination are now uniformly rejected under integer / boolean rules (refs #3301).
  • Test infrastructure (#3313, 10-11 18:25): Adds shared IR inspection helpers (node collection, exact operator call counts, external call collection by symbol), migrating issue and transform tests from ad-hoc traversal code to the helpers; lower_ldgstg tests gain structural assertions, and selected transform tests pin the sm_90 target with availability-based skips.

1.4 Main Repo Newly Opened: Two Host IR JIT PRs Plus Nine Others Including Parallel Compilation and Partial-Wave Reduction (10-10 ~ 10-11)

Dates: 2026-10-10, 2026-10-11　Sources: Host IR unification (#3473) / Direct Host IR JIT (#3481) / Parallel JIT compilation (#3476) / Partial-wave reduction (#3478)

  • Host IR line (#3473, #3481): First unifies the CUDA and CuTeDSL execution paths onto Host IR (#3473), then attempts a direct Host IR JIT with a native cache (#3481, experimental, MIR direction) — the JIT host-side refactor becomes a new main line in the main repo.
  • Compilation throughput (#3476): The autotuner compiles mutually independent JIT configurations in parallel, cutting tuning wall-clock time for large configuration spaces.
  • New fix PRs: Partial-wave scalar reduction (#3478), host expression cast grouping (#3477), pipeline epilogue unrolling when trip count is known only at runtime (#3472), optional Ascend example target (#3474); two WIP PRs (#3482 sparse backward gradient atomic accumulation, #3483 MoE stale-routed experts) were opened late on 10-11.
  • Queue: The main repo has 170 open PRs (down 7 from 177 last period).

1.5 TileFoundry: Sparse Decoding Threaded Through TIR; mesh Scope Fix (10-10 ~ 10-12)

Dates: 2026-10-10, 2026-10-12　Sources: Sparse decoding threaded through TIR (#223) / mesh scope (#220) / parser attributes (#221)

  • #223 (merged 10-12 00:52, 84 files, +4424/-1543): Follows up on the DSA decoding issues left by #218 — fixes lost loop workload, over-billed lookup accounting, and incorrect staged updates, and lands indexed asynchronous collection plus Bitcast and Where lowering; allocation constraints move to a single accessor (returning Storage), captured updates write directly to tiles (16B shared memory), and carried values for parameter initialization get independent storage with a preceding copy to preserve inputs; 16 FixtureCase guards each include CLI invocation and output checks; generated tutorial reports are refreshed in sync.
  • #220 (merged 10-10 11:59): Fixes #214 (ISL space comparison crash when the window start is an already-loaded scalar) and #215 (rebinding a mesh inside a loop after external initialization silently retrieves the old value); HIR calls that escape the mesh scope now error, and typed per-call-site mesh propagation is included in the inference cache key.
  • #221 newly opened (under review): Parser support for operator attributes and lexical layout sugar.

II. Multi-Backend Adaptation (Ascend / MetaX / Hygon / Moore Threads)

2.1 Ascend: Sparse MLA Migration Opens Two PRs, SeeSaw and Pipelined; Long-Running Migration Batch Updated Together (10-10 ~ 10-11)

Date: 2026-10-10, 2026-10-11　Source: Sparse MLA SeeSaw (#1869) / Sparse MLA Pipelined (#1870) / NSA Decode (#1701) / WY Fast (#1827)

  • Two new Sparse MLA forward PRs (#1869 / #1870): SeeSaw (seesaw dual-consumer) and Pipelined (pipelined) versions of the Sparse MLA forward operator were opened in the same period — the Ascend porting line for DeepSeek’s sparse attention operator continues to deepen, with the two implementations coexisting for benchmarking.
  • Long-running migration batch updated together (10-10): NSA Decode (#1701, opened 08-27), NSA Bwd (#1730), WY Fast forward/backward (#1827 / #1828), Chunk O Forward (#1866) — over half of the “migrate first, polish later” long-running PRs have advanced.
  • Docs and tests: #1657 (T.tile.relu docstrings and test cases), #1867 (example precision check alignment) updated in the same period; open PRs in the Ascend adaptation repo total 230 (225 in the previous issue).

2.2 Ascend: Four Consecutive Cache Fixes — JIT Specialization Key, autotune Key, NPU and Simulator Cache Separation (10-10)

Date: 2026-10-10　Source: Tuning Params into JIT Key (#1871) / autotune Key Alignment (#1872) / Cache Separation (#1873) / Storage Rewrite Decoupling (#1874)

  • Four PRs opened on the same day: #1871 incorporates tuning parameters into the JIT specialization cache key; #1872 aligns the autotune cache key with effective profiling parameters; #1873 separates Ascend NPU and simulator caches; #1874 makes storage rewrite no longer depend on host NPU availability.
  • All point to the class of issues where “the same pipeline cross-contaminates caches between real hardware and simulator, and across different tuning configurations” — cache semantics tightened on the Ascend side (commits carry auto-tags).

2.3 Ascend: Full MLIR Path Performance Report Merged — All 112 Cases Across 7 Operators Pass; NPU Profiling Support Under Review (10-10)

Date: 2026-10-10　Source: Full Report (#197) / NPU Profiling Support (#198)

  • #197 (merged 10-10 14:34): Updated the TileOPs full performance report — covering 7 operators and 112 correctness cases, all passing (CANN 8.5.0, Ascend 910B2C, msprof profiling); cleaned up old reports, added notes on a write race in a specific T.arange + T.vbrc scenario and a workaround using 1-D arange + reshape.
  • #198 under review: Optional Ascend NPU profiling support — integrates the torch_npu profiler (Level1, AiCMetrics.PipeUtilization), annotates the timeline with tilelang::<kernel> and tilelang.launch::<kernel> to expose the call hierarchy, and includes a CANN launch probe; preserves original launch behavior when disabled.

2.4 Ascend: Main Repo PTO / CANN PR Cluster Under Review — Reduction Helper Vendor, Doc Requirements, and Example Target Selection (10-10 ~ 10-11)

Date: 2026-10-10, 2026-10-11　Source: PTO Reduction Helper Vendor (#3469) / CANN 9.2.0 Docs (#3460) / Example Target Selection (#3474)

  • PTO line: Because upstream PTOAS removed its all-reduce helper module, #3469 vendors the SIMT all-reduce helper back into the main repo’s PTO directory with added tests — a fix for the main repo’s PTO path following an upstream interface change; #3316 (PTO execution routed through PTO codegen) remains under review.
  • CANN / toolchain: #3460 (docs PR requiring CANN 9.2.0 for the Ascend 950 backend), #3461 (bisheng wrapper honors the temp-file cleanup switch), #3468 (L0C fp32 to f16/bf16 dual-copy path conversion), #3466 (scalar sqrt sinking).
  • Others: #3474 (optional example targets, newly opened 10-10), #3324 (torch_npu task queue), #3326 (aibin single-stage compilation dropping ld.lld), #3437 (SimdVF dim=1 reduction), #3455 (SimdVF multi-buffer fill), #3321 (host operator and device kernel correlation profiling).

2.5 Hygon: Register Pipeline Update; MetaX / Moore Threads Silent (10-10 Check)

Date: 2026-10-10　Source: Register Pipeline (#18) / MetaX Repo / Moore Threads Repo

  • Hygon #18 (updated 10-10): Adds a register pipeline to tilelang-hygon (coordinating with the existing shared-memory pipeline, inserting commit and barrier instructions per pipeline stage), enabling warp-diverge when warp count exceeds 4; the self-reported example_gemm has reached rocblas-level performance; 48 files, +4055/-318, under review.
  • MetaX (last push 09-24) and Moore Threads (09-30) showed no new activity within the window.

III. Ecosystem and Adopters

3.1 TileOPs: 21 Merges — Op Base Class One-Shot Refactor Finalized (-5200 Lines) (10-10 ~ 10-11)

Date: 2026-10-10, 2026-10-11　Source: Op Base Class Refactor (#2520) / Op Base Class Guide (TileOPs.github.io #69)

  • #2520 (merged 10-11 06:36, self-described “pre-release” closeout, 363 files, +3362/-5227): Ten commits ordered as “behavior first, mechanical rename second” — operators with and without compilation boundaries now uniformly execute via _run_call, with rollback on failure determined by whether the target was selected by this call; sub-operator calls not belonging to any delegate_for stage now fail the composite call as a whole instead of being silently dropped; _validate_dtypes removed, select_kernel_key / select_implementation merged into key_for; compilation boundaries now derived from the manifest (validating compile_op_names against the cold-compile test set), default_kernel_map removed; constructor parameters such as Gelu / Div moved into the call spec.
  • The docs site followed up the next day with the “Op Base Class Guide” (#69, 10-11), kept in sync with the code refactor.

3.2 TileOPs: MLA / KDA / NSA Performance Batch — SM89 Decode Speedup Up to ~4.6x (10-10 ~ 10-11)

Date: 2026-10-10, 2026-10-11　Source: MLA Decode SM89 (#2511) / MLA Tuning Split Expansion (#2524) / MLA Candidate Pruning (#2525) / WGMMA Descriptor (#2523)

  • MLA Decode (#2511, merged 10-10 22:31): On SM89, selects 2/4/8/16 KV splits by batch and head-block count (targeting 128 CTAs, cap 16), reusing the existing scan and FP32 split-merge kernels — single-request bf16 4k default latency drops from 0.158 to 0.034 ms (~4.6x), 32k from 1.170 to 0.162 ms (~7.2x).
  • MLA Tuning Surface (#2524 / #2525): Tuning candidate splits expanded to 1/2/4/8/16 (candidates from 24 to 40, with a measured 2.00x row against FlashInfer); candidate query tiles whose staged KV exceeds the shared memory budget are pruned (40 down to 20 at D=512), cold tuning plus first tune drops from 348.6 s to 151.6 s, with failed candidates eliminated.
  • WGMMA Descriptor (#2523 / #2504): Descriptors for MLA decode and the DSA seesaw kernel are now constructed via lane 0 broadcast (HGMMA’s R2UR wait eliminated, no overflow) — 26 MLA benchmark rows 0.7% to 4.1% faster; incidentally fixes a hang on SM90 in bs1 partial RoPE decode when the final split block is undersized.
  • KDA Prefill (#2510): SM89 single-sequence 4096 to 64k tokens, up to 8 value heads, split by 16-column value tiles — 4k / 32k / 64k latency reduced by 22.9% / 19.8% / 18.5% respectively.
  • NSA top-k (#2514): Each compressed block assigned to one CTA (query heads fill a 64-row WGMMA tile), in-register bitonic sorting network sorts entire rows (replacing the odd-even transposition sorter), importance ties broken by lower block number.
  • Paged GQA (#2512): SM90 warp-specialized TMA kernel (one TMA producer warp + two consumer warpgroups overlapping QK and PV), one persistent CTA per SM; stale V rows from tile-switching at the cache tail are zeroed before reading; packed layout preferentially dispatched when averaging at least one 128-row tile per request, with the four adopted rows on H200 dropping to 0.44 to 0.88x of original time.

3.3 TileOPs: Five-Part Attention Sinks Series and New Masked FP8 GEMM (10-10)

Date: 2026-10-10　Source: Dense GQA Sinks (#2515) / Paged GQA RoPE / Window / Sinks (#2516) / Packed Varlen Sinks (#2517) / Paged GQA Sinks (#2518) / Paged KV Gather (#2519)

  • superAngGao’s attention sinks series opened five PRs the same day: dense GQA (#2515), paged GQA’s RoPE / window / sinks (#2516), packed varlen (#2517), paged (#2518), and paged KV gather (#2519) — attention “sink token” support rolled out across all GQA variants.
  • Additionally, masked FP8 grouped GEMM (#2521, MoE route) was opened; the Hopper paged GQA single kernel (#2499, self-reported 17/17 comparable cases faster than FlashInfer on H200) remains under review.

3.4 TileOPs: DSA / Paged GQA Fix Batch — Shared Memory Race and Stale Row Exclusion (10-10)

Date: 2026-10-10　Source: DSA SM90 Race (#2503) / Paged GQA Stale Rows (#2480) / Cache Rebuild Batch (#2501)

  • #2503: Fixes three races in the old SM90 DSA decode kernel — shared is_kv_valid mask (out-of-causal-bound keys could be judged live), cp.async.mbarrier.arrive not ordering ordinary stores, and row-sum contention between consumers; incidentally fixes a tail buffer construction defect in DSADecodeBasicKernel.
  • #2480: Stale rows at the cache tail in paged GQA output (zero weights not intercepting when K / V contain NaN) are clamped or zeroed per path — two NaN request regressions (page 64 / 256).
  • Small-item batch: #2501 / #2513 (kernel cache rebuild on csrc header and tuning config changes), #2522 (every autotuning search counted toward untuned config time), #2502 (csrc namespace style), #2498 (KDA chunked prefill decoupled from SM90), #2506 to #2509 (SM89 test group and sampling test closeout).

3.5 Nightly Pipeline: Three New Snapshots — 1032 Correctness Items, 1947 Benchmark Items (52 Suites) Zero Failures (10-10 ~ 10-12)

Date: 2026-10-10 ~ 2026-10-12　Source: Nightly Snapshot (fc2a2a91) / Snapshot Run Metadata

  • Three snapshots within the window: merge points c3146365 (10-11 04:16) to fe5995e0 (10-11 11:46) to 70cfdf84 i.e. #2525 (10-12 03:40, run 38161982847).
  • Latest snapshot: 1032 correctness items, zero failures, zero errors (1 skip being an autotuning case not applicable to SM89 on H200), 1947 benchmark items (52 suites), zero failures, zero errors (1 skip being an unsupported KDA config); each up 2 items from the previous snapshot.
  • Environment: H200 GPU, CUDA 13.2, driver 595.71.05, torch 2.13.0 (cu132), TileLang 0.1.12 (tileops dev build at g70cfdf848).

3.6 Docs and Adopters: Op Base Class Guide Lands with Refactor; Two Main Docs Site Builds (10-10 ~ 10-11)

Date: 2026-10-10, 2026-10-11　Source: Main Docs Site Build (9afde05a) / TileRT Benchmark Docs (#58) / TileKernels / FlashQLA

  • Two automatic builds of the main docs site (44ac4d7f, 9afde05a, 10-10 and 10-11); the TileOPs docs site followed up with the refactor (see 3.1).
  • Adopters and releases: TileKernels and FlashQLA had no pushes within the window (both remain at 09-30); the main repo’s latest tag remains v0.1.15 (09-30), with no new releases in the window; TileRT benchmark docs #58 (GLM-5.1 and vllm PD deployment latency / throughput) is under review (updated 10-10).

IV. Community, Tutorials, and Events

4.1 tilelang-debugger: Offline HTML Debug Reports Go Live, Validated on Both 0.1.12 / 0.1.15 (10-10)

Date: 2026-10-10　Source: tilelang-debugger / HTML report commit (07911c42)

  • Two commits in this window: unified source-access capture (replacing fixed lowered traces with source-access observations, preserving expression-evaluation semantics, supporting dynamic stride parameters, plus frontend compatibility probes and logical atomic / address adapters) — ran 117 CPU / TIR tests each on TileLang 0.1.12 and 0.1.15, 42 collection runs and 66 baseline / instrumented emission pairs on H200, passing independent code and install-package acceptance review; followed by offline HTML debug reports with linked evidence and diagnostics.
  • The project has stayed active for four consecutive windows since its founding on 10-08 (2 commits this window, 9 the previous window).

4.2 PTO-ISA: Eight Commits Advancing SuperNPUBench — mega-moe and tail_ocp_fp8 Specials (10-10 ~ 10-11)

Date: 2026-10-10, 2026-10-11　Source: SuperNPUBench / tilelang-puzzles-ascend

  • Eight commits in this window: mega-moe combine / dispatch version 2 (#217); corrected FP4 peak and MFU metric definitions; further optimization of the rms_norm 32k single-block path (gamma promotion, two in-block R reductions); completion of the M32 triple guards (inf / zero / special) for the tail_ocp_fp8 dynamic / static kernels plus V3 two-dimensional tiling (row-tile granularity with additional N-axis splitting); matmul reuse workbook refreshed and moved into perf_data.
  • The teaching repo tilelang-puzzles-ascend had no commits this window.

4.3 Community: New TileLang-Awesome Repo Created (10-11)

Date: 2026-10-11　Source: TileLang-Awesome

  • The community added SwHwCodesign/TileLang-Awesome (created 10-11, currently initial commit only) — an “Awesome list” effort to organize the TileLang ecosystem has appeared; combined with tilelang-debugger’s continued activity, third-party tooling and resource building around the main project remains warm.

4.4 Media and Academia: Chinese In-Depth Article Published; Overseas Aggregator Piece Continues; No New HN or arXiv Items (10-10 ~ 10-11)

Date: 2026-10-10, 2026-10-11　Source: Zhiwei, “Why DeepSeek’s Open Source Release This Time May Be as Important as R1” / tech-insider.org aggregator piece / Hacker News search / arXiv search

  • Chinese in-depth analysis: The Zhiwei article (10-10 on Fengwen / 10-11 on Zhihu) centers its narrative on TileLang — explaining the Tile abstraction, the three-tier programming interface, and the auto-tuning cache mechanism, and offering a comparison of the Ascend adaptation against Ascend C with “almost no performance difference (A2 / A3),” calling the event’s significance “comparable to R1”; the piece cites TileLang-Ascend code in discussing analogies to the Ascend 950’s Cube / Vector structure and memory architecture.
  • Overseas aggregation: The tech-insider.org piece on 10-11 stitches together a “six-module Ascend toolkit” list and a three-stack comparison of CUDA / ROCm / Ascend from secondary citations including Tom’s Hardware and The Next Web — a continuation of the coverage wave rather than an independent source, included here as secondary reporting.
  • Hacker News had zero items in this window (the most recent related item being the 10-02 discussion “DeepSeek open-sources Ascend programming stack”); arXiv had no new preprints (the latest related item being the 07-24 TileSight analytical model paper).

V. Trend Observations

5.1 A Full Weekend: 34 Merges Spanning Saturday, Sunday, and Early Monday

  • The 34 merges break down as 23 on Saturday, 9 on Sunday, and 2 in the early hours of Monday; the 42 newly opened PRs follow the same around-the-clock distribution (new opens continued from Sunday evening into early Monday). Compared with the previous window (Friday) at 21 merges — weekend merge volume exceeded the prior workday, and the project’s “7×24 rolling” cadence is now stable.
  • The evaluation baseline rolls in step: three nightly snapshots across the two days with no gaps, with correctness at 1,032 items and benchmarks at 1,947 items continuing to climb.

5.2 Refactor Wrap-Up and Version Silence: A Release Window in Sight

  • Three signals converge: TileOPs’ Op base-class refactor is described as wrapping up “pre-release” (a one-time net reduction of roughly 1,865 lines); the docs site followed the next day with an “Op Base Class Guide”; the main repo’s tags have stayed silent since v0.1.15 on 09-30, while the nightly pipeline keeps refreshing the evaluation baseline with zero failures.
  • Engineering-quality actions (naming / cache semantics / review guardrails) continued to land densely this window — the path of “solidify the baseline first, cut the official version after” is clear, and the static groundwork for the next release is already in place.

5.3 Hardware Coverage Expands in the Same Week: SM121 Lights Up, SM89 Performance Policies Land in Batches

  • Within the same window: SM121 (GB10 / DGX Spark) lights up block-scaled MMA (#3430); SM89 (RTX 40 series / L40 class) receives a batch of decode performance policies (#2510 / #2511 / #2506); SM90 (H100 / H200) continues to be refined (#2512 / #2497 / #2503).
  • The hardware focus is shifting from “single-generation Hopper optimization” to “multi-generation co-maintenance, with consumer-grade entering the mix”; domestic backends move in step: two Ascend sparse MLA migration commits plus a four-commit cache fix streak, and a Hygon register pipeline update.

Appendix: Sources and Verification Notes

Source Verification Result
tile-ai organization (29 repos) 8 repos had pushes in the window: tilelang (9 merged, 9 opened), TileOPs (21 merged, 24 opened), TileFoundry (2 merged, 1 opened under review), tilelang-mlir-ascend (1 merged), tilelang-hygon (#18 updated), TileOPs-nightly (3 snapshots), tilelang.github.io (2 builds), TileOPs.github.io (1 merged); organization total for the window: 34 merged, 42 opened; 498 open PRs total
Main repo tilelang 9 merged (#3400, #3300, #3318, #3427, #3414, #3430, #3332, #3313, #3245); 9 opened (#3472, #3473, #3474, #3476, #3477, #3478, #3481, #3482, #3483); 170 open PRs (177 last issue); no new releases or tags in the window (latest v0.1.15, 09-30)
Ascend repos (ascend / mlir-ascend) ascend: no merges this window; 6 opened (#1869 through #1874), multiple updates to the long-running migration batch; 230 open PRs (225 last issue). mlir-ascend: 1 merged (#197), #198 under review
Hygon / MetaX / Moore Threads Hygon: #18 (register pipeline) updated 10-10, under review; MetaX (last push 09-24) and Moore Threads (09-30) had no activity
TileOPs 21 merged (#2480, #2497, #2498, #2501 through #2514 range, #2520, #2522, #2523, #2524, #2525); 24 opened; 9 open PRs (6 last issue)
TileOPs-nightly Three new snapshots: c3146365 (10-11 04:16), fe5995e0 (10-11 11:46), 70cfdf84 (10-12 03:40, merge point #2525); latest correctness 1032 items, benchmark 1947 items (52 suites), zero failures and zero errors
TileFoundry 2 merged (#220, #223); 1 opened (#221, under review)
Adopters and community TileKernels and FlashQLA had no pushes in the window (both 09-30); TileRT #58 under review (updated 10-10); tilelang-debugger 2 commits; TileLang-Awesome new repo created (10-11)
PTO-ISA organization SuperNPUBench 8 commits in the window; tilelang-puzzles-ascend no updates
Google News / Hacker News / arXiv Google News 4 hits (1 Chinese in-depth analysis, 1 overseas aggregation, 2 background reports, none first-hand); HN zero entries; arXiv no new preprints

Full Source List