Research window: Past 24 hours (2026-09-18 07:00 ~ 2026-09-19 07:00, Beijing time). This is a regular daily window with no overlap with the previous issue. Sources: GitHub (full check of push times across 28 repositories in the tile-ai organization; 6 repositories had pushes within the window; 2 merges and 5 newly opened PRs in the main repo reviewed individually, including PR descriptions, number of changed files, and lines added/removed; 5 merges and 1 newly opened PR in TileOPs; Ascend repo daily regression reports, CI changes, and 2 commits; full parsing of benchmark and correctness XML from the TileOPs-nightly snapshot; verification of the Sunrise backend distribution repository and branches), Google News RSS multi-language queries (via proxy), Hacker News, arXiv, adopter repositories (TileKernels / FlashQLA)

Issue Index

  • Today’s Highlight: Main repo opens a new CUDA Tile IR execution backend, 134 files, ~36k lines added (09-18)
  • I. Core Project Progress
    • 1.1 Injectivity proof for symbolic loop layouts restored, mixed static and dynamic T.Parallel regression fixed (09-18)
    • 1.2 ROCm CI adds portable example validation, indirectly confirming the ROCm path is entering a convergence phase (09-18)
    • 1.3 Five new PRs opened in the main repo within the window: Tile IR backend, copy width clamping, 256-bit memory access starting from SM100, GLM-5.3 and KDA examples (09-18/09-19)
    • 1.4 TileOPs merges five in one day: decoupling of dispatch and tuning, SM90 shape completion, paged KV helper extraction, sparse MLA out-of-bounds fix, manifest composite operators (09-18)
    • 1.5 TileOPs opens FP8 batched matmul transpose kernel, directly catching up with the reference implementation (09-18)
  • II. Multi-Backend Adaptation (Ascend / Sunrise / MetaX / Hygon / Moore Threads)
    • 2.1 Ascend: Daily regression passes all 1936 items, and multi-device test sharding is introduced (09-18/09-19)
    • 2.2 Ascend: Comparison operator docs complete dtype coverage, benchmark script buffer lifetime fix (09-18)
    • 2.3 Sunrise backend distribution: TANG backend for the S2 accelerator enters 0.1.14 candidate (09-16/09-18)
    • 2.4 MetaX, Hygon, Moore Threads: No new commits within the window, version branch maintenance maintained (09-17)
  • III. Ecosystem and Adopters
    • 3.1 FlashQLA ends its silence: three merges on the same day, including an SM120 backward fused kernel (09-18)
    • 3.2 TileOPs nightly benchmark: 1040 items with zero failures, correctness 1118 items all passing (09-18)
    • 3.3 TileKernels and TileRT had no pushes within the window (04-23, 08-13)
    • 3.4 Community tools: TileSight profiling documentation repository goes live, corresponding to the arXiv performance model paper (09-18)
  • IV. Community, Tutorials, and Events
    • 4.1 Organization documentation site had one site deployment within the window, no content changes on the default branch (09-18)
    • 4.2 Zero additions on the media and academic side within the window (09-19)
    • 4.3 Release cadence: Main repo remains at v0.1.14, tags in adaptation repos unchanged (09-11)
  • V. Trend Observations
    • 5.1 A second NVIDIA-side execution path takes shape: from CUDA source generation to CUDA Tile IR
    • 5.2 The main repo continues to move silent semantic errors forward into compile-time failures
    • 5.3 TileOPs advances performance and contracts in parallel, nightly benchmark turns green
    • 5.4 Recovery on the adopter side, FlashQLA merges three in a single day
    • 5.5 Backend matrix expansion: from a single Ascend pole to multiple backend distributions coexisting
  • Appendix: Materials and Verification Notes

Today’s Highlight: Main Repo Opens a New CUDA Tile IR Execution Backend, 134 Files in a Single Commit

Date: 2026-09-18　Source: tilelang #3247 Add CUDA Tile IR execution backend

The heaviest item in this window appeared in the main repo’s review queue: an execution backend named tileir was submitted as a PR, with a change size of 134 files, approximately 35,829 lines added, and 111 lines removed, submitted by 0xtaruhi, created at 20:40 Beijing time on 09-18, and continuously updated within the window.

What it does is lower TileLang programs to NVIDIA’s CUDA Tile IR, then launch the assembly artifact via the cuTile runtime, with the target version combination being CUDA Tile IR 13.4 bindings, tileiras 13.4, and cuTile 1.5. Compared with the existing CUDA backend (which directly generates C/CUDA source code and hands it to nvcc), this is a new path at a higher semantic level: TileLang behavior lands directly on Tile IR, and compilation and optimization are delegated to NVIDIA’s own tile-level intermediate representation.

The accompanying changes are equally systematic, indicating that this is not a prototype but is being written to productization standards:

  • The backend is integrated into three places: JIT compilation, kernel caching, and autotuning, with changes in tilelang/jit/adapter/tileir, tilelang/cache, and tilelang/autotuner; the typed IR, lowering, and pass core are placed in tilelang/tileir;
  • A pass configuration option is added, used to still execute the existing source-language semantic checks before Tile IR launch materialization (including on the path restored from cache), while retaining a configurable disable switch;
  • Full example coverage under the new toolchain is restored, with one specific task being to isolate handwritten host-side pybind bindings from nvcc so that extension headers compile cleanly under CUDA 13.4;
  • Two documents are added (one on compiler internals and one programming guide) plus a dedicated CI job that builds fixed-version TileIR bindings.

The test plan given by the author covers unit tests and lowering cases, the JIT, cache, and tuning pipeline, and regression of all examples. It should be noted that as of the end of the window, this PR remains unmerged; the change size is large and the target toolchain version is new, so whether it ultimately lands in the mainline depends on review. This issue lists it as the highlight because it contributed the largest single piece of substantive engineering content within the window and points to TileLang’s backend route choice.

I. Core Project Progress

Window Overview: In the main repo’s default branch, only 2 merges landed within the window (one each at 09-18 14:56 and 09-19 01:56), but the review queue was active—5 new PRs were opened during the window, all still unmerged. In other words, the main repo’s focus this window was on “submitting new pathways + submitting defensive fixes,” with a slow merge cadence. TileOPs was the opposite, merging 5 PRs in a single day.

1.1 Injectivity Proof for Symbolic Loop Layouts Restored, Mixed Static and Dynamic T.Parallel Regression Fixed (09-18)

Date: 2026-09-18　Source: tilelang #3233 Restore injectivity proof for symbolic loop layouts / related bug report #2906

The only semantic fix in the main repo this window, addressing a regression between v0.1.12 and mainline, submitted by sepcnt, 4 files, +198/-13, merged 09-18 14:56 (Beijing time).

The triggering scenario is quite specific: when the T.Parallel iteration space is a mix of static and dynamic forms (e.g., (16, n) with n set to T.dynamic), the layout has a padded tail, and its loop layout is injective but not bijective, with a domain that cannot be enumerated. Previously, the check on this path would fall back to “no check,” but some intermediate change switched it to actually attempting a proof, which then couldn’t handle symbolic strides—so such kernels would directly report “no usable layout found” on mainline, even though they ran fine on v0.1.12.

The fix restores the injectivity proof for symbolic padded loop layouts: it attempts to construct an inverse mapping from the iteration map under test, then proves round-trip equality over the domain. The author documented the blind-spot differences between the two checking approaches at the call site, keeping both—meaning this is not a simple revert to old behavior, but rather filling in the correctness argument.

A second independent part rejects attaching layouts to symbolic shared memory tiles, submitted in the same batch as the first part, the result of the same author having the scope redrawn during review.

1.2 ROCm CI Adopts Portable Example Validation, Confirming ROCm Pathway Entering Convergence (09-18)

Date: 2026-09-19　Source: tilelang #3165 Run portable example validation in CI

Merged 09-19 01:56 (Beijing time), this adds a small whitelist to the ROCm CI job, directly running the examples’ own correctness paths rather than maintaining a duplicate set of test cases under the test directory. The whitelist covers four categories: Seer attention, general Top-K, sparse multi-head latent attention forward, and tensor-based grouped matrix multiplication.

The significance of this change lies in the shift in where coverage comes from: previously AMD-side validation was carried by a specially maintained test copy; now it’s “examples as tests.” When a backend starts using the examples themselves as regression assets, it usually means that backend’s examples have stabilized enough to serve as a baseline, and maintainers no longer need to lay down a separate test suite for it.

1.3 Five New PRs Opened in Main Repo During Window: Tile IR Backend, Copy Width Clamping, 256-bit Memory Access from SM100, GLM-5.3 and KDA Examples (09-18/09-19)

Date: 2026-09-18 to 2026-09-19　Source: #3246 Copy width clamping / #3247 Tile IR backend / #3248 256-bit memory access / #3249 KDA decode example / #3250 GLM-5.3 compression

Besides the Tile IR backend featured in today’s highlights, four other new entries appeared during the window, listed by creation time:

First, #3246 (09-18 15:39) clamps the merge width upper bound of T.copy and T.async_copy to the actually achievable vector width, replacing the previous fatal log. Previously, passing an unsupported width would terminate the process directly with LOG(FATAL); after the change, it clamps to a usable value and continues compilation. This runs counter to—but complements—the previous issue’s direction of “moving silent errors forward into explicit failures”—here it’s changing “crash outright” into “degrade and continue,” with the criterion being that the width upper bound is a capability constraint rather than a user semantic error.

Second, #3248 (09-19 01:35) corrects the applicable targets for 256-bit global memory access: the width is only emitted on SM100 and newer architectures with CUDA 12.9 or above, with older architectures falling back to the 128-bit pathway, plus added negative tests on older architectures. This belongs to the same category of work as the previous issue’s atomic vector width planning—both fill in dependent conditions on top of new wide-vector capabilities.

The third and fourth are both in the ROCm direction: #3249 (09-19 02:23) adds a KDA decode example with safety gating, writing a packed decode kernel in TileLang that updates a slot-indexed circular state pool in place, with added correctness coverage for output and state consistency, multi-step, empty state indices, out-of-order slots, and configurable boundaries; #3250 (09-19 06:42) adds GLM-5.3’s k-pool compression and cache writes, including per-dimension softmax pooling, normalized Hadamard-128 transform, and per-vector FP8 quantization, writing FP8 K values and FP32 scales into a caller-held paged cache.

Notably, these new ROCm-direction items are all specific operators for specific models (GLM-5.3’s compressed attention, KDA gated linear attention’s decode state), rather than generic backend capability fill-in. This indicates that AMD-side progress has shifted from “the backend works” to “new models’ native operators must also exist here.”

1.4 TileOPs Merges Five in One Day: Dispatch-Tuning Decoupling, SM90 Shape Fill-in, Paged KV Helper Extraction, Sparse MLA Out-of-Bounds Closure, Manifest Composite Operators (09-18)

Date: 2026-09-18　Source: #2147 Manifest composite operators / #2149 Sparse MLA out-of-bounds / #2150 Paged KV helper extraction / #2151 SM90 shape fill-in / #2152 Dispatch-tuning decoupling

TileOPs merged 5 PRs this window, falling into three categories:

Contract-related—#2147 (merged 08:36) enables the operator manifest to describe composite operators; this was reported as unmerged in the previous issue and landed this window. It also consolidates duplicate derivation logic previously scattered across multiple places and supports nullable outputs. Its problem list was detailed in the previous issue and is not repeated here.

Dispatch correctness—#2152 (merged 19:27) decouples “tuning requests” from “implementation selection.” Previously the tune parameter should only have affected how kernels are built, but two specialized implementations used it as a dispatch condition, causing the same shape to select different implementations merely because the caller requested tuning—with the batched matrix multiply template directly rejecting tuning requests. After the fix, the selector kernel is independent of tuning.

Blind-spot fill-in—#2151 (merged 15:42) fills in a shape range on SM90 that no one was responsible for: the base GEMM kernel excludes all of SM90, while the general GEMM kernel only serves TMA-addressable calls, and the subtraction of the two leaves a gap—specifically, cases where operands are half-precision and K is not a multiple of 8 while M is greater than 2. The fix has the base kernel take over this portion.

Correctness closure—#2149 (merged 13:02) fixes two issues: the gather operation in sparse multi-head latent attention decoding previously only checked the causal upper bound, so when top-k slots were padded with the sequence length or -1, it would read rows the cache did not hold; the fix clamps the upper bound to sequence length minus one and performs a non-negative check on each index. The other fix makes paged attention timing trustworthy under fragmented layouts.

Structural refactor—#2150 (merged 13:22) moves five paged KV cache helper functions out of the grouped query attention module. These five functions (interleaved block table construction, fragmented block table construction, paged cache row fetch, paged cache fill by logical sequence, and unit cache scale construction) are not exclusive to grouped query attention, and the multi-head attention module previously had to depend on it in reverse; they are now an independent layer.

The common thread across the five merges: TileOPs’ current main engineering effort is not in “adding new operators,” but in the dispatch consistency, module boundaries, and memory safety exposed as operators multiply.

1.5 TileOPs Opens New FP8 Batched Matrix Multiply Transpose Kernel, Directly Chasing the Reference Implementation (09-18)

Date: 2026-09-18　Source: TileOPs #2153 Transpose FP8’s B operand with a coalesced-access kernel

The only new PR opened in TileOPs during the window (updated 09-18 16:18, unmerged). The background is stated bluntly: the FP8 batched matrix multiply forward operator loses to the reference implementation in 4 of 5 cases with trans_b=False, with the worst case trailing at 0.34x. The author first re-verified the reference implementation’s consistency with the fp32 reference, confirmed the reference wasn’t cheating, then chose to implement the B operand transpose as a coalesced-access kernel rather than continuing to patch the shared template.

This continues the same line as the previous issue’s batched matrix multiply speedup (switching to a shared GEMM template, up to 1.44x on H200): batched matrix multiply has already caught up to or surpassed the reference on standard shapes, with remaining weaknesses concentrated in data type variants (FP8) and layout variants (requiring B transpose). Whether this affects the shared template’s generality will need to wait for nightly benchmark regression results after merging.

II. Multi-Backend Adaptation (Ascend / Sunrise / MetaX / Hygon / Moore Threads)

Window Overview: This window saw a structural change in the domestic and third-party backend landscape—in addition to the existing four backends (Ascend, Hygon, MetaX, Moore Threads), the tile-ai organization now hosts a backend distribution repository (Sunrise) targeting a new accelerator, which has advanced to a release-candidate branch. Among the four existing backends, only Ascend had commits during this window.

2.1 Ascend: All 1,936 Daily Regression Tests Pass, Multi-Device Test Sharding Introduced (09-18/09-19)

Date: 2026-09-19　Source: tilelang-ascend daily test report #1813 / CI multi-device test sharding #1812

The Ascend-side daily scheduled test report was generated at 05:52 Beijing time on 09-19: all 1,936 tests passed, 0 failures, a 100% pass rate. Compared with the previous day (1,925 tests at 05:46 on 09-18) and the day before that (1,919 on 09-17), the total case count grew by a net 17 over two days while remaining fully green—direct evidence that upstream capabilities continue to be merged in without breaking Ascend-side regression.

In the same window, the repo opened another CI change (#1812, titled to add generic multi-device test sharding), created at 16:31 on 09-18 and still being updated at 19:22 that day, not yet merged. As the case count keeps growing, single-machine regression time will lengthen accordingly, making sharding a natural move.

2.2 Ascend: Comparison Operator Docs Gain dtype Coverage, Benchmark Script Buffer Lifetime Fixed (09-18)

Date: 2026-09-18　Source: #1602 Update comparison operator docs and add dtype coverage / #1779 Fix buffer return token lifetime in benchmark script

Both Ascend-repo commits in this window landed at 15:10 and 15:31 Beijing time on 09-18: one updated the comparison operator docstrings, added data type coverage tests and API documentation; the other fixed the return token lifetime of accumulators and output temporary buffers in bench_sfa, preventing buffers from being reclaimed before use completes. Neither is an operator capability expansion; rather, they fill in documentation, test coverage, and benchmark script robustness for existing operators—viewed alongside the regression scale growth in 2.1, the Ascend side is currently in a phase of “capabilities already rolled out, focus shifting to quality and maintainability.”

2.3 Sunrise Backend Distribution: TANG Backend for S2 Accelerator Enters 0.1.14 Candidate (09-16/09-18)

Date: 2026-09-18　Source: tile-ai/tilelang-sunrise repository

A repository under the tile-ai organization not previously covered by this briefing entered the push list during this window: tilelang-sunrise, created on 2026-08-26. Its self-description positions it as the Sunrise S2/TANG backend distribution of TileLang—Sunrise S2 is a domestic GPGPU for large-model inference, and TANG is its compilation and runtime stack (the repo requires TANG Runtime along with a matching torch backend package and a matching Triton package). The provided operator examples cover matrix multiplication, dequantized matrix multiplication, FlashAttention, Flash linear attention, Flash multi-head latent attention decoding, and native sparse attention—i.e., the same example surface as the main repo.

Progress status: the repo had pushes during the window (09-18 11:03), but the last commit on the default branch is dated 09-04; on the release-candidate branch carrying release preparation, the latest commit is a version update on 09-16 that bumped the version to 0.1.14+sunrise.1.1.0, i.e., it has already tracked the main repo’s v0.1.14 line. The repo also has a batch of pending dependency-upgrade PRs and one CI branch.

Key takeaway: this is a “backend distribution” rather than a “patch branch” form—independent repo, independent version number (with a suffix after the main repo version), independent CI. Together with Hygon’s feat/hcu-... branches and Moore Threads’ suffixed backport branches, it constitutes three distinct approaches to organizing adaptation. Since the repo’s self-description and examples are isomorphic to the main repo, it can be seen as another inference accelerator pathway for TileLang—beyond NVIDIA/AMD/Ascend—entering a releasable state.

2.4 MetaX, Hygon, Moore Threads: No New Commits in Window, Version Branch Maintenance Continues (09-17)

Date: 2026-09-17　Source: tilelang-metax / tilelang-hygon / tilelang-musa

None of the three adaptation repos had commits within the 24-hour window; their most recent pushes fell at 17:38 on 09-17, 20:25 on 09-17, and 03:47 on 09-17 Beijing time respectively, all before the window and already covered in the previous issue: MetaX’s async copy matrix multiplication and its test fixes, Hygon’s multi-level memory address rebasing and async pipeline merge, and Moore Threads’ MUSA 5.3.0 documentation. None of the three had version tag updates during the window; the latest tags remain no release for MetaX, no release for Hygon, and v0.1.14+musa.1 for Moore Threads (09-11).

III. Ecosystem and Adopters

3.1 FlashQLA Ends Its Silence: Three PRs Merged the Same Day, Including an SM120 Reverse-Fusion Kernel (09-18)

Date: 2026-09-18　Source: FlashQLA #34 SM120/121 reverse-fusion kernel／#41 SM100 KKT solve occupancy／#44 async pipelining for variable-length tail tiles

In the previous report, the “quiet on the adopter side within the window” section explicitly noted that FlashQLA had no pushes; in this window it merged three PRs on the same day, tightly clustered between 15:51 and 15:53 Beijing time on 09-18 — a batch close-out.

The three PRs are:

  • New hardware support (#34): adds a reverse-fusion kernel for SM120/SM121 to the chunked gated delta rule. The implementation largely follows the earlier Hopper pipeline; the main difference is the shared-memory reduction strategy — SM120 has a lower shared-memory ceiling, so the reduction had to be redesigned around that constraint.
  • Occupancy tuning (#41): adds a minimum blocks-per-streaming-multiprocessor residency annotation to both the fixed-length and variable-length KKT solve kernels, targeting eight 128-thread thread blocks resident per streaming multiprocessor. The KT math, layout, launch grid, and public interface are all unchanged.
  • Correctness fix (#44): in the variable-length packed scenario, the final tile with fewer than 64 rows previously over-read into the next sequence. The fix preserves the direct memory access fast path for full tiles, switches incomplete tail tiles to predicated zero-fill async copies, and splits the tail-tile staging across multiple channels.

Both categories of change point to the same thing: FlashQLA (the Qwen-side gated linear attention implementation built on TileLang) is shifting its engineering focus from “new architecture adaptation” to “occupancy and boundary correctness on the same architecture.” The clustered three-PR merge also indicates a batch-review rather than per-PR merge cadence.

3.2 TileOPs Nightly Benchmark: 1040 Cases, Zero Failures; 1118 Correctness Cases All Pass (09-18)

Date: 2026-09-18　Source: TileOPs-nightly snapshot commit／snapshot environment metadata

In this window the nightly pipeline generated a snapshot for TileOPs 4c5b441f (the “dispatch and tuning decoupled” merge from 1.4), comprising benchmark results, correctness results, and environment metadata. Parsing the two result files yields:

  • Correctness: 1118 cases, 0 failures, 2 skipped;
  • Benchmark: 1040 cases, 0 failures, 3 skipped.

Compared with the previous day’s snapshot (1117 correctness cases all passing, 1 failure out of 1039 benchmark cases), the case counts each rose by 1, and yesterday’s sole benchmark failure has disappeared — that failure was the grouped query attention prefill paged kernel under the softcap 50 configuration, and the error came from a function signature mismatch (missing argument) in the reference baseline implementation, not from a TileOPs kernel itself. Turning green today indicates the reference-side issue has been addressed.

The environment metadata pins down reproducibility factors fairly completely: H200, CUDA 13.2, driver 595.71.05, 700 W power cap, 1500 MHz per-SM clock (1980 MHz max), 3201 MHz memory clock, the image recorded by its content digest, and full dependency versions (among them TileLang 0.1.11 plus a codename build for that commit, and PyTorch 2.13.0). The benchmark case surface covers decode-class operators (sparse attention decode, multi-head latent attention decode, grouped query attention variants) and 27 batched matrix multiply cases — the latter being precisely the battleground where the reference implementation was surpassed in 1.5.

3.3 TileKernels and TileRT: No Pushes Within the Window (04-23, 08-13)

Within the window, neither DeepSeek’s TileKernels nor tile-ai’s TileRT had any commits; their most recent push times remain 2026-04-23 and 2026-08-13 respectively. TileRT has now been static for six consecutive weeks. All adopter-side activity in this window came from FlashQLA.

3.4 Community Tooling: TileSight Profiling Documentation Repo Goes Live, Corresponding to an arXiv Performance-Model Paper (09-18)

Date: 2026-09-18　Source: tilelang4tilesight-doc repo／arXiv 2607.22432 TileSight

A community member created a new documentation repo in this window, on the theme of connecting TileLang profiling to the TileSight toolchain: extracting semantics, workload, and dependency information from Python and high-level TIR, plugging into TileSight’s cache and pipeline analysis interfaces, then using runtime observations to generate standalone reports and joint predictions. The repo gives a reading order for four Chinese-language documents (the overall scheme for the model and runtime paths, TileSight’s stage and frontend interfaces plus pipeline analysis, the cache module, and the profiling features and protocol cross-reference index), and classifies performance issues into six categories: pipeline bottlenecks, cross-level transfer anomalies, cache utilization anomalies, compute/memory-access overlap failures, and load imbalance. The documentation explicitly requires reports to distinguish three levels of conclusion strength: “model prediction,” “runtime observation,” and “insufficient evidence.”

The corresponding academic backdrop is an arXiv performance-modeling paper dated 2026-07-24 (a tile-level analytical GPU performance model from core to cluster), the most recent preprint under the TileLang topic. Together, the two materials indicate that performance explainability around TileLang is forming a third community thread independent of the language itself and the operator libraries. The repo is a personal project with no stars yet; it is included because it is the only substantive community-side addition in this window.

IV. Community, Tutorials, and Events

4.1 Organization Docs Site: One Site Deployment Within the Window, No Content Changes on the Default Branch (09-18)

Date: 2026-09-18　Source: TileOPs.github.io repo

The TileOPs docs site had a push record within the window (09-18 08:00), but its default branch saw no new commits in the window, so this is judged to be a site-deployment action rather than a content update. The main repo’s docs site had no pushes in this window, in contrast to the previous day’s bot regeneration (387 files) — the docs site following upstream code is inherently pulsed.

4.2 Media and Academia: Zero Additions Within the Window (09-19)

Multiple Google News RSS queries on the topic, in both English and Chinese, returned zero hits within the window: on the English side, only one strongly topic-relevant report appeared in the past 7 days — the piece already covered in the previous issue about a DeepSeek engineer evaluating AI’s ability to write kernels — and its publication time falls within the previous window, so it is not repeated here; on the Chinese side, all combined queries for component names, domestic accelerators, and operator kernels returned no in-window results. On Hacker News, no topic discussions hit within the past five days (the TileOPs and tile-type keyword hits retrieved were all unrelated topics). On arXiv, there were no new preprints within the window.

4.3 Release Cadence: Main Repo Still at v0.1.14, Adapter Repo Tags Unmoved (09-11)

The main repo’s latest tag remains v0.1.14 (released 09-02), with no new tags in the window; TileOPs still has no release record to date; the Ascend repo’s latest tag is TileLang-ascend v0.1.2.000-release (09-09); the Moore Threads repo’s most recent tag is v0.1.14+musa.1 (09-11). The release cadences of the latter two both align with the main repo’s minor versions, and both currently sit on the v0.1.14 line, not yet having advanced to a new version alongside the mainline.

V. Trend Observations

5.1 The Second NVIDIA-Side Execution Path Takes Shape: From CUDA Source Generation to CUDA Tile IR

The most noteworthy development this period is the opening of #3247. TileLang’s previous NVIDIA path was “lower to an intermediate representation with tile semantics, then generate CUDA source, and finally hand off to nvcc”; the new path instead “lowers to CUDA Tile IR, is compiled and optimized by NVIDIA’s tile-level toolchain, and loaded via the cuTile runtime.” The coexistence of the two paths means: first, TileLang’s abstraction level is beginning to directly border on NVIDIA’s own tile-level abstraction, and who bears scheduling and layout decisions will become a long-term issue; second, once the Tile IR path matures, TileLang’s value proposition on the NVIDIA platform will shift partly from “better code generation” toward “more complete program expression and cross-backend consistency.” The scale of this PR (an entire backend complete from compilation to caching to tuning to documentation and CI) also shows it is not an experimental branch.

5.2 The Main Repo Continues to Move Silent Semantic Errors Forward into Compile-Time Failures

Continuing the observation from the previous period, among the two merges in the main repo in this window, one is clearly (the layout proof restoration in 1.1) of the “turn silent errors into explicit errors” kind. Together with the cumulative random-number diagnostics, unsupported type-combination interception, and sparse metadata shape rejection from the previous three periods, this has made “compile-time failure first” a stable engineering orientation in the main repo. The new information added this period is the boundary of this principle: in 1.3, changing the fatal log for copy width into a clamped degradation shows that maintainers are distinguishing “user semantic errors” (which should fail) from “capability constraints” (which should degrade)—this is not a loosening of the principle, but a clarification of the criteria.

5.3 TileOPs Advances on Both Performance and Contract Fronts, Nightly Benchmarks Turn Green

Among TileOPs’ five merges in this window, three concern dispatch, module boundaries, and memory safety, one concerns the manifest contract, and only one (the newly opened FP8 batched matrix multiply) is purely performance-related. Viewed together with the nightly benchmark shifting from “1 failure” to “zero failures,” its current state is: the performance baseline is stable and can already beat the main shapes of the comparison implementation, so engineering resources are turning toward consistency and contracts after multiple operators coexist. This is a typical signal of an operator library in its mature phase—the more operators there are, the more important the correctness of dispatch and manifests becomes for upper layers.

5.4 Adopter Side Warms Up, FlashQLA Lands Three Merges in One Day

The previous period’s judgment that “adopters are quiet” is overturned in this period: FlashQLA merged three PRs on the same day, covering a new architecture (SM120/SM121 backward fused kernels), occupancy tuning, and variable-length tail-block correctness. This suggests that updates in adopter repositories are pulse-like—review backlogs accumulate to a certain volume and are then merged in batches, and silence over a single day or several days does not constitute a trend. At the daily-report level, it is necessary to avoid interpreting single-period silence as stalled adoption.

5.5 Backend Matrix Expansion: From a Single Ascend Pole to Multiple Backend Distributions Coexisting

The Sunrise backend distribution discovered in this window provides a new read on the landscape: TileLang’s backend ecosystem is no longer limited to the two forms of “backends built into the main repo” and “adaptation repos opened by vendors within their organizations”—a backend distribution with its own independent version number and CI has also appeared. Three types of adaptation forms have been identified so far—Ascend’s independent adaptation repo (multiple branches, including daily regression), Hygon’s feature branches and suffixed backport branches, Moore Threads’ version-aligned backport branches, plus Sunrise’s independent distribution. The differences in form themselves reflect each vendor’s depth of investment in TileLang and degree of productization, and are a usable indicator for judging domestic accelerators’ dependence on the TileLang ecosystem.

5.6 Gaps and Risk Points in This Window

Three points need to be flagged: first, only two merges landed in the main repo during the window, and one of them is a revert-type fix (restoring v0.1.12 behavior), so net new capability on the mainline is limited; second, once a very large change like #3247 is merged, the regression surface for the existing CUDA path and cache format will require additional observation, and there is no evidence on this yet in this period; third, no new tags or releases appeared in this window—the main repo has gone more than two weeks without a release since v0.1.14 on 09-02, while the review queue continues to accumulate.

Appendix: Sources and Verification Notes

Source Verification Table

Source Verification Result
tile-ai organization (28 repos) 6 repos had pushes within the window: tilelang, TileOPs, TileOPs-nightly, tilelang-ascend, tilelang-sunrise, TileOPs.github.io
Main repo tilelang default branch 2 merges (#3233, #3165), 5 new PRs opened (#3246 to #3250), no new tags
Main repo nightly/organization repos TileOPs-nightly generates snapshots for TileOPs commits; TileRT, TileFoundry, tilescale, DeepStack, tilelang-puzzles had no pushes within the window
Four domestic backends Only Ascend had commits and regression reports within the window; MetaX, Hygon, and Moore Threads last pushed before the window
Third-party/new backends The Sunrise backend distribution repo had pushes within the window; the candidate branch version was bumped to 0.1.14+sunrise.1.1.0
Adopters FlashQLA merged 3 commits; TileKernels had no pushes
Google News RSS (multiple Chinese and English queries, via proxy) Zero new items within the window; queries combining component names and technical terms likewise returned no in-window results
Hacker News No topic hits within the window; keyword noise was filtered out
arXiv No new preprints within the window; the most recent is a performance modeling paper dated 2026-07-24
Documentation site The TileOPs documentation site had a site deployment action; no content changes on the default branch

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