Research window: Past 24 hours (2026-09-16 19:23 ~ 2026-09-17 19:23, Beijing time; this task is the first trial run of the daily 07:00 scheduled job, with the assessment moved to the evening of the same day, while the window is still taken as 24 hours) Sources: GitHub (full pushed_at audit of 28 repositories under the tile-ai organization, with 9 repositories showing pushes within the window; commit-by-commit review of tilelang, tilelang-ascend, tilelang-metax, tilelang-hygon, TileOPs and other repositories within the window, with verification of key PR descriptions and benchmark data; cross-validation of branch and tag metadata), third-party adaptation and adopter repositories (tilelang-mlir-ascend, tilelang-musa, TileFoundry, TileRT, deepseek-ai/TileKernels, QwenLM/FlashQLA), Google News RSS multi-query searches in Chinese and English (via proxy), Hacker News, arXiv, on-site coverage of Huawei Connect 2026 (see appendix source list for details)

In This Issue

  • Today’s Highlight: T.gemm_blockscaled enters the main repo—block-scaled quantized GEMM now has a unified entry point (09-17)
  • I. Core Project Progress
    • 1.1 Main repo adds T.gemm_blockscaled and backend selector, block-scaled quantization no longer silently degrades (09-17)
    • 1.2 Atomic vector width now planned by destination address, embedding backward and other kernels speed up 1.4x to 2.5x (09-17)
    • 1.3 Atomic add stays scalar on non-contiguous destination addresses, fixing a class of silent miswrites and address misalignment crashes (09-17)
    • 1.4 JIT adds uint64 parameter type mapping, Cython and NVRTC host wrappers aligned (09-17)
    • 1.5 TileOPs: MoE index small-router expert path, comprehensively ahead of vLLM on H200 (09-17)
    • 1.6 TileOPs: kernel selection and build dispatch refactored, four operator parameters migrated into constructors (09-16/09-17)
  • II. Multi-Backend Adaptation (Ascend / MetaX / Hygon / Moore Threads)
    • 2.1 Ascend: NSA forward and its variable-length version land the same day, reaching the 20-microsecond range on 910B3 (09-17)
    • 2.2 Ascend: dynamic quantization, RMSNorm fusion, and RoPE examples round out the operator surface (09-16/09-17)
    • 2.3 MetaX: MACA asynchronous copy GEMM support lands (09-17)
    • 2.4 Hygon: HCU backend rebases multi-level storage and buffer storage, pipeline switches to prefer_async (09-17)
    • 2.5 Moore Threads: MUSA 5.3.0 documentation adds backport branch (09-17)
    • 2.6 Industry: Huawei Connect 2026 announces Ascend 960 and Atlas 960 supernode progress (09-17)
  • III. Ecosystem and Adopters
    • 3.1 tilelang-mlir-ascend: TileOPs multi-head attention operators and adaptive LayerNorm merged (09-16)
    • 3.2 Adopter repositories quiet within the window: TileKernels, FlashQLA, TileRT all show no pushes
    • 3.3 Third-party: TileSight performance analysis technical roadmap document made public (09-17)
  • IV. Community, Tutorials, and Events
    • 4.1 Documentation site continues to sync with the main repo (09-17)
    • 4.2 Academic and tutorial track: ICLR 2026 papers and Hugging Face kernel tutorials (background, outside window)
  • V. Trend Observations
    • 5.1 Four domestic backends evolve in parallel on the same day, adaptation shifts from one-way following to synchronized advancement
    • 5.2 Two tracks run in parallel in the main repo: block-scaled quantization capability for new hardware and performance recovery for existing kernels
    • 5.3 TileOPs is shifting from an operator library toward a production-grade operator layer that can be benchmarked against inference engines
    • 5.4 Gaps and risk points in this window

Today’s Highlight: T.gemm_blockscaled enters the main repo—block-scaled quantized GEMM now has a unified entry point

Date: 2026-09-17　Source: tilelang #3237 block-scaled quantized GEMM semantics and backend dispatch

The heaviest change in the main repo this window elevates “block-scaled GEMM” (MXFP8/MXFP4-class low-bit-width matrix multiplication with per-block shared scale factors) from special cases scattered across backends to a formal operator at the language level. The change introduces GemmBlockScaledNode (implemented in src/op/gemm_blockscaled.{h,cc}) and the language-side T.gemm_blockscaled, with semantics written as C (+)= (A * SFA) @ (B * SFB), i.e., scale factors are first-class inputs to the operator rather than something the caller manually folds in externally.

It also fixes two paths that previously failed silently: first, single-CTA block-scaled GEMM on SM100 could hit an instruction selection branch that should only be taken by SM120; second, backends without block-scaled quantization capability would execute it as a degraded dense GEMM, with scale factors simply discarded—the result would run, but the precision would be wrong. Dispatch now goes through a dedicated backend selector, landing on two implementations: cuda.tcgen05.blockscaled (SM100 line) and cuda.mma.blockscaled (SM120 line), while retaining parameter entry points such as mbar, use_2cta, and sf_layout. The author verified locally on an SM100-class device (sm_103), covering the MXFP8 block-scaled example with 1D1D layout and tcgen05 INT8 GEMM assertions, and explicitly noted that the SM120-side execution path was not locally verified.

Merged the same day, #3238 is the dual action on the other track: rather than adding new capability, it recovers a performance regression introduced by an earlier change—see 1.2. Read together, the main repo’s current rhythm is advancing “adding new hardware paths” and “recovering existing kernel performance” simultaneously.

I. Core Project Progress

Window Overview: Of the 28 repositories in the tile-ai organization, 9 had pushes during the window: the core repo tilelang, the domestic backends tilelang-ascend, tilelang-metax, tilelang-hygon, and tilelang-musa, the operator library TileOPs along with its sites TileOPs.github.io and TileOPs-nightly, and the documentation site tilelang.github.io. By number of commits in the window, tilelang-ascend leads with 6, followed by tilelang with 4, TileOPs with 3, tilelang-metax with 2, and tilelang-hygon with 1; tilelang-musa’s push landed on a backport branch rather than the default branch, so there are no in-window commits on its default branch.

1.1 Main Repo Adds T.gemm_blockscaled and Backend Selector, Block-Scaled Quantization No Longer Silently Degrades (09-17)

Date: 2026-09-17　Source: tilelang #3237

See “Today’s Highlights.” Two additional implementation-side details: first, block-scaled quantized GEMM has been split out of GemmImpl and registered separately per backend, so dense GEMM and block-scaled quantized GEMM each use their own implementation slot, avoiding a recurrence of the path confusion where “some backend treats it as a dense operator”; second, the two shared entry points tl.gemm.infer_layout and tl.gemm.lower are now required to strictly accept 13 positional parameters, forcing newly added operators to explicitly declare a complete interface rather than slipping through on defaults. The PR title carries a “Do not review” prefix and was self-merged by a core maintainer, landing with 19 commits.

1.2 Atomic Vector Width Now Planned from Destination Address, Embedding Backward and Other Kernels Speed Up 1.4x to 2.5x (09-17)

Date: 2026-09-16 to 2026-09-17　Source: tilelang #3238

Dynamic shapes introduce int64 conversions beyond the lane index; the previous vectorization check only recognized the unsimplified Ramp form, so when it encountered an equivalent expression such as “broadcast base address plus int64 lane offset,” it scalarized the entire loop—even though four aligned contiguous elements were being accessed, execution degraded to element-by-element. The fix changes the check to be based on the destination address (coordinated across three places: elem_offset, IndicesCanVectorize, and AtomicTargetIsContiguous), and provides median comparisons from three measurements on the same card against baseline c6ece48: embedding backward N=8192/H=4096/V=129280 drops from 97.90 microseconds to 56.01 microseconds, N=196608/H=256/V=3000000 drops from 146.87 microseconds to 82.70 microseconds, another case drops from 86.62 microseconds to 49.87 microseconds, and sequence auxiliary counting and summation drops from 18.40 microseconds to 12.17 microseconds; in the regression benchmarks, example_gqa_bwd_tma_reduce_varlen achieves roughly a 27% relative improvement, while other cases fluctuate between 0.5% and 1.5%. This is a classic case of “compiler rewrite rules affecting real inference performance”—the affected embedding backward and variable-length attention backward are both resident kernels in large-vocabulary inference.

1.3 Atomic Add Stays Scalar on Non-Contiguous Destination Addresses, Fixing a Class of Silent Miswrites and Address-Misalignment Crashes (09-17)

Date: 2026-09-16　Source: tilelang #3219

Another vectorization defect from the same root as 1.2: when the destination address of T.atomic_add is an expression that is invariant within the vector boundary (such as indexing by i divided by 2, or a constant index), the old logic selected width based only on data type, compiling a semantic where “all lanes write to the same cell” into a single wide atomic add, silently corrupting adjacent elements; when the base address is odd, it directly triggered an address-misalignment crash. The fix adds a CanVectorizeAtomicTarget pre-check covering the three destination address forms address_of, tl.access_ptr, and tvm_access_ptr, falling back to scalar whenever non-contiguous or unaligned. The impact of this defect is not small—T.Parallel with T.atomic_add is a common pattern in GEMM split-K, attention backward, and layer normalization, and existing tests happened to bypass it with configurations where N equals the thread count.

1.4 JIT Adds uint64 Parameter Type Mapping, Cython and NVRTC Host Wrappers Aligned (09-17)

Date: 2026-09-17　Source: tilelang #3229

The host-side wrapper previously lacked a type mapping for uint64, directly reporting “unsupported dtype” when encountering such a parameter. After the fix, both host paths—Cython and NVRTC—can handle uint64 arguments, aligned with the device-side uint64_t declaration. A small gap, but failing to patch it would directly hit a wall on large-integer indexing and bitwise-operation kernels.

1.5 TileOPs: MoE Indexed Small-Routing Expert Path, Broadly Ahead of vLLM on H200 (09-17)

Date: 2026-09-17　Source: TileOPs #2141

The most substantial item on the operator library side this window. The change adds an indexed small-routing expert path to the shared fused MoE: when routing groups are sparse and individual experts actually receive very few tokens, it switches to an index-based aggregation execution mode, avoiding the inefficient path under large groups. The public interface is unchanged; unsupported devices and shapes, large routing groups, and unverified activation and layout combinations all retain the existing fallback. On H200 with BF16, top-8 sigmoid routing plus correction bias, CUPTI device-occupancy timing, and L2 flushing, the author compared against vLLM across three models: GLM-4.5 leads by 25.85% at the 4096-token tier, DeepSeek-V3 leads by 16.03% at the same tier, Kimi K2 leads by 8.65%, and it also generally leads at small-token tiers. The benchmark itself was rebuilt (the previous baseline was untrustworthy), and it reports whole-group improvements of at least 49.3% for FusedTopK and at least 59.6% for PermuteAlign; the comparison data notes that routing is fixed-seed synthetic routing rather than real checkpoint traces, which is honest disclosure.

1.6 TileOPs: Kernel Selection and Build Dispatch Refactor, Four Operator Parameters Migrated into Constructors (09-16/09-17)

Date: 2026-09-16 to 2026-09-17　Source: TileOPs #2146, TileOPs #2145

The structural work landed on the same day as the performance changes in 1.5, part of the same round of internal cleanup. First, the dispatch model changed to “first select the kernel, then ask it how to build” (Op.kernel_for / Op.entry_for), with the entire GEMM family now dispatching through the selected class rather than being judged at the call site; second, four operators that previously took parameters per call moved their parameters to the construction stage, among which MHP forward would directly throw an attribute error on the first call if there was an external target, and the paged prefill operator held a sequence-length field that was never assigned at construction—both real defects; additionally, the output type parameter of six operators was uniformly renamed to out_dtype, and FP8 GEMM and its batched version now accept torch data types rather than strings. The author explicitly states that this change does not modify the kernel bodies or generated code, so no performance claims are made; the value lies in eliminating drift such as “reading one device’s architecture at selection time and another device’s at build time.”

II. Multi-Backend Adaptation (Ascend / MetaX / Hygon / Moore Threads)

This window’s shape is four domestic backends present on the same day: Ascend 6 commits, MetaX 2, Hygon 1, Moore Threads 1 (backport branch documentation). This is a rare density for this daily’s collection—all four had substantive activity on the same day, rather than staggered.

2.1 Ascend: NSA Forward and Its Variable-Length Version Land the Same Day, Reaching the 20-Microsecond Range on 910B3 (09-17)

Date: 2026-09-17　Source: tilelang-ascend #1699, tilelang-ascend #1700

Both land on the ascendc_pto branch of the Ascend-specific repo, merged four minutes apart (11:44 and 11:49 Beijing time). #1699 is the native sparse attention (NSA) forward operator: implemented in a hybrid developer-mode style, with the compiler automatically splitting Cube and Vector scopes and automatically inserting cross-core synchronization flags—no hand-written global barriers, scope declarations, or manual flag bits required; under the golden configuration the task takes 19.62 microseconds, with all 27 layered precision tests passing and a maximum absolute error of 1.95e-03. #1700 adds variable-length sequence support, with a single-kernel forward, persistent grid, and four-stage pipeline; on 910B3 the test configuration takes 20.34 microseconds, with all 21 layered tests passing and a match ratio of 1.0000 under the dual-gate tolerance standard. Taken together, Ascend’s coverage of DeepSeek-family sparse attention structures has moved from “has an implementation” to “with variable length and layered testing.”

2.2 Ascend: Dynamic Quantization, RMSNorm Fusion, and RoPE Examples Round Out the Operator Surface (09-16/09-17)

Date: 2026-09-16 to 2026-09-17　Source: tilelang-ascend #1688, tilelang-ascend #1673, tilelang-ascend #1580

Three example-layer changes together show Ascend filling in “the routine operators along the inference path”: the dynamic quantization operator (#1688), after CANN benchmarking and online evaluation, passes all 20 precision cases with an average speedup of 0.78x—that is, precision is usable while performance still lags the vendor baseline, recorded faithfully rather than as a win; the dynamic quantization fusion operator stacked with RMSNorm (#1673) and the rotary position embedding operator (#1580, covering both half-rotation and interleaved layouts, with benchmark scripts and precision tests against torch_npu) fill in the two links of large-model inference preprocessing and position encoding. In addition, #1603 adds interface documentation and test cases for T.tile.merge_sort.

2.3 MetaX: MACA Asynchronous Copy GEMM Support Lands (09-17)

Date: 2026-09-17　Source: tilelang-metax #156

The MetaX side adds an asynchronous copy GEMM path for the MACA platform, involving three entry points—asynchronous memory copy primitives, barrier instructions, and asynchronous copy completion counting—enabling matrix multiplication data movement to go through an asynchronous pipeline; the same day there is also a test case defect fix (#157). For MetaX this is a step “from running to running fast,” since asynchronous copy is precisely the prerequisite for GEMM pipeline overlap.

2.4 Hygon: HCU Backend Rebases Multi-Level Storage and Buffer Storage, Pipeline Switches to prefer_async (09-17)

Date: 2026-09-17　Source: tilelang-hygon commit 36db42e1

A single commit on the Hygon side touches 19 files; the action is to rebase the write paths of multi-level storage (MLS) and buffer storage, and to switch the pipeline’s copy scheduling to prefer_async. The newly added buffer offset dependency checker distinguishes between “block-index-related” and “thread-index-related” categories, then separates the block base address from the residual offset in a syntax-directed manner—the comments spell out the boundary here: the buffer annotation is the caller’s safety contract, and the compiler does not attempt range proofs. This aligns in direction with the MetaX commit: both are replacing synchronous movement with asynchronous pipelines.

2.5 Moore Threads: MUSA 5.3.0 Documentation Added to Backport Branch (09-17)

Date: 2026-09-17　Source: tilelang-musa branch list

The in-window push to the Moore Threads repo lands on the v0.1.12+musa.1 backport branch, adding MUSA 5.3.0 documentation to the older version line; the default branch has no in-window commits. This signal is weak: the mainline’s last substantive commit was the 09-11 public release preparation and a batch of runtime capabilities on 09-10 (symmetric IPC allocation, IPC and optional virtual memory management runtime, DLPack device compatibility, system-level fences); the MUSA side this period is maintenance activity rather than new capability.

2.6 Industry Side: Huawei Connect 2026 Announces Ascend 960 and Atlas 960 Supernode Progress (09-17)

Date: 2026-09-17　Source: Huawei Connect 2026 on-site report (National Business Daily, reposted by STNN), Ascend 960 slated for Q1 2027 (NetEase repost)

Ascend is the most active of TileLang’s domestic backends, and its hardware roadmap directly affects the pace of operator and kernel adaptation, so one industry-side item is listed. On September 17 at Huawei Connect 2026 held in Shanghai, Huawei Vice Chairman and Rotating Chairman Wang Tao announced that Ascend 960DT is moved up to a Q1 2027 release and Ascend 960PR to Q3 2027; a single Atlas 960 supernode can achieve high-speed interconnection of 4096 NPUs, relying on the Lingqu architecture and Hi-ONE optical engine with a minimum round-trip latency of 2 microseconds, and applies near-package optics (NPO) optical engines for the first time, with a liquid-cooled version planned for Q3 2027. The event also claimed cumulative deployment of over one thousand supernodes, serving more than 370 customers.

As background (not within this window): on September 8 at PyTorch Conference China 2026, Ascend stated it has become the first Chinese hardware officially supported by PyTorch, and plans to co-build a native software stack for supernodes with PyTorch. Taken together, Ascend’s software ecosystem position is rising, which is a tailwind for the operator DSL layer (including the TileLang Ascend backend).

III. Ecosystem and Adopters

3.1 tilelang-mlir-ascend: TileOPs Multi-Head Attention Operators and Adaptive LayerNorm Merged (09-16)

Date: 2026-09-16　Source: tilelang-mlir-ascend commit list

This repo merged a change on the evening of 09-16 (close to the front boundary of this window) that “brings in TileOPs’ multi-head attention operators,” and fixed defects in its benchmark scripts; the adaptive LayerNorm kernel had been added the day before. The repo also switched CI to the Ascend A3 device runner label — indicating that on the Ascend side, work is not limited to writing operators but also involves moving validation into real-device pipelines.

3.2 Adopter Repos Quiet Within the Window: No Pushes to TileKernels, FlashQLA, or TileRT

Date: 2026-09-17 (verification)　Source: deepseek-ai/TileKernels, QwenLM/FlashQLA, tile-ai/TileRT

According to this briefing’s verification checklist, none of the three adopter- and inference-side repos had any pushes within the window: TileKernels’ most recent push was 2026-04-23, FlashQLA’s was 2026-08-26, and TileRT’s was 2026-08-13. TileRT has now gone five consecutive weeks without an update, making it the longest-quiet item on the current list. This does not constitute a negative conclusion, but it warrants continued tracking — TileRT targets a low-latency inference runtime, and a prolonged stall would leave the narrative that “the TileLang ecosystem has entered production deployment” lacking fresh engineering-side evidence.

3.3 Third Party: TileSight Performance Analysis Technical Roadmap Document Made Public (09-17)

Date: 2026-09-17　Source: tilelang4tilesight-doc repo

A third-party developer has published a set of technical documents on interfacing TileLang programs with the TileSight performance analysis tool. The content covers extracting semantics, workload, and dependencies from Python and high-level intermediate representations, integrating cache and pipeline analysis, and generating independent reports and joint predictions from runtime observations. The documents classify performance issues into six categories: pipeline bottlenecks, cross-level transfer anomalies, cache utilization anomalies, compute-memory access overlap failures, load imbalance, and model prediction deviation, and explicitly distinguish three levels of conclusion strength: model prediction, runtime observation, and insufficient evidence. The primary platform discussed is H200. The value here lies in the fact that TileLang’s observation and tuning toolchain is being filled in by outside parties.

IV. Community, Tutorials, and Events

4.1 Documentation Site Continues to Sync with the Main Repo (09-17)

Date: 2026-09-17　Source: tilelang.github.io commit list

The documentation site had one automated sync commit within the window (09-17 18:37 Beijing time), with additional ones on 09-16, 09-15, and 09-12, keeping pace broadly aligned with main-repo merges. The site is currently at version 0.1.14, and the tools section already includes entries for compilation tools, profilers, layout visualization, automatic incremental debugging, intermediate representation lowering tracing, and operator profiling. Documentation-site syncs are bot commits; this report records them only for cadence.

4.2 Academic and Tutorial Track: ICLR 2026 Paper and Hugging Face Kernel Tutorial (Background, Outside Window)

Date: 2026-04-23 to 2026-05-31 (outside-window background)　Source: ICLR 2026 poster page, TileLang paper (arXiv:2504.17577), Hugging Face tutorial “Writing High-Performance Kernels in TileLang”

Within this window, no new TileLang-related content appeared in arXiv, Hacker News, or Chinese- and English-language news searches, so only pre-existing academic and tutorial assets outside the window are listed here for reference: the paper claims up to 5x speedup over Triton on H100 and up to 90% reduction in code size for fused attention kernels; the Hugging Face tutorial provides a complete walkthrough from GEMM to multi-head latent attention and records one real-world gain — a model configuration that previously had no fast path went from “throwing an error outright” to “shippable” after switching to a plug-and-play kernel written in TileLang.

V. Trend Observations

5.1 Four Domestic Backends Evolving in Parallel on the Same Day, with Adaptation Shifting from One-Way Following to Synchronized Advancement

Ascend, MetaX, Hygon, and Moore Threads all had landed changes within the same 24-hour window, and their directions are highly convergent: all are filling in asynchronous transfers and pipelining (MetaX’s async-copy GEMM, Hygon’s prefer_async, Ascend’s multi-stage pipelining), and all are filling in routine operators for the inference pipeline (dynamic quantization, RMSNorm fusion, positional encoding). This shows that adaptation on domestic backends is no longer “wait for upstream to ship a feature, then follow up,” but rather each filling in the same set of capabilities within the same round.

5.2 Two Parallel Tracks in the Main Repo: Block-Wise Quantization Capability for New Hardware and Performance Recovery for Existing Kernels

The two major changes in the main repo within this window are opposite in nature yet merged on the same day: one establishes a unified entry point and dedicated dispatch for block-wise quantization GEMM on the Blackwell generation (avoiding fallback and path confusion), while the other restores a vectorization regression caused by an earlier rewrite (nearly doubling embedding backward speed). Block-wise quantization corresponds to the spread of low-bit-width formats such as MXFP8/MXFP4 on the inference side, while performance recovery corresponds to the resident kernels for large-vocabulary inference — neither falls into the “new operator” type of expansion, but rather compiler-layer stability and efficiency work, which typically indicates entry into engineering maturity more than point operators do.

5.3 TileOPs’ Positioning Is Shifting from an Operator Library to a Production-Grade Operator Layer That Can Be Benchmarked Against Inference Engines

In this window, TileOPs did two things at once: first, it provided full-table performance data benchmarked against vLLM (leading by 25.85% at the GLM-4.5 4096-token tier and 16.03% at the same tier for DeepSeek-V3); second, it cleanly refactored kernel selection and build dispatch and consolidated inconsistent interface parameters in one pass. The willingness to publish tier-by-tier comparisons against vLLM while also acknowledging that the benchmarks were previously unreliable indicates that its acceptance criteria are moving toward production readiness; the fact that the Ascend-side mlir repo has begun directly integrating TileOPs operators is a signal that this set of criteria is starting to be reused across backends.

5.4 Gaps and Risk Points in This Window

Four gaps must be noted honestly: first, on the news side, there were no hits on TileLang itself across Chinese- and English-language channels within 24 hours, and the same-name noise found in searches (a database product renamed Tile.ai, an unrelated 2048 reinforcement learning repo) does not count as activity; second, the adopter repos (TileKernels, FlashQLA) and the inference runtime TileRT were all quiet, with TileRT having been stalled for five weeks; third, there were no new papers on the academic side within the window; fourth, aside from Ascend’s block-wise quantization, domestic backends remain focused mainly on “filling in routine capabilities,” with no performance data yet that benchmarks against vendor baselines and wins — Ascend’s dynamic quantization operator at 0.78x speedup is one example: accuracy passes but performance lags, and whether this converges will need continued tracking in subsequent windows.

Appendix: Sources and Verification Notes

Verification method: All entries are based on repository committer time; repository push time and commit time were checked separately. For new commits in this window, titles and PR descriptions were read one by one, and for key changes the verification methodology and benchmark data in the body were also reviewed. For branch-push repositories (Moore Threads), attribution was traced to the specific branch, confirming no in-window commits on the default branch. For third-party links whose body text was unavailable (including some media pages), only existence was cited and their nature noted in the body.

Limitations: First, the GitHub API hit unauthenticated rate limiting during local collection (60 requests per hour); late in the window, verification of the documentation site, the mlir repo, TileFoundry, and TileRT was switched to repository commit streams, with a slight trade-off in repository coverage, and the verification method for each step is noted in the body. Second, the measured data for Ascend and MetaX comes from self-reported commit descriptions and PR bodies; no corresponding hardware was available locally, so no independent reproduction was performed. Third, industry-side developments come from public reports; no first-hand vendor announcement originals were obtained.

Source Verification Table

Source Verification result
tile-ai organization (28 repos) 9 repos had pushes in the window
Commit detail review tilelang 4, tilelang-ascend 6, TileOPs 3, tilelang-metax 2, tilelang-hygon 1
tilelang-musa No in-window commits on the default branch; pushes landed on the backport branch v0.1.12+musa.1
tilelang-mlir-ascend No pushes in the window; most recent was the evening of 09-16 (one hour outside the window’s front boundary)
TileFoundry / DeepStack / tilescale No pushes in the window; most recent were 09-15 / 09-15 / 08-25 respectively
TileRT No pushes in the window; most recent 2026-08-13, five consecutive weeks without updates
Adopter repos TileKernels / FlashQLA No pushes in the window; most recent were 2026-04-23 / 2026-08-26 respectively
Google News RSS (multiple Chinese and English queries) Zero hits for topic terms and component names in the window; the TileDB rename and 2048 reinforcement learning repo hits were same-name noise and were excluded
Industry news channels Two on-site reports from Huawei Connect 2026 were usable; 1 was included
Hacker News No TileLang-related discussion in the window
arXiv No new papers in the window; the main paper is the existing version v2

Complete Source List