Reporting period: September 30, 2026 (Wednesday) to October 7, 2026 (Wednesday), 8 days total; special National Day holiday summary period (October 1–7 is the holiday, daily reports paused) Sources: This publication’s daily RuyiAI activity reports (one issue on 2026-09-30, window 09-29 04:30 ~ 09-30 04:30; no daily report material during the 10-01 ~ 10-07 holiday); also includes a 216-hour window audit of organizational repositories, dual-source community verification, and a full-period scan of the technical intelligence repository (coverage through the morning of 10-08) Editorial note: This period spans the National Day holiday—code merges entered a low-output mode during the holiday, while the review queue, intelligence repository, and community channels kept operating; all technical facts come from hands-on verification of code repositories, releases, and community forums

1. Weekly Highlights

  • openRuyi 2026.09 officially released: RVA23 refinements, expanded cloud and storage software stack, repo GPG verification enabled (09-30): The release announcement went live on the first day of this cycle (not yet visible within the 09-30 daily window; a newly discovered item in this cycle’s review). Key points: GCC 16 backports a BCLR codegen fix—eliminating the DPDK rte_softrss() hang and Mesa ACO scheduler miscompilation; DPDK 25.07 enables RVV lookup paths on RVA23 (lpm / fib / acl / node); OpenJDK merges 15 RISC-V patches (Zbs / Zfa instruction generation, RVV vset optimization, CRC32C intrinsic); on the container side, after allowing riscv_hwprobe, testing on SpacemiT V100 shows OpenSSL enabling Zvkned / Zvknhb vector crypto extensions and zlib-ng enabling Zbc-accelerated crc32; kernels 7.2.6 / 6.18.54; newly added Cloudpods 4.0.3 multi-cloud platform, SPDK 25.09 (io_uring / RBD bdev / SMA), and Ceph 21.3.0 snapshot; the installation pipeline enables GPG signature verification by default; security updates land in batch (expat / jq / vim / pcre2 / runc, etc.); four editions offered—Server / Container / Desktop / Zero—plus an experimental RVA20 edition. Source: openRuyi 2026.09 release

  • “PyTorch RISC-V CI in Practice” blog post published: Ruyi community, together with XuanTie and RISE, discloses a real-machine CI system (live in the early hours of 10-08): The post reveals the full picture of PyTorch RISC-V continuous integration—co-built by RuyiAI (Institute of Software, Chinese Academy of Sciences), the XuanTie team, and the RISE AI/ML working group: it adopts a Debian Trixie / Python 3.13 / GCC 14 / OpenBLAS 0.3.33 baseline, “build once, test on multiple machines”; Jenkins parallel sharding (core tests about 3 hours, full suite about 5 hours); dynamic sharding based on historical durations; a unified blocklist managed through manual classification; failure logs centrally archived (community-ci.openruyi.cn); SyncBots continuously syncs upstream main into the RISC-V working branch and automatically triggers core tests—the RISC-V core test suite currently passes consistently and stably. The work originated from the XuanTie team’s RFC (pytorch#171659) and tracking issue (#180975); the Institute of Software is a RISE member, and a RuyiAI member serves as co-chair of the RISE AI/ML WG. Source: blog post (Chinese-English bilingual), RFC #171659, tracking #180975

  • PyTorch fork ends its silence: riscv branch resumes daily sync and completes a full rebuild in the early hours of 10-08 (09-30 ~ 10-08): The riscv branch had been silent since 09-21, and maintainer pushes resumed on the morning of 09-30—thereafter roughly once per day (7 times from 09-30 to 10-07); in the early hours of 10-08 (Beijing time) a full rebuild was completed—the local patch stack was replayed in order (23 patches starting from #1 RISC-V Blocklist, including #44 bytes_to_scalar fix, #50 inductor blocklist, #42 ULP tolerance, etc.), and the SyncBots integration commit advanced the upstream sync point to e188cec; the baselines of 8 open PRs (#23 / #35 / #36 / #38 / #43 / #46 / #48 / #51) were uniformly refreshed—the two RVV PRs (#46 ATen RVV support, #48 RVV CPU capability) and the CI local image (#51) are among them. Source: riscv branch commits, PR list

  • llvm-project riscv branch: three SpacemiT A100-series patches merged (10-03); nightly rebuild cadence continues through the holiday (10-01 ~ 10-07): #30 lowers IME intrinsics to A100 dot-product instructions, #32 adds A100 pack/unpack intrinsic lowering and scheduling, and #31 adds A100 HP/SP and pack/unpack lowering and calibrates the scheduling model—the three were merged in succession on 10-03; the branch maintains nightly rebuilds (in the early hours of Beijing time), with the last rebuild of the window headed at 03e4e494. The standard AME pre-approved backend PR #22 (opened in July, 7 discussions) was closed on 10-02 (not merged); the two FPGA PRs (#25 / #28) remain under review and received baseline refreshes. Source: PR #30, PR #31, PR #32, PR #22

  • Two riscv-gcc P-extension PRs merged (10-02); Ztt draft toolchain workstream opens (from 09-30): #20 (abs / pabs series changed to header-file operator lowering with test fixes) and #21 (removing an erroneous same-channel PAS/PSA combine pattern) were merged on 10-02 (author TelGome); during the same period, a new ztt-dev branch was opened in riscv-gcc and riscv-binutils to add register operands, instruction encoding, and CSR support for the Ztt draft extension, with continuous commits through the holiday (including codegen optimizations, latest through the morning of 10-08); riscv-gnu-toolchain added an ame-experimental branch. Source: PR #20, PR #21, ztt-dev branch

  • Matrix extension workstream in place: AME-operator repo open-sourced, official AME spec repo fork lands (09-30): The ruyisdk organization created the AME-operator repo—RISC-V AME/Ztt GEMM and GEMV kernels, an independent numerical reference, and a DejaGNU/Spike verification suite (covering INT8 / UINT8 / INT32 / FP32 / BF16, T=4~128; smoke tests ran 16 ELFs and 32 executions, all passing); on the same day it forked the official RISC-V attached-matrix-extension (the AME task group’s management repo). With this, the matrix direction forms a three-line layout: “LLVM (BOSC AME / A100) - GCC/Binutils (Ztt) - operators and verification (AME-operator)”. Source: AME-operator repo, attached-matrix-extension fork

  • During the National Day holiday, “intelligence and review both continue without pause”: ruyiai-daily publishes 9 consecutive issues, the openRuyi review queue stays active, and new community courses launch (09-30 ~ 10-08): The technical intelligence repo ruyiai-daily pushed 9 consecutive issues through the holiday (issues from 09-30 to 10-08, going live every morning), maintaining the five-chapter structure of PyTorch ecosystem / LLVM-MLIR / Triton and TileLang / RISC-V / AI industry; on the open PR side, the openRuyi queue saw intensive review around audit enabling RISC-V support (#1399), the go-github-chewxy-math32 RISC-V test fix (#1398), moby 29.8.1 (#1395), and more; the community forum published the lecture notes and labs for Chapter 01 “Environment and Toolchain” of the “RISC-V Linux in Practice” course (10-04, 10-06) as well as a dev-board example repo resource post (09-30). Source: ruyiai-daily, forum #2885

  • triton-riscv: Nightly 2026-10-04 build released; softmax and matmul optimization PR opened (10-05, 10-08): Nightly builds maintain a weekly cadence—Nightly 2026-10-04-12c2f6a was released on 10-05 (x86_64 and riscv64 wheels covering CPython 3.12 to 3.14); on the morning of 10-08, PR #85 “softmax and matmul optimization” was newly opened (community contributor). Source: Nightly 2026-10-04, PR #85

II. RuyiAI Stack Progress (PyTorch / Triton / TileLang RISC-V Adaptation)

Window Overview: The RuyiAI-Stack organization (18 repos) focused this cycle on llvm-project (A100 series merged, nightly rebuilds), pytorch (daily sync, full rebuild and PR refresh), triton-riscv (weekly builds, new PR), ruyiai-daily (9 issues), and the site blog; tilelang-riscv, mxnet, caffe, FBGEMM, cpuinfo, VecIntrinBench, IntrinTrans, torq-tile, dsh-osc, pytorch-ci, etc. had no commits; harness had no commits but saw review activity on the PR side.

PyTorch fork: From “quiet wrap-up” to “daily sync + full rebuild”

  • Holiday sync (09-30 ~ 10-07): The riscv branch resumed pushes on the morning of 09-30 (previously silent since 09-21), followed by roughly one maintenance push per day (09-30, 10-01, 10-02, 10-04, 10-05, 10-06, 10-07 — 7 total), executed by the branch maintainer — these are rebuild-style syncs (patch stack replayed onto a newer upstream baseline); routine upstream syncs on the main branch continued (general commits such as MPS, ROCm, inductor are excluded per filtering rules).
  • Full rebuild (early morning 10-08): The branch completed its final full rebuild of the window — the 23-patch stack was replayed in order (the earliest dating back to April’s RISC-V Blocklist #1 and CI buildout #6~#12), with the SyncBots integration commit (e188cec) placed on top; the baseline status of 8 open PRs was refreshed in sync, with update times unified to 10-08.
  • RVV pending-review queue: Two vector patches (#46 ATen RVV support, #48 RVV CPU capability) remain queued — this period’s updates were triggered by the rebuild; the CI local mirror PR #51 (requiring native riscv64 hardware) sits in the same queue.
  • Background context: This rebuild echoes the “PyTorch RISC-V CI in Practice” blog post — SyncBots continuously syncs upstream main and automatically triggers core tests, embodying the closed loop from “upstream tracking to on-hardware regression” (see this week’s highlights for details).

Compiler line (llvm-project): A100 series merged, nightly rebuilds, AME path convergence

  • A100 series (merged 10-03): #30 “Lower IME intrinsics to SpacemiT A100 dot instructions” — lowers IME intrinsics to SpacemiT A100 dot-product instructions; #32 “Add A100 pack/unpack intrinsic lowering and scheduling”; #31 “Add A100 HP/SP and pack/unpack lowering with calibrated scheduling” — all three merged in succession within a single day, forming the foundation for A100 platform instruction lowering and scheduling on the LLVM side.
  • Nightly rebuilds (every night 10-01 ~ 10-07): The riscv branch maintained its nightly (Beijing time early morning) rebuild cadence over the holiday; starting the night of 10-03 it included the A100 series changes; the window’s final rebuild advanced the sync point to the window’s last upstream commit (head 03e4e494), with the status of three pending PRs refreshed accordingly.
  • AME path changes: The standard AME (RVI, pre-approval stage) backend PR #22 was closed on 10-02 (not merged, with 7 discussion threads since opening); the BOSC AME scanline (#29 and the preceding series) and the two FPGA PRs (#25 / #28) are the currently active paths in the repo.

triton-riscv: Weekly build cadence maintained, new optimization PR opened

  • Nightly 2026-10-04-12c2f6a (released 10-05): Maintained the weekly build cadence (previous issue 09-27); wheels cover CPython 3.12 through 3.14, dual-architecture x86_64 and riscv64.
  • PR #85 “softmax and matmul optimization”: Opened on the morning of 10-08 by a community contributor (under review); the earlier renovate dependency PR #84 remains open.
  • The main branch’s latest commit still dates to 09-14 (no functional commits over the holiday).

TileLang and other target repos: Silent throughout the period

  • tilelang-riscv (latest commit 07-16), FBGEMM (07-13), cpuinfo (05-20), torq-tile (04-09), dsh-osc (09-15), pytorch-ci (no commit records) all saw no activity over the holiday; mxnet and caffe had no commits (previously opened PR queues saw no updates within the window).
  • harness: no commits; PR #2 “Integrate Triton-RISCV agent backend and workbench with Harness” received a review update on 10-01 (aligning with triton-riscv’s agent workbench direction).

Tech intelligence and site (ruyiai-daily / blog / site)

  • ruyiai-daily published 9 consecutive issues: Daily pushes from 09-30 through 10-08 (going live around 06:15 each day), maintaining the five-chapter structure; over the holiday it covered PyTorch upstream developments (RMSNorm backward optimization, AliasDb wildcard caching, MPS / ROCm series fixes, etc.), LLVM/MLIR progress (ClangIR, SLP, etc.), and RISC-V upstream/downstream items (excerpts in Section IV).
  • Site and blog: The official site added Chinese and English versions of “PyTorch RISC-V CI in Practice” (committed 10-07, live in the early hours of 10-08, #79); the contributor data file was routinely updated daily over the holiday (10 automated commits).
  • Scope note: Bulk commits from upstream forks (PyTorch main, LLVM main) are included after filtering by RISC-V keywords; general commits not included are not counted toward this stack’s progress.

III. RuyiSDK Toolchain and Distribution (ruyi Package Manager, packages-index, openRuyi)

openRuyi Distribution: 2026.09 Release Lands; Main Repo Merges Pause Over the Holiday, Queue Under Intensive Review

  • 2026.09 release (09-30): See “This Week’s Highlights” for details; the release announcement is the heaviest distribution-side event of this cycle.
  • Main repo cadence: No new merges in the main repo during the holiday (most recent merges were #1388 / #1389 the day before the break), with the commit side pausing over the holiday; the PR queue remains active — #1392 docker-cli (WIP), #1393 python-numba tests, #1394 spdk bdevperf, #1395 moby 29.8.1, #1398 go-github-chewxy-math32 RISC-V test fix, #1399 audit 4.2.1 enabling RISC-V support, #1401 metadata fix, #1402 AGENTS.md (guidance for AI coding agents), among others, were opened or reviewed in succession; #1379 OpenCL is also in the queue.
  • Adjacent components: rpm-spec / rpm-spec-tool (openruyi branch) and k1firmware made progress over the holiday; homepage #77 merged (09-30); the “lookout” package tracking service iterated at high frequency (~30 commits), upgraded to 0.2.0 on 10-07 — providing openRuyi with read-only tracking of RPM source versions, upstream releases, OBS builds, and maintenance evidence; TakoPack (a tool for packaging Rust/Python into RPM specs) opened a new Rust pipeline implementation PR #1 (10-07).
  • openRuyi-zero: No commits (most recent was the build script fix on 09-29).

ruyi Package Manager and Toolchain Adjacent

  • ruyi: Main repo silent (most recent commit 09-25); release channel remains 0.53.0 (same version on PyPI), next version previewed for late October 2026; public mirror sync and installation feedback remain post-holiday watch items.
  • packages-index: No commits (most recent 09-16); issue #227 “Question about mirror://” closed on 09-30.
  • ruyi-tuner: Three consecutive pushes to the v1.x branch on 09-30 — added run_csibe.py and real_compile.py scripts and documentation (full-package runs and data extraction for the CSiBE code-size benchmark), and changed extract_tuner_data.py to read CSiBE_Step3 summary data — completing the benchmark data pipeline for “project-level search.”
  • ruyi-backend: Merged pyjwt 2.15.0 dependency upgrade on 09-30 (#129); opened four dependency PRs from 10-05 to 10-06 (semver 3.1.0, SQLAlchemy 2.1.3, mypy 2.4.0, ruff 0.16.10).
  • IDE and desktop tools: VS Code extension #259 (fix for preserving case in search queries) merged on 09-30; #260 (package description tooltip) and #261 (@vscode/vsce bumped to 4.0.0) opened on 10-05 and are under review. ruyici (macOS build PR #13) remains open. ruyi-imager nightly build channel refreshed as usual (10-07).

Support Matrix, Documentation, and Website

  • support-matrix: New PR #409 “ESP32C6: add RT-Thread report for the official BSP” opened early on 10-07 and reviewed — continuing the cadence of RT-Thread reports for MCU boards; the pending queue #397 (RT-Thread Smart), #405 (Zephyr), #390 (VisionFive2_Lite) saw no updates over the holiday.
  • board-docs: New PR #50 (docs: bump ruyi version, opened 10-01, under review).
  • docs / website: No commits to docs; website ruyisdk-website automated data PR #593 merged (10-01), #594 opened (10-01), apiupdate branch advanced as usual on 10-06.

Kernel and Low-Level (linux-xuantie-kernel)

  • No new commits (most recent 09-23); issue #286 received on 10-05: “kendryte-hash: shared DMA buffer makes the SHA-256 driver unsafe for concurrent calls” — a concurrency-safety issue in the local kernel tree enters the queue.

IV. Vector Extensions and Operator Optimization (VecIntrinBench / IntrinTrans / FBGEMM)

  • All three target repos silent throughout: VecIntrinBench (last commit 02-13), IntrinTrans (06-25), FBGEMM fork (07-13); cpuinfo (05-20) and torq-tile (04-09) in the same group were likewise silent — no new benchmark data this cycle.
  • Substantive progress on adjacent workstreams: Code output in the matrix/vector direction concentrated in — LLVM A100 dot-product and pack/unpack lowering (#30–#32), GCC/Binutils Ztt draft support (ztt-dev), and AME-operator GEMM/GEMV kernels and verification (see This Week’s Highlights and Sections II and III).
  • Upstream and architecture-side observations (from daily intelligence, 09-30 to 10-08):
    • Dense merges in riscv-arch-test: vector floating-point test generation (#2349), pointer-masking extension (Ssnpm / Smmpm, etc.) test generation, fix to the criterion for treating vector EEW overlap as Agnostic (#2711), Sdtrig mcontrol6 coverage group (#2418), CHIPS Alliance VeeR EL2 core integrated into ACT (#2443), among others.
    • Sail 0.15 released (10-07): adds the Double Trap extension, partial Sdtrig support, and a basic event framework; also fixes virtualization semantics issues such as Sv32x4 PTE write-back and G-stage htval.
    • XiangShan DiffTest: added 128-bit hash completion records for AME matrix results (#978), providing a compact verification path for matrix-extension differential testing.
    • riscv-unified-db: incorporated Zvzip 0.3.0 (structured data interleave / deinterleave / pairwise transpose, a development version).
    • Board-level and model adaptation: SpacemiT K3 firmware supports a new device tree (FML13V05) and COM260 compatibility fixes; Sophgo sophon-demo adds deployment examples for models such as Qwen3 / Qwen2.5-VL on CV84X6.
    • CVA6: regression orchestration consolidated into cook.py and a unified dashboard (#3612), making the hardware verification flow replayable.

V. Community and Events (Biweekly Progress, Forum, Documentation)

Forum: New Course and Resource Posts; News Posts Paused Over the Holiday

  • “RISC-V Linux in Practice” Chapter 01 “Environment and Toolchain” (10-04, 10-06): Released in dual “lecture notes + lab” versions — the notes cover environment setup, RevyOS flashing, serial / SSH login, and the full cross-compilation CoreMark workflow; the lab sets three progressive tasks (on-board native probe, architecture pitfall demonstration, board bring-up channel acceptance); a companion course website went live simultaneously.
  • Resources and reposts (09-30): development board example repository resource post (#2875, aggregating entry points for Hello World / CoreMark / peripherals / multimedia and ROS 2 courses); open-source technology news roundup post (#2876); repost of ESWIN Computing’s Hong Kong IPO developments (#2878, expected listing on 10-09).
  • Cadence observation: the daily “Open-Source Technology News” post was paused over the holiday (last issue 09-30, #2876); the forum saw no new topics after 10-06 (as of the morning check on 10-08).

Biweekly Progress and External Materials

  • Biweekly Report No. 078 not yet published (as of the check, the latest is still No. 077; no holiday commits in the wechat-articles repo) — based on the holiday schedule, publication is expected after the break, listed as a watch item for next week.
  • Website blog expansion: “PyTorch RISC-V CI in Practice” added to the blog page (alongside “Triton’s RISC-V Port”), presented bilingually on a standalone page.

VI. Trend Observations

  • Divergence in holiday mode: “low merge output, but queues and intelligence never stop”: Across the three organizations, main-repo merges over the 8 days were few and far between (two for riscv-gcc, three for llvm-project, zero for openRuyi), yet PR reviews, branch refreshes, intelligence repos, and community channels ran throughout; in the early hours of the first post-holiday day (10-08), a full PyTorch rebuild and a new triton PR appeared — a recovery speed worth noting.
  • Systematic build-out of matrix extensions: LLVM-side A100 series merges, GCC/Binutils-side Ztt draft branch, operator-side AME-operator open-sourcing, and a fork of the official AME repo on the spec side — the matrix direction has shifted from scattered patches to parallel progress across “compiler–operator–spec–verification,” the most technically significant structural change this issue.
  • PyTorch RISC-V moving from “can compile” to “continuously verified”: the CI blog post, fork rebuilds, and SyncBots automated syncing together form a closed loop of “upstream tracking, on-hardware regression, issue feedback”; next, watch the review of the two RVV PRs (#46 / #48) and the onboarding of more hardware backends.
  • openRuyi’s “enterprise-grade software stack” narrative: the 2026.09 release brings the Cloudpods cloud platform, Ceph / SPDK storage, and GPG supply-chain signing into the mainline, layered with RVA23 fixes and container performance paths — the distribution’s target scenario is shifting from “it runs” to “production-ready.”
  • Continued instruction-level correctness fixes on the compiler side: BCLR codegen fix (backported to openRuyi GCC 16), P extension lowering, A100 and Ztt — the toolchain is gaining on both correctness of existing extensions and support for new ones.
  • Gaps and watch items: publication of Biweekly Report No. 078; the direction of the standard AME route after llvm-project #25 / #28 (FPGA) and the closure of #22; recovery of openRuyi main-repo merges and the 2026.10 release cadence; post-holiday continuity of ruyiai-daily; review of triton-riscv #85; merge cadence of support-matrix #409 and board-docs #50.

Appendix: Sources and Verification Notes

Sources (and Gaps)

  • 2026-09-30 daily report: window 09-29 04:30 to 09-30 04:30 (Wednesday issue, the last issue before the holiday).
  • 2026-10-01 to 10-07: National Day holiday, daily reports suspended, no sources (a planned suspension, not a missing issue).
  • Developments outside the cycle boundary (the portion between daytime 09-30 and the morning of 10-08 that the daily reports could not cover) were included after organizational verification and dual-source community reinforcement.

Verification Methods and Scope

  • Organizational verification (216-hour window): covers commits, PRs, and releases across three organizations — RuyiAI-Stack, ruyisdk, and openRuyi-Project (via both Atom and web channels, not reliant on API rate limits); upstream fork commits are filtered by RISC-V-related keywords.
  • Full scan of organizational event streams: locates non-default branch activity (ztt-dev, ame-experimental, lookout, rpm-spec, etc.) and newly created repositories (AME-operator, attached-matrix-extension fork).
  • Community dual-source: latest topics on the RuyiSDK developer community forum; the openRuyi distribution news page (2026.09 release announcement).
  • Intelligence repository: full-cycle file review of ruyiai-daily (9 issues).
  • Commit counts are based on the verification window; “daily”-type descriptions are converted from repository commit timestamps to Beijing time.

Main References

Data sources: daily RuyiAI activity reports (the 2026-09-30 issue) and National Day holiday reinforcement verification (organizational repositories, community dual-source, technical intelligence repository); the reporting period is 2026-09-30 to 2026-10-07.