Research window: 2026-10-22 04:30 ~ 2026-10-23 04:30 (Beijing time, past 24 hours), contiguous with the previous issue.

Sources: Full-repository verification across four GitHub organizations (commits, pull requests, and releases in RuyiAI-Stack, ruyisdk, openRuyi-Project, and buddy-compiler, with every item in the window re-checked; upstream forks filtered by RISC-V keywords, with unrelated upstream commits excluded), per-commit counts and author distribution for the main openRuyi repository, ruyi package manager release and PyPI version verification, the openRuyi distribution news page, the RuyiSDK developer community forum and biweekly report repository, three-page snapshots of the official RuyiAI homepage, upstream activity in IREE and riscv-arch-test, arXiv searches, and targeted Google News RSS queries in Chinese and English (via proxy).

This Issue’s Index

  • Today’s Focus: Biweekly Report 079 completes six sections; QEMU fills in full P extension v0.6 instruction coverage and merges DAMO AME v0.6 (10-22)
  • I. RuyiAI Stack Progress (PyTorch / Triton / TileLang RISC-V adaptation)
    • 1.1 pytorch: riscv branch replayed in full for the fourth consecutive day, head switched to 29259d90 (10-22)
    • 1.2 llvm-project: rebased for the second consecutive day, riscv branch advances to 58d62a47 (10-22)
    • 1.3 tilelang-riscv: no commits for six consecutive days (10-22 status)
    • 1.4 triton-riscv: nightly build stays at 10-19, PR #85 has no new activity (10-22 status)
  • II. RuyiSDK Toolchain and Distributions
    • 2.1 openRuyi main repo: 81 commits, Jingwiw sweeps 54 packages in one pass (10-22)
    • 2.2 openRuyi PRs: 22 merged, security update batch cleared, open queue at 77 (10-22)
    • 2.3 Biweekly Report 079 completes six sections: GCC extends Ztt and P 0.6, LLVM merges nine patches (10-22)
    • 2.4 QEMU: full P extension v0.6 instruction coverage, DAMO AME v0.6 merged (10-22)
    • 2.5 ruyi package manager: 0.53.0 maintained, 0.54.0 slated for end of October (10-22 status)
    • 2.6 packages-index: ISCAS source sync anomaly, no package updates this issue (10-22)
    • 2.7 Kernel and firmware line: edk2-ruyi, ruyifirmware silent (10-22 status)
  • III. Vector Extensions and Operator Optimization
    • 3.1 AME trio closes the loop: LLVM patches, QEMU emulation, AME-operator operator library (10-22)
    • 3.2 IREE: no RISC-V-specific commits in window, only LLVM baseline tracking (10-22)
    • 3.3 Paper: rearranging FlashAttention on long-vector processors, measured speedup of 1.84 to 2.08x (10-21)
    • 3.4 This stack’s vector repos and upstream validation line: VecIntrinBench, IntrinTrans, riscv-arch-test silent (10-22 status)
  • IV. Buddy Compiler Updates
    • 4.1 buddy-mlir: zero commits, zero releases in window (10-22 status)
    • 4.2 Downstream anchoring: triton-riscv nightly build still locked to 0.1.1.dev20261017 (10-22 status)
  • V. Community, Events, and Official Homepage
    • 5.1 Summit recap post published: two talks, six posters, seven live demos (10-22)
    • 5.2 RISC-V Linux Practice Course Session 02 lecture notes archived (10-22)
    • 5.3 ruyi-imager: nightly package now tracks 731e52b, adds image download action (10-22)
    • 5.4 Official homepage three pages unchanged, openRuyi website repo adds tag descriptions (10-22)
    • 5.5 External news and arXiv: targeted queries return zero hits, FlashAttention restructuring on long-vector processors (10-21)
  • VI. Trend Observations
    • 6.1 Replay shifts from “scheduled” to “daily”: llvm rebases on two consecutive days for the first time
    • 6.2 openRuyi enters a specification-completion phase: 54 sweeps outweigh 22 upgrades
    • 6.3 Distribution begins laying out desktop and virtualization validation stack
    • 6.4 Extension landing path takes shape: compilation, emulation, and operator layers arrive in sequence

Today’s Focus: Biweekly Report 079 completes six sections; QEMU fills in full P extension v0.6 instruction coverage and merges DAMO AME v0.6

Date: 2026-10-22　Sources: Biweekly Report Issue 079, QEMU p-dev branch, QEMU ame-0.6 branch, QEMU repo

The Issue 079 draft recorded in yesterday’s report only covered three sections—OpenJDK, the base C library, and development boards. In this window the remaining six sections were all completed: GCC, LLVM, V8, OpenJDK, Go, QEMU, plus the package manager and IDE subsections. Ten patch commits landed in the repo between 10-22 09:26 and 14:20 (#383 through #391).

The QEMU section carries the most information. The RuyiSDK QEMU repo released an implementation of P extension v0.6, claiming complete emulation support for all current P extension instructions, with the p-dev branch based on upstream v11.1.0. The branch’s last batch of commits landed at 10-21 16:35, covering the packed SIMD series (Q-format multiply-add, pure multiply and multiply-accumulate, two-way and four-way multiply-add/subtract, load-replicate, RV32-specific instructions), and removed P’s dependency on Zbkb to align with the spec, along with added TCG tests.

The same issue also records the merge of DAMO’s AME extension v0.6 into the ame-0.6 branch: major feature development and architectural refactoring completed, supporting 32/64-bit user mode and system mode, covering matrix computation, mixed integer and floating-point operations, data movement, and type conversion, with support for multi-core shared backends, state migration, and debugging, likewise based on upstream v11.1.0. Visible commits on this branch run through 10-16; this window compiles the results into the publication rather than representing new commits.

These two items correspond to the compiler side of RuyiAI: the AME patches on the LLVM branch—#29 (instruction updates), #30 (IME builtins lowered to SpacemiT A100 dot), #31/#32 (A100 HP/SP and pack/unpack scheduling)—handle compiling the matrix extension into instructions, while the QEMU side handles emulating the same semantics when no hardware is available. Support for the same extension across all three sites reached v0.6 simultaneously this week, meaning the extension now has a minimal closed loop of “compiler can generate, emulator can execute.” The remaining gap is real-hardware measurement data.

I. RuyiAI Stack Progress (PyTorch / Triton / TileLang RISC-V Adaptation)

1.1 pytorch: riscv branch fully replayed for the fourth consecutive day, head switched to 29259d90 (10-22)

Date: 2026-10-22　Sources: riscv branch commit list, new head 29259d90, head-to-head comparison of two rounds, PR list

The riscv branch completed its fourth full-branch rewrite at 03:00 on 10-22, with the head switched from 3c1ea315 to 29259d90 and the committer timestamps of all visible commits uniformly rewritten to the same instant. Comparison with the previous head shows diverged: 60 commits ahead, 24 behind, 106 files differing, with the entire diff surface falling within the upstream baseline range (MPS operators, Metal kernels, CI workflows, and pr_review scripts); no local patch files appear in the diff list.

The local patch series is unchanged item by item: the riscv64 local image (#51), the bytes_to_scalar floating-point fix (#44), the inductor opinfo blocklist (#50), the ULP tolerance restriction for linear cross entropy (#42), and the CI series (#20, #21, #40, #41). The seven open PRs (#23, #35, #36, #38, #43, #46, #48) had their update timestamps refreshed in the same batch at 08:25 on 10-22, with no new review comments and no merges. Among them, #46 “RISC-V Vector Extension support for ATen” and #48 “Add RISC-V Vector CPU capability” remain the two main proposals for upstreaming RVV capability.

1.2 llvm-project: rebased for the second consecutive day, riscv branch advances to 58d62a47 (10-22)

Date: 2026-10-22　Sources: riscv branch commit list, new head 58d62a47, head-to-head comparison of two rounds, PR #25, PR #28

The riscv branch, which had just completed a rebase yesterday after eight days of silence, was rebased again at 23:00 on 10-22, with the head changing from dd05e5b5 to 58d62a47 and the title still “[RISCV] Add A100 HP/SP and pack/unpack lowering with calibrated scheduling (#31)”. Comparison with the previous head: 275 commits ahead, 26 behind, 300 files differing — markedly smaller than yesterday’s 1769-commit span, indicating that this time the baseline was only nudged forward a small step.

The patch series is fully preserved and in unchanged order, from the BOSC AME extension (#16) to A100 HP/SP and pack/unpack scheduling (#31, #32), including the Buckyball vendor extension (#20), alignment with the Pebble core ISA (#23), the xtame design update (#27), and IME builtin lowering (#30). The two FPGA backend PRs (#25, #28) had their timestamps refreshed in the same batch at 00:57 on 10-23 and remain open. This is the second full-branch rewrite within two days, now converged with pytorch’s daily cadence.

1.3 tilelang-riscv: no commits for six consecutive days (10-22 status)

Date: 2026-10-22 (status)　Sources: commit list, PR #4 RVV mask and reduction

The last commit on the main branch remains the batch of five changes from 10-16 (code generation formatting conventions, upstream operator runtime semantics, TileOps runtime adaptation, Buddy MLIR release CI, in-CI Python extension build), with no new commits for six consecutive days since. Open PR #4 “Add RVV vector mask and max reduction lowering” was last updated on 09-28, and PR #2 on 06-16. The repo remains in a stalled phase where “the CI and runtime skeleton are working, operator coverage is still to be filled in”; there is no new evidence this period to change that assessment.

1.4 triton-riscv: nightly stays at the 10-19 build, no new activity on PR #85 (10-22 status)

Date: 2026-10-22 (status)　Sources: Releases, Nightly 2026-10-18-a305fb6, PR #85 softmax and matmul optimization

No commits and no new releases during the window; the latest nightly is still nightly/20261018-a305fb6, released on 10-19, pinning Buddy MLIR nightly 0.1.1.dev20261017. Open PR #85 was last updated at 07:55 on 10-19 (Beijing time) and remains the only active operator optimization proposal; the most recent activity on the other open PRs is concentrated in mid-to-late September, and the queue has been idle for a long time.

II. RuyiSDK Toolchain and Distributions

2.1 openRuyi main repo: 81 commits, Jingwiw sweeps 54 packages in one pass (10-22)

Date: 2026-10-22　Sources: commit list, checksum sweep example xmltoman, rdma-core 65.0 commit 3b13a2a5, opencv build directory fix 2829a38d

All 81 commits in the window carry the SPECS: prefix, from seven authors—Jingwiw 54, misaka00251 21, DingliZhang 2, and one each from sunyuechi, Leetfs, wzssyqa, and Z572. The commits span nine hourly blocks from 10-22 09:27 to 10-23 00:12, with a single batch of 55 pushed at 13:00.

All 54 of Jingwiw’s commits are the same change: “Add source checksums and use %autochangelog”, covering the alphabetical range from luksmeta to xmltoman—the entire m-to-x stretch. This kind of change adds source checksums to specs and moves changelog generation to %autochangelog; it is foundational distro normalization work that changes no package version or behavior.

The other 27 commits are substantive upgrades. The security batch is the most concentrated: go 1.27.3, php 8.5.12, nss 3.131.1, ca-certificates-mozilla 2.92, rustup 1.29.2, python-pip 26.2.2, nodejs 24.22.1, python 3.14.9, python-pillow 13.0.0, nginx 1.31.8, plus certifi, perl-Mozilla-CA, two webpki-roots commits, and rustls-webpki. On the Rust side, rustls-platform-verifier 0.7 and android 0.2, enum-map 3, quote 1.0.47, and proc-macro2 1.0.107 were added. The rest are openjdk-17 17.0.21.9, openjdk-21 21.0.13.9, libudev-zero 1.0.5, brotli 1.2.1, and rdma-core 65.0.

One small fix deserves separate mention: opencv replaced a hardcoded /home path with %{_builddir} (wzssyqa); such hardcoding is a common source of non-reproducible build environments.

2.2 openRuyi PRs: 22 merged, security update batch cleared, 77 open (10-22)

Date: 2026-10-22　Sources: PR list, PR #1498 python 3.14.9, PR #1502 openjdk-17, PR #1501 openjdk-25, PR #1500 openjdk-latest, PR #1490 cross toolchain, PR #1415 virglrenderer

22 PRs merged in the window. The nineteen security updates listed in yesterday’s report have essentially cleared the review queue: go, php, nss, ca-certificates-mozilla, rustup, python-pip, python-certifi, perl-Mozilla-CA, rustls-webpki, two webpki-roots PRs, nodejs, python-pillow, nginx, and python were merged in succession; the four openjdk versions landed in two batches, first 27.0.1.0.2.1, 25.0.5.8, 21.0.13.9, and 17.0.21.9 (#1493 through #1496), followed by 17 and 21 tagged [security-fixes] (#1502, #1503). The remaining merges are libudev-zero 1.0.5, the opencv build directory fix, brotli 1.2.1, rdma-core 65.0, the second batch of metadata and source declaration corrections (#1403), and a README typo fix.

The open queue still holds 77 PRs. Notable ones: the security-tagged openjdk-latest and openjdk-25 versions (#1500, #1501), postgresql disabling the systemd startup timeout (#1504), alibabacloud-go-tea 1.5.3 (#1505), and the first batch of metadata corrections (#1401).

A cluster of desktop and virtualization proposals is also taking shape: qemu enabling GUI test features (#1421), adding virglrenderer (#1415), ovmf adding fwupd (#1436), adding ydotool (#1457), fixing a xorriso man page conflict (#1489); plus a WIP cross riscv64 toolchain (#1490) aimed at producing a riscv64 toolchain directly on an x86 host.

2.3 Biweekly 079 fills in six sections: GCC extends Ztt and P 0.6, LLVM merges nine (10-22)

Date: 2026-10-22　Sources: Biweekly issue 079, GCC Ztt Md commit 368ab1b0, GCC P 0.6 commit 883d7da2, RVA23.1 non-experimental PR #234064

Of the six completed sections, five cover base components. GCC has three: rebasing Zvdota/Zvbdota support and fixing issues found during the rebase (patches sent to patchwork), adding Md support for the Ztt extension, and updating P extension support to version 0.6.

LLVM lists twelve commits, nine merged, falling into four groups: RVA23.1 and RVB23.1 profiles promoted to non-experimental (#234064), GlobalISel handling f16 truncation with Zfhmin plus half-precision legalization (#231370), LLT overloading for unaligned scalar accesses so memcpy can expand with wider instructions (#232183), and P extension intrinsics for mulq, multiply-high accumulate, sati/usati, Packed Pair, and packed multiply (#232316, #232340, #233769, #232202, #232612), plus an RV64 constraint fix for __builtin_riscv_rev16_64 (#232362). Two remain under review: an InstCombine improvement inferring addend ranges from sum ranges (#231357), and TableGen-generated vector library call selection with a RISC-V SLEEF selection fix (#231739).

V8 merged four: binary-search switch inputs always sign-extended on riscv64, Sandbox trusted pointer table entries marked, Liftoff tracing f32 and 32-bit f64 constants (ported from upstream), and a maximum parameter count check added to the interpreter entry trampoline. On the Go side, six mainline CLs were proposed, of which two enabling sha256 and sha512 zvknha/zvknhb hardware acceleration on riscv64 have merged; the rest are removing redundant MOVDnop, optimizing bit tests with register shift values, Zfa assembly support, and routing riscv_hwprobe through vDSO. The twelve OpenJDK commits and JEP 544 RISC-V port progress were covered in yesterday’s report; this issue only finalizes them for publication.

Three sections of the issue remain blank: the opening remarks, version testing and outstanding issues, and the website and documentation.

2.4 QEMU: full P extension v0.6 instruction coverage, DAMO AME v0.6 merged (10-22)

Date: 2026-10-22　Sources: Biweekly QEMU section, p-dev branch, ame-0.6 branch, qemu commit list

On the P extension side, the final batch on the p-dev branch focuses entirely on packed SIMD: Q-format multiply and Q-format multiply-add, plain multiply, multiply-accumulate, two-way and four-way multiply-add/subtract, load-and-replicate, and RV32-only instructions, plus removal of P’s dependency on Zbkb to align with the new spec version, and P extension tests under tests/tcg/riscv. The branch is based on upstream v11.1.0.

On the AME side, the v0.6 implementation contributed by DAMO was merged into the ame-0.6 branch; the official description states that major feature development and architectural refactoring are complete, with support for 32/64-bit user mode and system mode, covering matrix computation, mixed integer and floating-point operations, data movement and type conversion, multi-core shared backends, state migration, and debugging. Visible commits on the branch run through 10-16 and cover Ztt instruction family work: decodetree decoding, instruction family helpers, GDB state exposure, experimental CPU configuration exposure, disas support, and four test groups for Ztt numeric/tensor operations, control and shared backends, memory and debugger integration, and configuration and migration, plus documentation.

Both lines converge on the same goal: turning not-yet-shipping extensions into a working software baseline. For developers without P extension or AME hardware, QEMU is the only way to validate toolchain output; only with full P extension instruction coverage do GCC’s P 0.6 update and LLVM’s P extension intrinsics have execution semantics to check against.

2.5 ruyi package manager: 0.53.0 holds, 0.54.0 slated for late October (10-22 status)

Date: 2026-10-22 (status)　Sources: ruyi Releases, PyPI ruyi, Biweekly 079 package manager section

GitHub Release and PyPI both remain at 0.53.0 (released 09-24), and the last commit on main is from 09-25; no new version or commits in the window. Issue 079 states that 0.54.0 is expected to ship in late October due to a release cycle adjustment, and notes that most of the development and testing team was in Shenzhen last week for the RISC-V China Summit, slowing this cycle’s pace.

Three in-development items are unchanged: ABI compatibility checks between packages and the current system, macOS packaging for more officially maintained packages, and toolchain adaptation for SpacemiT K1/K3. A software source maintenance commitment is also given: ruyi update content is compatible with the last three official releases.

2.6 packages-index: ISCAS source sync issue, no package updates this cycle (10-22)

Date: 2026-10-22　Sources: packages-index commit list, Biweekly 079 resource update section

The repo’s last commit remains 10-13 (adding the ubuntu-old-releases mirror, fixing the ubuntu version for Sifive Unmatched). Issue 079 explains the silence: over the past two weeks the ISCAS software source has had data synchronization problems, and built packages have not been refreshed to the public network, so there are no package updates.

This explains the combined pattern over the past two weeks—”no new package manager version, no new packages in the index”—which reflects a blocked release channel rather than stalled development. The direct user impact is that installing packages via ruyi still shows the old set; this is a server-side issue and requires no local troubleshooting.

2.7 Kernel and firmware lines: edk2-ruyi, ruyifirmware quiet (10-22 status)

Date: 2026-10-22 (status)　Sources: linux-xuantie-kernel commit list, edk2-ruyi commit list, ruyifirmware Releases

The kernel line linux-xuantie-kernel (linux-6.6.36 branch) last committed on 10-16 with the cpufeature and hwprobe change batch; the firmware line ruyifirmware’s latest release is still “Ruyi Firmware 20261015” from 10-15; edk2-ruyi is stopped at the 10-15 K3 system information page. All three lines have been quiet for a seventh consecutive day; in this window the openRuyi organization’s activity is entirely on the package and documentation sides (see 2.1 and 5.4).

III. Vector Extensions and Operator Optimization

3.1 The AME Three-Piece Loop Closes: LLVM Patches, QEMU Emulation, AME-operator Library (10-22)

Date: 2026-10-22　Sources: LLVM AME instruction update #29, IME to A100 dot #30, A100 HP/SP and scheduling #31, AME-operator, qemu ame-0.6

Viewed side by side, these three efforts show that the AME extension’s software stack has taken shape. On the compiler side, the RuyiAI LLVM branch proceeds in three steps: first the extension and backend path design (#16, #24, #27), then landing the AME instruction set update (#29), and finally lowering the IME builtins to SpacemiT A100 dot instructions and completing HP/SP and pack/unpack lowering and scheduling calibration (#30, #31, #32). On the emulation side, the QEMU ame-0.6 branch covers matrix computation, mixed precision, data movement and type conversion, and supports state migration and debugging. On the operator side, ruyisdk/AME-operator pushed in one go on September 30: GEMM and GEMV kernels, a portable operator reference and validation suite, and build and validation workflow documentation.

The common gap across all three layers is real-hardware measurement: the compiler-side performance model is calibrated against A100 instructions, QEMU only guarantees semantic correctness, and the operator library’s validation suite runs on emulation or existing hardware—no layer provides real-silicon throughput data. Until A100 or later hardware is available, what this stack can prove is “it compiles, it runs, the results are correct”—not “it’s faster.”

3.2 IREE: No RISC-V-Specific Commits in Window, Only LLVM Baseline Tracking (10-22)

Date: 2026-10-22　Sources: IREE commit list, LLVM integration #25103, VM ISA validation commit 9ea0d950

Two commits in the window: one integrates upstream LLVM to bdd8381f5b7e (#25103); the other, on the VM side, wires up the ISA decoder’s validation macros and tightens register validation (9ea0d950). The latter concerns validation in IREE’s own bytecode virtual machine and is unrelated to RISC-V.

In other words, after yesterday’s report on landing RVV f16 vfmacc/vfwmacc, IREE had no new RISC-V-specific commits in this window. The version line had already advanced to 3.14 (the version bump commit on 10-20); what’s worth watching next is when the blocking and threading improvements to the f16 path under tracking item #24932 appear.

3.3 Paper: Restructuring FlashAttention on Long-Vector Processors Yields 1.84–2.08× Measured Speedup (10-21)

Date: 2026-10-21 (slightly before this window’s start; included because the arXiv index first made it visible within this window)　Source: arXiv 2610.29489v1

“Reorienting the Vector Axis: Restructuring FlashAttention for Long-Vector Processors” (Emmanuel Irabor, Marc Casas) ports PyTorch’s CPU FlashAttention kernel to a RISC-V CPU with 2KB vector registers, and starts with a blunt baseline: only 16.2% of peak floating-point throughput.

The cause analysis is specific. The original kernel advances query row by row: the multiply with V is vectorized along the 64-element head dimension; softmax’s per-row max and sum are reductions that “collapse an entire register into a scalar”; and the polynomial coefficients of the software exponential function compete with tile data for vector registers, causing spills to the stack. Together, these three keep vector register utilization low.

Neither fix changes the algorithm or the numerics. The first transposes the score tile together with the running output so that queries fall on a linear contiguous axis—so a single parameter, “how many queries fit in a tile,” uniformly determines the vector length of every kernel section, configurable per machine, and the two reductions disappear naturally. The second moves the polynomial coefficients into scalar registers, eliminating spills and cutting softmax’s vector memory instructions by 78.7%.

Measured results: at head dimension 64, the two changes together bring the full-kernel cycle count down to a 1.84–2.08× speedup, raising floating-point utilization from 16.2% to 29.7%; an FPGA with the same design ranks the two changes consistently and benefits more, reaching 2.71×.

The significance for this stack lies in the method, not the numbers: vector-length adaptation and register pressure are the structural problems in triton-riscv’s and tilelang-riscv’s RVV lowering—not “whether intrinsics exist.” The paper’s “match queries per tile to the machine” and IREE’s choice of vlen/8 for Tile N are the same class of decision and can be compared directly on equal terms.

3.4 This Stack’s Vector Repos and Upstream Validation Lines: VecIntrinBench, IntrinTrans, riscv-arch-test Quiet (10-22 status)

Date: 2026-10-22 (status)　Sources: VecIntrinBench, IntrinTrans, riscv-arch-test commit list, XiangShan commit list

This stack’s vector benchmarks and translation toolchain remain static: VecIntrinBench stopped at 02-13, IntrinTrans at 06-25, the FBGEMM fork at 07-13, cpuinfo at 05-20, harness at 10-10, and torq-tile at 04-09, with no commits in the window. The upstream validation lines are equally inactive: riscv-arch-test’s latest commit stopped at 09-08 (ACT 4.1 release notes and workflow fixes), and the main XiangShan repo also had no commits in the window within the scope of this topic’s checks.

IV. Buddy Compiler Updates

4.1 buddy-mlir: Zero Commits, Zero Releases in Window (10-22 status)

Date: 2026-10-22 (status)　Sources: Commit list, Releases

The main branch’s last commit remains 10-16’s “[ci] Add the publish-models workflow (#925)”; 0 commits and 0 releases in the window. The version line holds at the combination of the official BUDDY MLIR 0.1.1 (released 10-18) plus the last nightly 0.1.1.dev20261017, with no new nightly builds for five consecutive days since. After the two official releases from 0.1.0 to 0.1.1 two days apart, things fell into a lull that has now lasted four reporting periods; the batch of RISC-V usability changes from 10-13 to 10-16 (Makefile targets, cross-compilation to dev boards, CI switching to the Ruyi package index, running the Qwen3-VL-30B-A3B decoder on the SpacemiT platform) marked the end of a phase.

4.2 Downstream Anchoring: triton-riscv Nightly Builds Still Locked to 0.1.1.dev20261017 (10-22 status)

Date: 2026-10-22 (status)　Sources: triton-riscv commit list, buddy-mlir nightly 0.1.1.dev20261017

triton-riscv’s main branch’s last commit remains 10-18’s PR #88, which anchors the downstream dependency to buddy-mlir’s 10-17 nightly (0.1.1.dev20261017). Since buddy-mlir has had no new nightly since 10-17, triton-riscv’s nightly builds lack a new upstream to follow, and the two sides continue to wait on each other. Restoring daily artifact output on this chain depends on when buddy-mlir restarts its nightly workflow.

V. Community, Events, and Official Homepage

5.1 Summit retrospective post published: two talks, six posters, seven live demos (10-22)

Date: 2026-10-22　Source: Forum post #2893, Ruyi package manager poster

The forum published a retrospective post on the 6th RISC-V China Summit at 11:31 on 10-22. Scale figures given in the post: over 3,600 in-person professional attendees, 10 RuyiSDK team members on site, in the form of two technical talks, six technical posters, and a standalone D15 booth.

The two talks were “RISC-V Course Porting Methods and RuyiSDK Ecosystem Building” (Luo Yunxiang) and “Mastering the RISC-V Vector Extension: Practical Go Optimization on RVV” (Meng Zhuo, Zhu Junxian). The former proposed three main threads—”open the door, pave the road, teach the people”—with the approach of running simulation and visualization on the host or in the cloud while pushing drivers and inference down to the board. The latter focused on the engineering problems of connecting managed-language runtimes to RVV, including vector-length agnosticism, assembly stubs, and inlining optimization.

The six posters concentrated their information in numbers. The package manager’s metadata index contains over 328 software packages and over 265 system images, covering 41 development boards; it has been published to PyPI and integrated into the RevyOS and Bianbu repositories. Others covered RuyiTuner (genetic-algorithm search for compiler optimization sequences), AI-driven graphical IDE testing, using Sail plus Pydrofoil to interface with XiangShan difftest (about 800 lines of adaptation layer replacing NEMU), the Sail-RISCV-WASM toolchain running in browser WebWorkers, and the RISC-V course rebuild (821 videos, 1.441 million plays, 26,000 followers).

The most convincing of the seven live demos was the OpenCV RVV acceleration comparison: on the same hardware platform, comparing the ruyi-installed version against the distribution’s bundled OpenCV, operators such as image filtering and feature extraction achieved 3x to 8x speedups. This data point turns “how much benefit the vector library layer can deliver” from an estimate into a reproducible on-site measurement. In addition, the “Xindong Challenge” used the RuyiSDK IDE combined with CyberCAM and the K230’s onboard KPU for interactive gesture recognition, and four developers established cooperation communication channels on site.

5.2 RISC-V Linux Practice Course Episode 02 handout added to repository (10-22)

Date: 2026-10-22　Source: Forum post #2894

The forum added “RISC-V Linux Practice Course 02 Just-Enough C Language Basics [Handout]” the same day, published at 20:58, with the same author as Episode 01. The content is a minimal C language subset for embedded scenarios, covering types and variables, control flow, pointers, arrays, structs, storage duration, strings, and bitwise operations, with a running example of fan control and temperature reading, and it flags common pitfalls such as “integer division truncates toward fixed point” and “use const to state the meaning of constants.”

Together with the Episode 01 handout on environment and toolchain, this course now has two consecutive self-study installments, aligned with the course porting talk in 5.1: first explain thoroughly the parts reproducible on the host, then push the hardware-related parts down to the board.

5.3 ruyi-imager: nightly package now tracks 731e52b, adds image download action (10-22)

Date: 2026-10-22　Source: Commit list, Nightly build channel, Image download action commit 3ca6f445

Yesterday’s report noted that the nightly build had not followed the three Gradle changes from 10-21; this window provides the follow-up: the nightly channel has been rebuilt (packaged 10-21 21:31, built 10-22 05:38, source commit 731e52b, i.e., the TOMLJ upgrade commit), indicating that the automated build did subsequently trigger, just with a lag of about seven hours.

However, the three commits from 10-22 are not yet in the package: 15:33 moved activity progress to a fixed status bar and separated update errors, 15:40 aligned settings controls and condensed update feedback, and 20:42 merged PR #12 (providing the download action directly in the image selection step, saving one navigation). There is still a one-build-cycle gap between the nightly package and this batch of commits.

5.4 Official homepage’s three pages unchanged; openRuyi homepage repo adds tag description (10-22)

Date: 2026-10-22 (status)　Source: RuyiAI official homepage, Blog, Docs, openRuyi homepage repo commits

The three-page snapshot is identical to the previous issue: index.html indexes 3 items, blog.html indexes 2 posts (Triton’s RISC-V adaptation, PyTorch RISC-V CI practices), and docs.html indexes 23 chapters; the sha256 of all three pages is unchanged, with no new blog posts and no new documentation chapters this round.

The openRuyi homepage repo had one commit in the window (10-22 21:35, misaka00251): “docs: Add experimental tag and change tags description.”, adding an experimental tag to the docs and adjusting the tag description. This is consistent with the openRuyi main repo marking some packages as experimental, indicating that the distribution is turning “experimental” from an internal convention into a publicly visible classification.

5.5 External news and arXiv: targeted queries return zero hits; long-vector processor FlashAttention refactor (10-21)

Date: 2026-10-22　Source: Google News RSS, arXiv RISC-V search

Google News targeted queries for RuyiSDK and RuyiAI in Chinese and English returned zero hits in the window; the openRuyi query returned only one old piece from April; “如意 RISC-V”-type queries returned 25 items, the most recent being a summit preview from 10-13, unrelated to the distribution’s actions this issue. The bare query channel worked normally, indicating that there was genuinely no media coverage on the content side, not a proxy or parsing problem.

On the arXiv side, one directly relevant preprint appeared in the window (10-21), porting PyTorch’s CPU FlashAttention kernel to a RISC-V CPU with 2KB vector registers and providing measured speedups; see 3.3 for details.

VI. Trend Watch

6.1 Replay moves from “scheduled” to “daily”: llvm rebases two days in a row for the first time

Our read in the previous two issues was that pytorch rebases daily while llvm rebases on a schedule: pytorch had rewritten at 03:00 three times in a row, while llvm had rebased only once after eight quiet days. This window overturns the second half of that judgment—llvm rewrote the entire branch again at 23:00 on 10-22, exactly one day later.

The difference in span between the two rebases explains the mechanism: yesterday’s rebase, ahead 1769 and 300 files, was a concentrated catch-up on eight days of upstream backlog; today’s, ahead 275 and still 300 files, is routine catch-up on a single day’s increment. The branch has entered a state of “moving the baseline forward a small step each day,” converging on the same operational model as pytorch.

The cost is unchanged: committer timestamps are uniformly rewritten, SHAs expire daily, and any downstream that references these branches by SHA goes stale that same day—so these two branches should be read by their set of patch titles, not by SHA. The benefit is also unchanged: no new patches were added; all seven open PRs in pytorch and two in llvm only refreshed their timestamps, and actual progress is still determined by the review queue.

6.2 openRuyi enters a spec-completion phase: 54 cleanup commits outweigh 22 upgrades

Of the 81 commits in this window, 54 are the same kind of normalization change (adding source checksums, switching to %autochangelog), covering a run of package names from m to x; actual version upgrades number 22, a ratio of 2.5 to 1.

This differs from the previous phase of “filling in the dependency closure”: back then, Go dropped vendoring and Rust added crates, with the goal of making packages build at all; what is being cleaned up now is auditability and automated bookkeeping—source checksums make build inputs verifiable, and %autochangelog makes changelogs generated from commit history rather than written by hand. The user-perceivable benefit lands on the security-update path: only once a unified path works will CVE fixes propagate along a single route. The ISAC source-sync problem (see 2.6) is a reminder of the other side—however good the specs, users still see no updates when the release channel is blocked.

6.3 The distro begins laying down a desktop and virtualization validation stack

A group of proposals pointing the same direction has appeared in the open PR queue: qemu enabling GUI test features (#1421), adding virglrenderer (#1415), ovmf supporting fwupd (#1436), adding ydotool (#1457), and fixing a man-page conflict in xorriso (#1489).

The five items belong to virtualization, graphics virtualization, firmware update, input automation, and the optical-disc image toolchain; together they point to one thing: running a full desktop on RISC-V and validating it automatically. This is the other end of the same requirement as the “AI-driven IDE graphical testing” shown at the summit—for a test framework to drive a real interface, it first needs scriptable input and a virtualizable graphics stack. Desktop support was previously a weak spot for RISC-V distributions; this batch of proposals breaks it into tasks that can be merged one by one.

6.4 The extension landing path takes shape: compilation, simulation, and operators arrive in sequence

Taking AME as an example, a complete path from proposal to usability is visible this week: first the backend design and instruction-set definitions (LLVM #16, #24, #27, #29), then the lowering and scheduling implementation (#30, #31, #32), while the simulator provides executable semantics (QEMU ame-0.6), and finally the operator library provides testable kernels and a validation suite (AME-operator).

The P extension follows the same path but is already past the halfway point: QEMU covers all instructions, GCC support is updated to 0.6, and on the LLVM side intrinsics such as mulq, multiply-high accumulate, sati/usati, and Packed Pair are being merged upstream in batches. By comparison, the P extension lacks application-side benchmarks, and AME lacks real hardware.

This order is itself worth recording as a method: without a simulator you cannot validate the compiler, and without an operator library you cannot validate the simulator. Before all three are in place, talking about performance is meaningless; once they are, the bottleneck shifts to hardware and real measurements. This week’s progress is “complete,” not “faster.”

Source Verification Table

Source Verification result
RuyiAI-Stack org (all repos) pytorch: the riscv branch underwent its fourth full-branch replay (head 3c1ea315 replaced by 29259d90, compare ahead 60/behind 24, 106 files), and seven open PRs were refreshed together at 10-22 08:25; llvm-project: the riscv branch rebased for the second consecutive day (head dd05e5b5 replaced by 58d62a47, ahead 275/behind 26, 300 files), and two FPGA PRs were refreshed at 10-23 00:57; triton-riscv and tilelang-riscv had zero commits and zero releases; the latest ruyiai-daily issue is 10-22; harness, FBGEMM, cpuinfo, VecIntrinBench, IntrinTrans, torq-tile, and pytorch-ci had no commits in the window
ruyisdk org (all repos) ruyi-imager: 3 commits (two status-bar and settings-UI reworks, one image-download action PR #12), nightly package rebuilt (source commit 731e52b, built 10-22 05:38); wechat-articles: 9 commits (biweekly 079 finalized; GCC/LLVM/V8/Go/QEMU/IDE updates); ruyi: 0 commits, 0 releases (0.53.0 maintained); packages-index, support-matrix, ruyi-tuner, ruyisdk-vscode-extension, ruyici, AME-operator, and linux-xuantie-kernel had no commits in the window; the riscv-gcc default branch is stuck at 06-24 (the commits described in the biweekly are on other branches); the qemu p-dev and ame-0.6 branches had no new commits in the window (their final batches were 10-21 and 10-16 respectively)
openRuyi-Project org (all repos) openRuyi main repo: 81 commits (Jingwiw 54, misaka00251 21, DingliZhang 2, four others 1 each; 54 checksum cleanups, 22 version upgrades, 15 security-fixes) + 22 PRs merged + 77 open; homepage: 1 commit (documentation of the experimental label); ruyifirmware, edk2-ruyi, coreboot, linux, kiwi-image, and TakoPack had no commits in the window
buddy-compiler org buddy-mlir main branch: 0 commits, 0 releases; latest stable 0.1.1 (10-18), latest nightly 0.1.1.dev20261017 (10-17)
RuyiSDK community forum Two new threads: #2893 summit recap (10-22 11:31), #2894 hands-on course session 02 handout (10-22 20:58); biweekly 079 has not yet been posted to the forum, which still shows 078 as the latest
openRuyi distro news page No new articles; the 2026.09 release announcement remains the latest; /zh-Hans/news/2026-10/release and /2026-10/ both return 404, and the 2026.10 release has not yet shipped
ruyi package manager / PyPI 0.53.0 remains the latest (released 09-24); no new version and no new commits in the window; 0.54.0 is slated for late October
Official homepage (ruyiai.org) No changes across the three pages: 3 items on the homepage index, 2 blog posts, 23 documentation chapters; sha256 matches the previous issue
IREE upstream 2 commits in the window (LLVM integration #25103, VM ISA validation); no RISC-V-specific changes; the RVV f16 path landed yesterday has no follow-up commits
riscv-arch-test / XiangShan riscv-arch-test’s latest commit is stuck at 09-08 (ACT 4.1 release notes); no commits in the window within the scope of this check
arXiv (RISC-V) 1 new directly relevant preprint (10-21): porting PyTorch’s CPU FlashAttention kernel to a RISC-V CPU with 2KB vector registers, measured at 1.84x to 2.08x speedup; the rest are latest as of 10-20
Google News RSS (multiple Chinese and English queries) RuyiSDK / RuyiAI: zero hits; openRuyi: only one old April article; 25 Ruyi-type queries all returned old articles, the most recent being the 10-13 summit preview

Full Source List