Reporting period: October 19 (Monday) to October 23 (Friday), 2026 — 5 working days, source material from 5 daily briefings. The 10-19 issue used a 72-hour window (covering 10-16 through 10-19, continuing from the previous briefing’s cutoff); the other four issues used 24-hour windows. A small number of items therefore carry dates falling on 10-16 to 10-18, which is normal coverage for that issue.

Sources: Daily RISC-V Global Briefings (10-19, 10-20, 10-21, 10-22, 10-23); plus a 168-hour window review of followed GitHub organizations and key repositories (with Atom fallback), dual-source verification for openRuyi (main repo commits and the official news page), a sweep of RISC-V International member websites (391 members) and supplementary checks of the riscv.org blog; commits and releases after 10-23 05:00 were additionally cross-checked item by item against Atom feeds and official pages.

Editorial note: Core items from the five daily briefings are aggregated along four dimensions — “ISA and Architecture Ecosystem / Operating Systems and Distributions / Chips and Hardware / Community and Industry Events” — with cross-day developments on the same thread merged into a single narrative while retaining original dates. Facts, version numbers and dates are taken from verified sources in the relevant issue or from this cycle’s hands-on verification; single-outlet claims and vendor statements are flagged in the text. The week’s main thread was the 6th RISC-V China Summit (10-18 to 10-20 in Shenzhen, with a Hong Kong day on 10-21); the summit was both the peak in news density and the original source for most of this week’s product and roadmap information.

I. Weekly Highlights

  • The 6th RISC-V China Summit took place in Shenzhen, with a three-day main program plus a Hong Kong Day forming the year’s largest industry gathering (10-18 to 10-21): The summit opened on October 18 at the Shenzhen Convention & Exhibition Center (Futian) and ran for three days through October 20. Organizers expected more than 3,600 on-site professional attendees and over 450 exhibitors and research institutions; 10-19 featured the opening ceremony and main forum, 10-20 featured seven parallel sub-forums (AI, data center and HPC, software ecosystem, embedded IoT and smart hardware, chip design and verification, industry-academia collaboration and entrepreneurship, and automotive electronics and robotics), and 10-21 was Hong Kong Day (Room ICP B-101, City University of Hong Kong, 9:00 to 17:10). Main forum speakers included RISC-V International CEO Andrea Gallo, Turing Award laureate David Patterson, Chief Architect Krste Asanović, DAMO Academy’s Meng Jianyi, SpacemiT’s Chen Zhijian, ESWIN’s He Ning, and BlueCore Computing’s Jia Xinxia. Sources: Summit official agenda, NetEase (10-18)

  • SpacemiT and XiangShan unveiled the server-class CPU V100, billed as the industry’s first chip fully compliant with RISC-V server specifications (10-19): V100 implements server specifications across three layers—silicon, firmware, and operating system—covering five specifications: RVA23, server SoC, server platform, BRS (Boot and Runtime Services), and security model. It passes all BRS specification tests and supports direct installation, boot, and operation of mainstream distributions including openEuler, openRuyi, openKylin, Debian, Ubuntu, Fedora, Red Hat, and Rocky. The microarchitecture is a 46-core hybrid design—6 XiangShan Kunminghu V2R2 cores + 40 in-house X100 cores—clocked up to 2.4 GHz, with dual-socket coherent interconnect scaling to 92 cores; a single chip provides 8-channel DDR5-4800 and 52 PCIe 5.0 lanes. Overseas media report 12nm and 120 W TDP, with support for UEFI/ACPI/SMBIOS. It supports the H extension, AIA, and IOMMU, and its virtualization extensions already have native upstream Linux support. The company also launched the C2201 compute server, G5201 AI server, and S5236 storage server; the G5201 has been validated with the Kunlunxin M100 accelerator card and supports RDMA networking. Sources: Phoronix, EETrend

  • DAMO XuanTie: cumulative shipments exceed 6 billion units; dual-ASIL automotive IP E908A launched; autonomous driving and embodied intelligence roadmaps unveiled for the first time (10-19 to 10-20): Chief Scientist Meng Jianyi disclosed that XuanTie chips have achieved cumulative stable shipments of over 6 billion units (first surpassing 4 billion in 2024). At the same event, the company launched the automotive-enhanced processor E908A: officially described as the first RISC-V CPU IP to simultaneously meet ASIL-B and ASIL-D standards, with a single-point fault metric (SPFM) exceeding 90% for the first time in the industry, targeting safety islands, domain controllers, and automotive gateways. The next day, the automotive roadmap was announced: following E908A, C925A, C930A, and C950A will launch successively, with C950A targeting 5x the overall performance of first-generation automotive products; on the server side, C950 works with XT-LINK multi-core interconnect and achieves the first deep adaptation of RISC-V to server-side Java (30% performance improvement). Ecosystem data: DAMO ranks second worldwide in GCC community RISC-V contributions (delivering over 10% typical performance gains); more than half of RISC-V code in the OpenJDK community comes from DAMO; and 2,796 test cases have been open-sourced at RISC-V International. In collaboration with the Beijing Institute of Open Source Chip (BOSC) and ZTE Microelectronics, spatial multithreading (SMT) delivers a 30% dual-thread performance gain, and the company is working with more than 20 organizations on software adaptation for the AME matrix extension. Sources: East Money (Shanghai Securities News), Sina Tech (Fast Technology)

  • Qualcomm acquired RISC-V server IP company Akeana, its second server IP team in ten months (10-21): Akeana founder and CEO Rabin Sugumar confirmed that its IP and team “have become part of Qualcomm,” with Sugumar serving as Qualcomm Vice President of Engineering. Founded in 2021, Akeana’s core team came from Marvell/Cavium’s ThunderX server processor team; it emerged from stealth in August 2024 and disclosed more than $100 million in funding. Its IP spans the Akeana 100/1000/5000 tiers and includes an AI matrix compute engine plus system IP for security, debug, RAS, and telemetry; a 4nm server chip co-developed with Samsung Foundry completed design of the Alpine test chip in December 2025. Qualcomm previously acquired Ventana Micro Systems in December 2025 and completed its $2.4 billion acquisition of Alphawave. Deal terms and product integration plans were not disclosed. Sources: Dealroom, Sammy Fans

  • Tenstorrent rejected a sale and closed a $1.5 billion Series E at a $6.2 billion post-money valuation (10-19): The round was co-led by newly formed Trace Capital and Innovation X, with participation from Fidelity, T. Rowe Price, Morgan Stanley, Sandisk, Tether Investments, Cadence Ventures, ARK Invest, and others. The valuation more than doubled from roughly $2.6 billion in 2024, making it one of the largest Series E rounds for a U.S. semiconductor company. Proceeds will fund volume production and global commercialization expansion, scaling deployment of the Galaxy server. The outcome contrasts with reports two days earlier that “Intel and Qualcomm were simultaneously in acquisition talks”—media say the company chose to reject a sale and raise independently. Sources: Tenstorrent press release, Quartz

  • BlueCore Computing launched an intelligent-computing-integrated super node, taking RISC-V AI compute from single chips to clusters (announced 10-19, reported 10-20): The core chip LX500 integrates 48 RISC-V cores (32 performance cores + 16 efficiency cores) and an AI Vector/Matrix compute engine, delivering 75 TOPS INT8 of AI compute, supporting multiple precisions from INT4 to FP32, sharing DDR5, and supporting CXL expansion. Product timeline: powered on in February 2026, publicly unveiled in April, all-in-one prototype in May, the Lenovo Wentian WR5219 G5 server in July, and sampling plus small-batch deployment with industry customers from August—forming a four-tier matrix of the LX500 chip, WR5219 G5 server, LX5000 intelligent-computing-integrated all-in-one, and intelligent-computing-integrated super node. It has been adapted for Qwen, DeepSeek, and Kimi, with deployments targeting enterprise knowledge-base RAG, Agent office assistants, financial compliance inference, and industrial on-site inspection. In the same week, Ruixin Gaoguang’s D35 (128 GB memory, chiplet packaging, able to run 35B models locally, RISC-V + dataflow architecture) and Zhongke Tongliang’s full-stack product line (12-core AI workstation, video encoding all-in-one, intelligent-computing accelerator card) also appeared. Sources: Economic Information Daily, Shanghai Securities News (Ruixin), CSDN (Zhongke Tongliang)

  • RISE released the first open-source Android 17 build based on RVA23, giving RVA23 its first reproducible baseline for a mobile OS (10-20): Project number RP024, led and funded by RISE, with member organizations SpacemiT and Alibaba DAMO Academy providing platform expertise and hardware, BayLibre handling engineering implementation, built on the SpacemiT K1 Android port, and supporting the SpacemiT K3 Pico-ITX and Alibaba A210 EVB boards. The release includes binary images, a version-locked source manifest, checksums, flashing tools, and rebuild instructions; it uses an open-source boot chain of U-Boot + OpenSBI, with a graphics stack based on the upstream Imagination kernel driver and Mesa. The project explicitly states this is an open-source release for developers, not a production or certified version. Phase two will automate builds and hardware testing, starting with tests on A210 systems in the RISE Board Farm and adding K3 within weeks; subsequent RFPs will cover Bionic, BoringSSL, ART, V8, Chrome, and multimedia libraries. Sources: RISE, android-17-v1.0

  • Linux 7.3 officially released: RVA23 moves from “guessing via Kconfig” to “runtime determinable” (released 10-18, reported 10-19): On the RISC-V side, this release lands hwprobe exposure of RVA23U64 baseline behavior, counter-delegation-related extensions (Smcdeleg/Ssccfg/Smcntrpmf) and resctrl support for Ssqosid/CBQRI, KVM support for Svadu, Zicfiss, and Zicfilp FWFT, a switch to EFI runtime services for shutdown and reboot, and crashkernel CMA reservation shared with arm64; on the platform side, it adds the StarFive JHB100 device tree and Canaan K230 support, and completes detection and enumeration of extensions including Smcsrind, Zicclsm, Ziccamoa, Ziccif, Ziccrse, and Za64rs. Meanwhile, the Linux 7.4 crypto library moves the optimized RISC-V and x86 AES implementations for each mode into lib/crypto, so upper-layer consumers such as filesystem encryption, IPsec, and dm-crypt benefit without changes. Sources: Phoronix (7.3), Kernel Newbies, Phoronix (7.4 crypto library)

II. Instruction Set and Architecture Ecosystem

RVA23: Closing the “Specification—Kernel—Distribution—Chip—Operating System” Loop Within a Single Week

  • Determinability: Linux 7.3 uses hwprobe to expose RVA23U64 baseline behavior, allowing user space to directly determine whether a machine conforms to RVA23 — a key step from “compile-time guessing” to “runtime querying.” The same release completes counter delegation, QoS identifiers, and KVM support for Svadu and shadow stacks (Zicfiss/Zicfilp).
  • Landing in products: SpacemiT V100 was designed against five specifications — RVA23, server SoC, server platform, BRS, and security model — and passed all BRS tests; Sophgo UR-CP400 complies with RVA23 and supports RVV 1.0; K3 is described as the world’s first RISC-V AI CPU compliant with the RVA23 specification and delivered in mass production.
  • Landing in operating systems: RISE’s Android 17 build explicitly targets RVA23 hardware, providing a locked manifest and checksums — the first public baseline for the most demanding combination of “mobile operating system + application processor specification.”
  • Assessment: All three lines aligned with each other within the same week, indicating that RVA23 has moved from specification text to a purchasable, installable, reproducible engineering fact. The next observation point is whether distribution-side profile tiers and glibc’s tiered fallback land alongside kernel progress.
  • Sources: Kernel Newbies (Linux 7.3), RISE (Android 17 on RVA23), Phoronix (SpacemiT V100), Sohu (Sophgo UR-CP400)

XiangShan: Beyond Performance Numbers, This Week’s Focus Clearly Shifted to Privileged Mode, Verification, and CI

  • 10-19 issue (covering 10-16 to 10-18): Main repo #6730 expands the reorder buffer (ROB) to 160 entries, a parameter-level performance adjustment of the out-of-order execution window; GEM5 (xs-dev) #1231 adds intermediate-stage resource partitioning for two-thread SpMT; NEMU #1246 adds the Kunminghu V2 (kmhv2) configuration and aligns with V2/V3 common fixes, while #1252 reduces DiffTest memory CRC verification overhead.
  • 10-20: XSCache #36 splits CoupledL2’s L2 SRAM by set and bank and throttles prefetch admission, targeting last-level cache bandwidth contention and prefetch pollution; main repo #6738 bumps the XSCache submodule version; GEM5 #1241 skips the load pipeline’s replay flag when store/AMO issue fails.
  • 10-22: Main repo #6692 adds decoding for the two privileged return instructions mnret and dret, #6729 fixes the ROB redirect start index, #6696 adds Dashboard and star history links to the README.
  • 10-23 (after the previous daily briefing cutoff, verified via Atom): Main repo #6742 makes StoreUnit report the pointer-masked address in tval, #6756 updates checkpoints, #6701 unifies CI’s PERF_HOME and WAVE_HOME and caches the built emu; NEMU #1260 removes the Copilot review workflow.
  • Simulation and verification: GEM5 merged #1189 Hybrid CROB support and #1257 SMT LSQ DynamicBorrowing donor detection fix and statistics on 10-23, and merged #1214 on 10-22 to initialize memory access size before delayed translation; difftest merged #991 concurrent register write hashing, #996 avoiding copy-back of successful CUDA results, #995 adding BOOM DiffTest integration documentation, and CUDA verification throughput optimizations — all within a single day on 10-23.
  • Assessment: XiangShan published no new performance numbers this week; commits concentrated on privileged-mode decoding, redirect indexing, tval reporting, CI, and DiffTest infrastructure — a typical shape for an open-source core moving from “benchmarking” to “deliverability.” Sources: XiangShan, XSCache, NEMU, difftest

CORE-V: CVA6 Mainline Consolidation, CVW Verification Surface Expansion

  • Governance change (10-23): openhwfoundation/cva6 commit #3664 “master made read-only”; the README explicitly states that the master branch no longer accepts new PRs and is retained only for users continuing to integrate older versions, with all new contributions moving to main, which has become the default branch. This is a branch governance consolidation and a clear migration signal for downstream integrators (especially projects still tracking master).
  • Verification platform: CVW (CORE-V Wally) merged 3 PRs this week — adding QM Tech K7 development board support (PR #1601, continuing to expand FPGA board adaptation) and adding the hptwReservedAD regression test (PR #1993) covering A/D bit updates on reserved leaf PTEs; merged the jalr erratum entry in Table I.1 on 10-22 (PR #1996); merged the Sail 0.16 upgrade on 10-23 (PR #1995), having previously aligned riscv-arch-test to act4 2b0415eef.
  • Assessment: For CORE-V, known for formal verification and regression suites, this week’s actions were “switch mainline + add boundary cases + upgrade the formal model” — a better reflection of verification maturity than new features. Sources: cva6 #3664, cvw

Toolchains and Simulation: DAMO’s Community Contributions and Espressif’s Emulator Consistency

  • DAMO XuanTie (summit figures): RISC-V-related contributions to the GCC community rank second globally, delivering over 10% typical performance gains for processors; more than half of RISC-V code in the OpenJDK community comes from DAMO; it participates in building the CSC certification baseline at the RISC-V International Foundation and has open-sourced 2,796 test cases; C950 is the first to achieve deep adaptation between RISC-V and server-side Java, with a 30% performance improvement.
  • Espressif esp-emu 0.50.0 (10-20): Single-precision fused multiply-add on ESP32-P4 and S31 now takes a host passthrough path, roughly 3× faster, with math functions such as sinf, expf, and powf benefiting accordingly while flag bits remain consistent; the P4’s PSRAM window now follows the PSRAM MMU, so firmware that remaps the external memory window at runtime no longer reads all zeros or hits illegal-instruction traps; the BLE transmit power API fix on C3 and S3 resolves Load access faults; P4 now rejects booting rev 0.x/1.x firmware early on the emulator side.
  • Assessment: Aligning emulator behavior with silicon down to the single-instruction level is a prerequisite for RISC-V endpoint firmware CI to shed its dependence on real hardware; such work generates no headlines but determines the ecosystem’s iteration speed. Sources: GCC/OpenJDK figures per XuanTie summit coverage, esp-emu 0.50.0

III. Operating Systems and Distributions

openRuyi: Over a hundred commits in a week, filling gaps from the toolchain all the way up to runtimes and cloud-native

  • Main repo pace: Oct 19 period 15 commits (dpdk backports of RISC-V lpm and fib lookup optimizations, spdk bumped to 26.09, Rust ecosystem packages updated as a group to regex 1.13.1 / regex-automata 0.4.18); Oct 20 40 commits (minio series, Prometheus and prom2json, IBM sarama, gobwas-ws, xdg-scram, plus two new packages uwsgi and dropwatch); early Oct 22 20 commits (all rust-uv-* 0.0.96 series dependencies, serving uv, the Rust-written Python package manager); another Oct 22 batch of 20 commits (python 3.14.9, nodejs 24.22.1, openjdk-17 17.0.21.9, openjdk-21 21.0.13.9, nginx 1.31.8, python-pillow 13.0.0, rdma-core 65.0, several tagged security-fixes); Oct 23 about 20 commits (go-github-gobuffalo-* series, go-gopkg-gorp.v1, go-howett-plist, go-github-ziutek-mymysql and other Go ecosystem packages landing in batches). Five working days total over 110 commits.
  • Order of fill-in: Go cloud-native components → uv’s Rust dependencies → Python/Node/Java runtime major versions → Go ecosystem packages. Commits tagged security-fixes appear in batches, indicating security updates have entered a process-driven channel rather than scattered patch drops.
  • Dual-source verification conclusion: The latest announcement on the official news page is still the 2026.09 release (published September 30, improving RVA23 support, expanding the cloud and storage software stack, upgrading the Go 1.27 build environment); there was no new release announcement this week; lookout, kiwi-image, TakoPack, and homepage in the organization also had pushes during the same period.
  • Assessment: What openRuyi actually answered this week is “can RISC-V servers handle real workloads” — minio, Prometheus, and sarama determine data-center-side usability, while uv and the Python/Node/Java runtimes determine whether developers can use it day to day. Sources: openRuyi main repo, openRuyi official news

Kernel: 7.3 release and 7.4 performance backports

  • Linux 7.3 (Oct 18): Beyond the RISC-V content listed in this week’s headlines, it also adds detection and enumeration of extensions including Smcsrind/Sscsrind, Zicclsm, Ziccamoa, Ziccif, Ziccrse, and Za64rs, statically computes alternative section boundaries to fix vDSO compatibility, and further removes xip support.
  • Linux 7.4 crypto library (Oct 21): The crypto subsystem performance work by Google kernel engineer Eric Biggers has been merged, migrating the optimized AES implementations for each mode on x86/x86_64 and RISC-V into lib/crypto, covering six modes: ECB, CBC, CBC-CTS, CTR, XCTR, XTS; the RISC-V side uses vector- and crypto-extension-based accelerated implementations. A side benefit is the cleanup of a large amount of duplicated glue code; the same batch also includes AES-XTS optimization for SPARC64.
  • Distribution kernel layer: meta-riscv had 14 commits in the window, linux-mainline went from 7.2.10 to 7.2.11, riscv-common was adjusted to prefer mainline Linux and U-Boot and reduce reliance on vendor BSP branches, and the documentation added boot and UART notes for SpacemiT K3 Pico-ITX, K3 COM260, and LicheePi-4A. The distribution build layer is converging toward mainline, in the same direction as the recent platform consolidation moves by openRuyi and RevyOS. Sources: Kernel Newbies, Phoronix, meta-riscv

RevyOS and other distributions

  • RevyOS: The batch configuration commits on the revyos/linux 7.3.y branch on Oct 19 are identical in content to the 20-commit batch already included on Oct 16 (K3/K1/EIC7700/linuxboot/CI), judged to be a re-push rather than new additions; the runner repo in the organization also had pushes during the same period. No new platform support entries this week.
  • openEuler: None of the five daily reports this week included new openEuler releases or RISC-V SIG activity, so this section does not cover it; openEuler’s listing in the V100 distribution compatibility list reflects the vendor’s claims rather than testing this week.
  • Android on RVA23: RISE’s RP024 (see this week’s headlines) is the most structural progress on the distribution front this week — moving from “yet another port” to “a public baseline with manifest, checksums, flashing tools, and Board Farm regression,” with the second phase automating builds and testing.
  • Community projects: The community project esp32-s31-linux has brought up upstream Linux 7.3 and OpenSBI 1.9 on the Espressif ESP32-S31 (dual-core RV32, 320 MHz, 512 KB SRAM, 16 MB octal PSRAM); the build chain is ESP ROM → ESP-IDF second stage → loader → OpenSBI → Linux → Buildroot root filesystem; available user space includes LCD shell, wpa_supplicant, BlueZ, SSH, USB keyboard/mouse and flash drives, vim, gdb, strace, MicroPython, and links. The technical highlight is that this SoC has no PLIC, no Zicbom, and no coherent DMA, and the project provides alternative implementations in a few hundred lines of code. This project does not constitute a product path, but it is an extreme test case for toolchain, kernel porting, and driver maturity. Sources: revyos/linux, esp32-s31-linux

IV. Chips and Hardware

Server and Data Center CPUs: Five Products Share the Stage in One Week

  • SpacemiT V100: 46 cores (6 XiangShan Kunminghu V2R2 + 40 X100), 2.4 GHz, dual-socket 92 cores, 8-channel DDR5-4800, 52 PCIe 5.0 lanes, supporting H extension/AIA/IOMMU, hardware root of trust and RISC-V native TEE, RERI RAS; offers a lightweight virtual machine solution for cloud Agent applications, achieving VM-level isolation at resource overhead close to that of containers. Complete systems come in three models: C2201/G5201/S5236.
  • Zhongxing Microelectronics’ subsidiary Lirui Micro “Zhufeng 200” (first shown 10-19): officially billed as the industry’s first RISC-V CPU chip for intelligent computing center scenarios, targeting three use cases: Agent clusters, inference super-node Host, and enterprise-grade intelligent computing hybrid inference; natively carries RISC-V AI instruction acceleration, optimized for KV Cache and long-context LLM inference; integrates Matrix, Vector, compression, and encryption acceleration engines, supports DDR5, PCIe, CXL, and can accommodate MoE hybrid inference combining “RISC-V native AI + GPU accelerator cards.” Detailed specifications will be officially released at the end of 2026; this week only confirms direction and scenarios.
  • Chaorui Technology UR-CP400: compliant with RVA23, supports RVV 1.0, out-of-order 8-issue, 14-stage pipeline, SPECint_base2006 exceeding 22 points per GHz under FPGA emulation configuration; virtualization enhancements for multi-tier cloud, plus hardware optimization for Agentic AI. IP is planned for delivery in Q1 2027.
  • Lanxin Computing LX500: 48 cores (32P + 16E), AI Vector/Matrix engines, 75 TOPS INT8, DDR5, CXL; has formed a four-tier matrix of chip—server—all-in-one—super-node.
  • Architectural differentiation: all three independently sidestep “benchmarking against general-purpose CPUs”—Lanxin pursues super-nodes with unified memory and CXL, Ruixin and Zhongke Tongliang pursue a dataflow architecture, and DAMO pursues SMT and AME matrix extensions. Under advanced process constraints, these are the paths to reclaiming performance through design. Sources: 21jingji (Zhufeng 200), Sohu (Chaorui)

Edge and Application Processors

  • Espressif ESP32-S31 ecosystem enters the finished-product phase: the company launched the ESP-Mosaico modular development platform (core board ESP32-S31NRV16: 320 MHz RV32IMAFCP high-performance core + low-power MCU core, 512 KB SRAM + 16 MB PSRAM, Wi-Fi 6/Bluetooth 5.4/802.15.4, 128 MB SPI NAND + 16 MB NOR; 2.16-inch 480×480 QSPI touchscreen, dual BMM150 magnetometers, BMI270 six-axis), with a complete kit including camera and interaction modules at $59 and a battery module at $15; development is centered on ESP-Claw natural-language “conversational coding” and ESP-ZeroCode AI’s “vibe programming.” Less than ten days after the ESP32-S31 first appeared in a third-party development board (10-14), finished products are already being refreshed—the GUITION JC3636F118C-I-YR1 knob display upgrades from ESP32-S3 to ESP32-S31NRV16 (1.8-inch 360×360 round TFT, 16 MB flash + 16 MB PSRAM, Wi-Fi 6/Bluetooth 5.4/802.15.4).
  • LILYGO T-Halow P4 (10-23): an M.2 2280 form-factor (80 × 22 mm) development board built around the ESP32-P4NRW32X (dual-core RISC-V @400 MHz + single low-power RISC-V core @40 MHz, with AI instruction extensions and single-precision FPU), paired with an ESP32-C6 wireless co-processor (Wi-Fi 6/Bluetooth 5/802.15.4) and a Taixin TX-AH WiFi HaLow module (859–894 MHz or 902–928 MHz, up to 1.2 km line-of-sight), supporting MIPI CSI/DSI and 1080p30 H.264 hardware encoding; from $26.57 in the official store.
  • Sophgo: sophon-tools saw 7 commits in one day; the batch deployment tool pqt_batch_deployment was rewritten in Go + Fyne and now outputs a single binary for both Linux and Windows, followed by version-by-version progress: 2.1.0 (Web UI and headless build), 2.2.0 (reworked desktop GUI and Web UI visuals), 2.3.0 (LAN scanning, batch device discovery by MAC prefix), 2.4.0 (fallback to Ping-only when MAC is unavailable); sophon-demo within one week added C++ samples for SAM, SAM2, SAM3, YOLO_world, YOLO_world_v2, D-FINE, Recognize-Anything, FearTracker, MP_SENet, BLIP, added three multimodal models—MiniCPM4, InternVL3, MiniCPMV—for the CV84X6 platform, and on 10-22 added a Python sample for PaddleOCR-VL; zsbl completed the cpusys directory split and moved application selection up to SoC-level Kconfig.
  • Radxa Linkr v1.6.0 (10-21): Radxa’s browser-based remote management product line for development boards and NAS, maintained across six repos—the main linkr repo plus plugins, linkr-skills, linkr-docs, linkr-docs-en, and docs—holding to a biweekly release cadence over the past month (the previous version, v1.5.2, shipped on 10-08). The release page does not include a changelog.
  • Assessment: the center of gravity in edge competition is shifting from spec sheets to developer experience—natural-language firmware generation, AI agents running tests on real hardware, and sample libraries moving from Python reference implementations to engineering-grade C++ samples. As chip specs converge, whoever shortens the path “from idea to hardware” is more likely to win developers. Sources: CNX (ESP-Mosaico), CNX (T-Halow P4), sophon-demo

IP, Automotive-Grade, and Niche Categories

  • ESWIN Computing: the first market assessment after its 10-09 Hong Kong Stock Exchange listing is out—closed its first day at HK$1.535, down 0.97%, with a market cap of about HK$33.8 billion; revenue from 2023 to 2025 was RMB 1.752/2.025/2.431 billion, adjusted net profit −1.705/−1.440/−1.161 billion, gross margin 14% to 18%; human-machine interaction chips still account for 76% of revenue, with average selling price falling from RMB 20.9 to 11.6. By 2025 revenue, it ranks fifth in China’s RISC-V main control chip market and third among domestic vendors, with a 1.2% share (the top five together hold 22.5%). On 10-21 it signed a Gold Partner Alliance MOU with SiFive, extending cooperation from edge AI to Agentic AI; its EIC7700 SoC is already used in SiFive’s flagship development board, the HiFive Premier P550.
  • Zijing Semiconductor (incubated by Great Wall Motor) Zijing M100: has become a mass-production, on-vehicle RISC-V automotive-grade chip. A RISC-V automotive-grade product incubated inside an OEM moving from samples to mass production is the hardest evidence in this round of “getting onto vehicles” narratives.
  • RISC-V’s place in mmWave radar (10-22 roundup): Zhenghe Microelectronics’ RS6240 (released in 2024, dual-core RISC-V) is used in smart home, elderly care monitoring, and security alerting; Kaiku’s K60213 integrates a RISC-V MCU and AI accelerator; Nuclei’s NA900 has obtained ISO 26262 ASIL-D certification, and Calterah’s Kunlun-Pro integrates this core with dual-issue dual-core total compute of 3668 DMIPS (about 5× the previous-generation Alps-Pro), advancing L2 ADAS forward perception. Key boundary: the 10× signal-processing compute that has drawn outside attention comes from Calterah’s in-house RSP 2.0, not the RISC-V core; RISC-V handles the parts that must stay on a programmable CPU, such as point-cloud post-processing and target tracking. TI’s AWR2188 and NXP’s TEF8388 and SAF8444 still use Cortex-A53 and M7, with no short-term incentive to switch.
  • Assessment: RISC-V’s real position in niche categories is not “what it replaces” but “where it pays off more”—the drivers are supply-chain controllability, cost, and freedom to customize, not a performance generational gap; functional safety is not a weakness either (NA900 already has ASIL-D). What is genuinely long is the three-to-five-year certification cycle for a complete chip. Sources: Sina Finance (ESWIN), NetEase (SiFive MOU), RFID World

Capital and M&A

  • Domestic primary market: Ruixin Semiconductor (睿思芯科) completed a new round of strategic financing (Renjun Capital and Shuimu Fund participating, amount undisclosed), with proceeds for RISC-V server-grade high-performance processors and cloud-native CPU R&D; Xinji Wuxian completed a Pre-A round of tens of millions of RMB (Zhiyuan Robotics together with Anhui Provincial Automotive Innovation Center, Guoyuan Equity, Hefei Baohe Venture Capital, with Wanchuang Investment Bank as financial advisor); SpacemiT completed a B+ round (Qiming Venture Partners, Guoxiang Capital, Shangqi Capital, Woan Robotics, C&D Emerging Investment, Biyi Co., China Merchants Bank International, Shenzhen Investment Holdings, and Yaotu Capital participating; Biyi Co. disclosed it on the evening of 10-20).
  • Overseas: Tenstorrent’s $1.5 billion Series E ($6.2 billion post-money); Qualcomm’s acquisition of Akeana (see this week’s top stories); Ubitium closed a $14 million new seed round (led by Ibex Investors with OpenOcean participating, $18 million cumulative), with its first validation chip UB108 on Samsung 8nm with 256 processing units, and commercial chip UB410 planned with 4096 processing units and evaluation samples slated for delivery in 2027.
  • Hot and cold divergence: the primary market keeps adding capital while the secondary market prices in “rationally cool” terms (ESWIN broke issue price on its first trading day). The mismatch between long-term industry space and near-term profit realization remains the main valuation theme. Sources: Sohu (Ruixin Semiconductor), Eastmoney (Xinji Wuxian), Sohu (SpacemiT)

V. Open-Source Community and Industry Activities

Summit: Ecosystem Maturity as Seen Through Agenda Delivery

  • Scale and structure: Opened 10-18, closed 10-20, with over 3,600 on-site professional attendees and more than 450 exhibitors and research institutions; 10-18 featured four concurrent tracks (Member Day/Workshops/Community Exchange, GPGPU track, AI for RISC-V track, XiangShan processor track), 10-19 the opening ceremony and main forum, 10-20 seven parallel sub-forums (the Automotive Electronics and Industrial & Robotics sub-forums co-chaired by Xu Tao of StarFive and Yang Yong of WCH), and 10-21 Hong Kong Day.
  • Main forum highlights: In the morning, Andrea Gallo (Architecture for Intelligence), David Patterson (RISC-V in the AI Era), Rong Zhicheng (From RISC-I to RISC-V), Meng Jianyi (Technical Innovation and Open Ecosystem of XuanTie IP), and Chen Zhijian (From Edge to Cloud); in the afternoon, Krste Asanović (RISC-V State of the Union), Aniket Saha (Tenstorrent), Zhou Meng (Scaling Inflection Point and Standardization), He Ning (ESWIN RISC-V + AI), and Jia Xinxia (Blue Core LX500). The lightning talk session included ZTE Microelectronics, SiFive, Synopsys, Chaorui Technology, Sophgo, MIPS, Beijing Institute of Open Source Chip, Cadence, and others.
  • Gap between sub-forum messaging and engineering detail: The overall message of the Automotive Electronics and Industrial & Robotics sub-forums was that “RISC-V has moved from whether it can be used to being usable and commercial,” but in engineering detail the discussion still centered on three hard problems—safety certification, real-time control, and toolchain compliance—which are precisely the shared threshold for robot joint control and automotive-grade chassis domain control. IAR framed three major challenges from a toolchain perspective and launched RISC-V development tools, while Nuclei shared its AI chip IP solutions (dynamic vector length, extensible instruction set, unified software ecosystem).
  • First post-summit actions: Kehua Data and SpacemiT signed a strategic cooperation agreement (10-22) covering four dimensions—technology, products, market, and ecosystem—to connect the adaptation link between the AI chip layer and the computing infrastructure layer. Kehua has nearly 40 years of deep expertise in power electronics and over a decade of data center construction and operations experience, and led the drafting of the CCHS (Coordination Technical Specification for Domestic Chips and Computing Hardware Infrastructure) group standard. Foreign media noted in the same period that competition in server CPUs is not only about single-chip performance—whether adaptation and maintenance costs are acceptable is the key to customer migration. Sources: Summit official website, People’s Daily Online (sub-forum recap), Guandian (Kehua signing)

Policy and Industry Data

  • MIIT (10-19 press conference): In the first half of this year, China’s humanoid robot complete products exceeded 400 models, with output exceeding 40,000 units, and are expected to exceed 100,000 units for the full year; related products have been validated and deployed in more than 300 key scenarios, including warehousing and logistics, catering and retail, and home services. Next steps include advancing the “reveal the list and take the lead” mechanism to tackle key common technologies, real-world training, publishing the 2026 edition of the National Humanoid Robot Industry Standard System Construction Guide, building a high-level humanoid robot open-source community, establishing an industry monitoring system, and strengthening quality and data security testing.
  • Market forecasts: Frost & Sullivan data shows that RISC-V penetration in China’s embodied intelligence chips is expected to rise from 10.7% in 2025 to 28.2% in 2030, and in intelligent terminals from 6.9% to 26.7%; China’s RISC-V main control chip market is projected to grow from approximately RMB 37.7 billion in 2025 to approximately RMB 219.4 billion in 2030.
  • AgiBot’s capital map: In two years it has invested in 47 companies, established at least 17 new companies through joint ventures, and reached cooperation including capital ties with more than 40 listed companies; the “AgiBot A Plan” aims to incubate more than 50 early-stage projects within three years; shipment pace is expected to reach several thousand units this year and tens of thousands next year. Body manufacturers are binding upstream chips through capital, so that the instruction set choice for embodied intelligence is locked in by industry capital at an early stage.
  • Assessment: The policy’s two levers (standard system and open-source community) correspond precisely to the software and interface specifications that have long been missing on the RISC-V side; embodied intelligence is the only direction this week with evidence at all three levels—policy, capital, and shipments. Sources: Sina Tech (MIIT), Securities Times, Dahe Cube (AgiBot)

International Community

  • riscv.org: Published a summit poster paper from the CERN team (Benoît Denkinger et al.) introducing SoCMake, developed under the SOCRATES (System-on-Chip Radiation-Tolerant Ecosystem) project for modular construction of radiation-tolerant RISC-V SoCs for high-energy physics; the accompanying prototype chip TriglaV is a fully radiation-tolerant ASIC targeting harsh-radiation environments such as LHC detector front-end readout. The technical combination comprises triple modular redundancy, hardened interconnect, and memory protection, and is equally applicable to safety-critical scenarios in automotive and industrial control.
  • Boundaries: Most international media coverage of this week’s server products consisted of post-summit roundups overlapping with items already reported domestically; the judgment that “adaptation cost is the real threshold” came from interviewed industry analysts and does not represent industry consensus. Sources: riscv.org blog, Global Times

VI. Trend Observations

  • The focus of server RISC-V is shifting from “launch” to “adaptation”: This week V100, LX500, Zhufeng 200, and UR-CP400 were unveiled in quick succession, proving that hardware form factors are already in place; yet the first action after the summit was Kehua Data’s infrastructure coordination signing with SpacemiT, and foreign media analysis also listed adaptation and maintenance costs as the decisive variable for customer migration. The next stage in the cloud will be won not at launch events but in machine rooms and software stacks.
  • Open-source cores enter a sellable commercial server chip for the first time: Of V100’s 46 cores, 6 are XiangShan Kunminghu V2R2—open-source high-performance cores are no longer merely academic and verification targets but are entering data center products as IP. In the same week, OpenHW made CVA6’s master branch read-only and set main as the default branch; governance and productization of open-source core projects are converging simultaneously—one in, one out, forming the two sides of “open-source core supply capability.”
  • Server IP supply is diverging into three paths: Qualcomm absorbed Ventana and Akeana within ten months (big-company internal assets), domestic players are putting open-source cores into commercial chips (V100), and ESWIN chose “in-house cores + external IP alliance” (upgrading its MOU with SiFive). All three paths answer the same question: where does server-grade RISC-V IP come from?
  • Performance roadmaps bypass process nodes and turn to architecture and systems: Dataflow (RuiXin, Zhongke Tongliang), unified memory and CXL (Blue Core), SMT and AME matrix extensions (DAMO), reconfigurable arrays (Ubitium)—under advanced-node constraints, these are the means of winning back performance through design. The “5x” target DAMO set for C950A is essentially an extension of the same logic.
  • The distribution’s fill-in layers moved up two levels in one week: openRuyi advanced from toolchain and kernel packages to cloud-native middleware (minio, Prometheus, sarama), then to Python/Node/Java runtimes and the Go ecosystem; security fixes began flowing through the process in batches tagged security-fixes. The RISC-V distribution is moving from “installable” to “safe for production,” but the official website version remains at 2026.09—release cadence and commit cadence are not in sync.
  • The first wave of real embodied intelligence shipments comes from real-time control, not general-purpose AI compute: MIIT puts the full-year scale at 100,000 units, AgiBot has bound upstream chips through 47 investments, and verifiable product progress shows that joint control chips and cerebellum chips are already in mass production and automotive-grade motor control MCUs have shipped over 1 million units, while V1000 (2.5D Chiplet, 1000 TOPS), positioned as the “brain,” is still in tape-out. This pace gap says more about where the industry stands today than any roadmap.

Appendix: Sources and Verification Notes

Source Composition

  • Five daily briefs: 2026-10-19 (72-hour window, covering 10-16 05:00 to 10-19 05:00), 10-20, 10-21, 10-22, and 10-23 (each a 24-hour window, continuing from the prior cutoff). The main body of this report therefore covers events across the eight days from 10-16 to 10-23, of which 10-16 to 10-18 falls within the normal coverage of the Monday issue.
  • Friday fill-in: the final cutoff of the five daily briefs was 10-23 05:00, so activity during the day on 10-23 falls outside any daily window. This report re-checked that period separately: 3 commits to the main XiangShan repo (#6742, #6756, #6701), 1 to NEMU (#1260), 2 to GEM5 (#1189, #1257), 4 to difftest (#991, #996, #995, and a CUDA throughput optimization), 1 to CVA6 (#3664, master converted to read-only), about 20 to openRuyi (Go ecosystem SPECS), and the new LILYGO T-Halow P4 product — all verified via Atom or official pages before inclusion.

Supplementary Verification Results

Verification Item Result
GitHub watched organizations (168-hour window) Repos pushed within the window: espressif 78, spacemit-com 37, sipeed 11, openhwfoundation 7, spacemit-robotics 6, openRuyi-Project 5, radxa-linkr 4, sophgo 3, XUANTIE-RV 3, Nuclei-Software 2, eswincomputing 2, revyos 2; all key repos — XiangShan, XSCache, NEMU, GEM5, difftest, cva6, cvw, openRuyi — had pushes
Per-repo re-check of the XiangShan family Main repo kunminghu-v3: 7 commits this week (including three on 10-23); XSCache: 1 (#36); NEMU: 3; GEM5: 5; difftest: 5. On 10-21 and 10-22, some repos showed a pushed_at update but no new commits on the default branch in Atom; these were judged to be non-default-branch or PR head-branch activity and were not included as entries
openRuyi dual-source check More than 110 commits to the main repo over five working days; the latest item on the official news page remains 2026.09 (published 9-30), with no new release announcement this week
Member company website sweep (391 sites, 168-hour basis) Took 270 seconds: 226 unchanged, 97 with content changes, 68 failed to fetch. The changes were routine homepage updates at universities and vendors such as NVIDIA, AMD, SiFive, MIT, imec, and METU; no substantive RISC-V product, funding, or architecture announcements were detected
riscv.org blog 1 substantive new article within the window (CERN SoCMake / TriglaV), included
Pending-inclusion queue During the period, the 10-22 queue file contained only FlagOS entries; nothing on the RISC-V side was pending inclusion

Limitations and Methodology Notes

  • Two inconsistent Omdia figures: the 10-19 brief quotes Meng Jianyi as saying “by 2030, annual shipments will grow nearly 30% year over year, accounting for about 25% of global processor shipments,” while the 10-23 brief quotes Sun Yanbang as saying “annual shipment growth rate of 50%, with global market share approaching 25% in 2030.” The share figures agree; the growth-rate figures differ. This report adopts only the common element (about 25% in 2030) and leaves the growth-rate discrepancy open pending verification.
  • Vendor claims not independently verified: V100’s “industry’s first chip fully compliant with server specifications,” Ruixin D35’s “world’s first mass-produced RISC-V dataflow physical AI chip” and “core IP validated through Intel global procurement,” the Zhongke Tongliang workstation specifications, and the scenario positioning of Zhuifeng 200 are all company statements or on-site summit presentations, without third-party measured reproduction.
  • Single-source process and power data: V100’s 12nm / 120 W appears only in overseas media reports; the official Chinese release does not list these two items.
  • Not yet public: detailed specifications of Zhuifeng 200 (to be released at year-end); the number of chips per node, interconnect method, and delivery timeline for the Lanxin supernode; the transaction value and product integration plan for Qualcomm’s acquisition of Akeana; the amount and timetable of the KEHUA Data–SpacemiT partnership.
  • Vendor test data: Calterah Kunlun-Pro’s 3668 DMIPS and clustering/tracking timings come from vendor tests; XuanTie’s 6 billion units shipped, GCC’s global No. 2 ranking, and OpenJDK’s majority contribution are summit figures.
  • Form-factor boundaries: RISE’s Android 17 is explicitly a developer version, not for mass production; esp32-s31-linux is a community project and does not constitute a productization path; CubeSandbox’s RISC-V support remains a developer preview, with no official release images; the V1000 brain chip is still at the tape-out stage.
  • Handling of duplicate coverage: this week, items such as V100, E908A, UR-CP400, Zhuifeng 200, Tenstorrent, and XuanTie’s 6 billion units were republished on later dates; they are included under their first-report date and not counted twice, and the appendix sources retain the original attribution.
  • Sources: all entries are drawn from the daily RISC-V Global Dynamics briefs (2026-10-19 to 2026-10-23); key data were re-verified this period via GitHub Atom, the openRuyi official news page, the riscv.org blog, and the member website sweep.