Reporting period: Monday, October 12, 2026 to Friday, October 16, 2026 — 5 working days, material from 5 daily issues.

Sources: Daily RISC-V Global Updates (five issues: 10-12, 10-13, 10-14, 10-15, 10-16; the 10-12 issue covers a 44-hour window starting from the previous issue’s National Day holiday make-up cutoff of 10-10 09:20); additionally verified through a 168-hour window review of followed GitHub organizations and key repositories, dual-source verification of openRuyi, and supplementary checks of riscv.org and RISC-V International member official websites; the Ubuntu 26.10 release image was verified against the official cdimage site.

Editorial note: Core items from the five daily issues are aggregated under four dimensions: “Instruction Set & Architecture Ecosystem / Operating Systems & Distributions / Chips & Hardware / Community & Industry Activities”; developments on the same thread across days are merged into a single narrative. Facts, version numbers, and dates are taken from verified sources in the relevant issue or from this period’s hands-on verification; single-media claims and vendor self-statements are flagged in the text.

I. Weekly Highlights

  • DAMO XuanTie C950 runs a 27B large model on a 64-core target configuration without a standalone accelerator; results amplified via an interview on the RISC-V International Foundation website (10-15): The RISC-V International Foundation’s “V Questions” column published an interview with Meng Jianyi, Chief Scientist of XuanTie and Vice Chair of the RISC-V China Summit 2026, disclosing that the XuanTie team natively ran Qwen3.8-27B (27 billion parameters) on a 64-core C950 configuration without relying on a standalone GPU/NPU, achieving a decode speed of over 30 tokens/s (roughly 20 to 22 words/s, reaching natural real-time conversation level); this workload requires about 400 GB/s of memory data movement capability, and the interview emphasizes that quantization, matrix instructions, on-chip memory, bandwidth, and operator optimization must be co-designed as a single system. The C950 is a server-class 64-bit superscalar processor with the RVA23 profile (including RVV 1.0) as its general-purpose computing baseline; after XuanTie’s self-developed matrix extension was silicon-validated, it co-founded the AME (Attached Matrix Extension) task group with members including Qualcomm, IBM, VRULL, ISCAS, and BOSC, and is pushing the specification toward formal ratification. In design, AME uses separate tile registers rather than reusing vector registers, and natively supports INT4/INT8→INT32 and FP4/FP8/FP16/BF16→FP32 mixed-precision accumulation. Caveat: the decode speed is the company team’s own figure, without third-party benchmarks or full-system power data. Source: riscv.org

  • Lanxin Computing completes nearly RMB 2 billion Series B financing; RISC-V + AI server chip enters mass-production validation (10-12 Chinese first / 10-13 English follow-up): Shenzhen Lanxin Computing completed a Series B financing totaling nearly RMB 2 billion (about USD 299 million), with existing shareholders Shenzhen Capital Group, Huakong Fund, and Longqiu Capital increasing their investments, and new entrants including Jiangsu State Investment, Suzhou Venture Capital, GigaDevice, Cowin Capital, CCB International, Yueke Financial, and JiuKun Venture Capital; the funds are directed toward RISC-V CPU mass production, AI heterogeneous processor iteration, and general-purpose computing solutions for telecom operators/financial institutions/cloud service providers. The core product LX500 is a 48-core heterogeneous (32 performance cores + 16 efficiency cores) server CPU with an integrated 75 TOPS (INT8) AI engine, supporting RVV 1.0 and RVA23, and natively compatible with PCIe 5.0 and CXL 2.0; it taped out and lit up in February 2026, and in July the Lenovo Wentian WR5219 G5 carrying this chip rolled off the production line in Hefei (Lianbao), and has been adapted to China Mobile’s BC-LINUX and completed inference validation of Kimi K2.6 and Qwen3.6-35B. Caveat: the financing scale is per Chinese media and DIGITIMES, and the chip has no third-party performance evaluation yet. Sources: Phoenix Net · Pedaily, DIGITIMES

  • RVA23 goes from “specification” to “decidable fact”: 8 kernel profile-bit patches enter riscv/for-next, single-query capability reported by Phoronix (10-11/10-14): An LPC26 trip report discloses that the Linux kernel rva23u64 profile bit series has advanced to v9 (in flight), and the first 8 of the 11 patches in v8 were merged into riscv/for-next by RISC-V kernel maintainer Paul Walmsley on 10-09, with the remaining 3 to be submitted with v9 after incorporating on-site LPC feedback. Four conclusions from LPC26: v9 will add RVA22/RVA20 tiered bits to facilitate gradual fallback in glibc; glibc will switch to building by profile with automatic library selection via glibc-hwcaps (hwcaps sourced from kernel bits, with ifunc reserved for microarchitecture level); the userspace interface for dynamically disabling the V extension will be deprecated, and Samuel Holland (SiFive) sent out a 3-patch series the next day; future extensions with register state (such as matrix) will no longer introduce similar switches. This series has spawned no fewer than 5 mainline series, including the two-year-stalled extension-name case unification and Zicclsm, and ByteDance’s Qingwei Hu’s Zic64b support. On 10-14 Phoronix followed up with a report on the patch for “querying in a single call whether the system is RVA23-compliant” (the approach being a single-bit riscv_hwprobe KEY_BASE_BEHAVIOR: IMA RVA23U64); previously Ubuntu-side tools could only give “probably RVA23”. Sources: LPC26 trip report, Phoronix, LPC26 presentation materials

  • Ubuntu 26.10 officially released, first official RISC-V desktop image lands with the release, baseline explicitly RVA23 (10-15): Ubuntu 26.10 (Stonking Stingray) was released on October 15, and the official cdimage site now provides ubuntu-26.10-desktop-riscv64.iso (4.0 GB), labeled “for 64-bit RISC-V RVA23 and above processors”; the same batch of riscv64 images also includes live-server (1.6 GB), netboot tarball, and preinstalled-server (1.3 GB). This is the first time Ubuntu has provided an official RISC-V image with a desktop environment (previously riscv64 had only server/CLI versions), and Canonical simultaneously provides official support and installation documentation for the SpacemiT K3 Pico-ITX; an experimental Xubuntu Minimal image targets QEMU environments (GNOME takes over 30 minutes to load under pure emulation). A week before the release (10-12), the community published testing guidance on “what to test” along with Chinese media coverage. Significance: the desktop image is the first time the RVA23 baseline has landed in a consumer-downloadable finished product, forming a “specification—kernel—distribution” closed loop with this week’s kernel profile-bit progress. Sources: Ubuntu cdimage 26.10, Canonical Discourse

  • openRuyi firmware line releases on three consecutive days, K3 platform support becomes the main line (10-13/10-14/10-15): The openRuyi project released three versions in the window—“Ruyi Firmware 20261013”, “20261014”, and “20261015”—all centered on SpacemiT K3: the 13th version lands GOP graphics output and EDID modes for the K3 Pico-ITX, PCI option ROM, RTL8127 wired NIC driver, boot selection and console hotkeys, and provides two firmware variants with and without x64 emulation (x64emu) (AMD Radeon RX 6400 verified under x64emu); the 14th version adds K3 dual-cluster CPU mode selection—UEFI Setup offers three tiers: X100 only (default, 8 cores, RVV VLEN 256, H extension retained) / X100+A100 (16 cores) / A100 only (8 cores, VLEN 1024), with the setting persisted to a dedicated SPI sector, read by coreboot before OpenSBI starts, A100-only boot handing SEC from hart 0 to hart 8 via SBI HSM, and the device-tree root compatible string reflecting the mode accordingly; the 15th version adds raw SPI flashing installation documentation, an A100-only mode interrupt routing fix, a System Information page and DRAM list, and an IMG GPU clock device-tree fix. In the same week, the main repo (openRuyi) completed Go 1.27.2/OpenSSL 3.6.5/docker-cli package splitting, a full KDE Plasma 6.7.5 upgrade (19 packages), Mesa 26.2.4 and PowerVR backports, and a security maintenance batch for cups, python-nltk (CVE-2026-81726), capstone 5.0.9, llama-cpp 0.4.1, and multipath-tools 0.15.1. Sources: 20261013, 20261014, 20261015

  • SpacemiT opens up its full on-device Agent stack: Bianbu AgentOS components open-sourced in a batch, llama.cpp standalone backend released twice in a row (10-12 ~ 10-15): After a concentrated round of repo creation on the evening of 10-13, SpacemiT made its on-device Agent system software stack (Bianbu AgentOS) public on 10-14: the desktop BiBit GUI and offline voice Bibit Voice released 1.0Beta1, while also open-sourcing the Agent runtime (bianbu-agent-runtime, YAML-configuration-driven, sessions as event streams, securityd signed manifests and Tool approval, fail-closed in production mode, currently supporting only K3/Bianbu 4.0), the local-first memory service (bianbu-agent-memory, three tiers of L1 session events/L2 working summaries/L3 long-term memory, SQLCipher encryption and namespace isolation), and components such as intent routing and file search; on 10-15 it completed the capability distribution infrastructure—APM (agent-power-manager, consolidating retrieval, installation, and upgrade of the four Power types Skill/Plugin/MCP/Expert into a unified command, Apache-2.0), Bibit Agent Hub (capability center frontend plugin + Go CLI Provider, supporting riscv64 builds), and the Bianbu Skills read-only mirror (11 Skills in the first batch). On the AI inference side in parallel: the llama.cpp branch introduced a standalone ggml-spacemit backend (PR #43, enabled only when both the device backend environment variable and --device SPACEMIT0 are set) and released v0.2.1/v0.2.2 back-to-back (the latter fixing garbled output from Qwen3.5-2B on K1). Caveat: all components are first validated on the single K3 platform, and cross-platform portability remains to be seen. Sources: bibit 1.0Beta1, bianbu-agent-runtime, llama.cpp v0.2.2

  • RISE publishes RVV vector optimization results for SpeexDSP: resampling accelerated up to 4.88x (10-13): The RISE project published the RP020 completion results—introducing hand-written RVV assembly for the real-time audio foundation library SpeexDSP (widely used by VLC, Firefox, Wireshark, PulseAudio, Mumble, etc.): the floating-point resampling kernel is 3.71x (Clang 18)/3.59x (GCC 13) faster than compiler auto-vectorized C, and the fixed-point kernel 2.69x (Clang 18)/4.88x (GCC 13, which failed to auto-vectorize). Thanks to RVV’s length-agnostic nature, the same assembly is effective on both physical platforms, SpacemiT K1 (VLEN=256) and Canaan K230 (VLEN=128); the accompanying Meson + Checkasm validation also incidentally found and fixed an 8-year-old data-dependency defect in the SSE2 kernel. The project was advanced by Google engineers in collaboration with RISE, with RISE funding USD 40,000. Source: RISE Project

II. Instruction Set and Architecture Ecosystem

RVA23 and the Kernel: Profile Bits Merged, Auto-Vectorization Experiments, and “Compliance You Can Query”

  • Profile bits enter the merge pipeline: Of the 11 patches in v8, 8 have entered riscv/for-next (10-09), with the remaining 3 submitted in v9; v9 will add RVA22/RVA20 tiered bits to enable glibc to fall back level by level, and will document the legacy behavior of not inheriting IMA bits. On the glibc side, the approach shifts to profile-based builds plus automatic library selection via glibc-hwcaps; GCC maintainer Jeff Law is pushing in the same direction at the RISC-V BoF at GNU Tools Cauldron; the userspace interface for dynamically disabling the V extension will be deprecated (SiFive’s Samuel Holland has already posted a 3-patch series), and future extensions with register state will no longer introduce similar switches.
  • Spillover series: This series directly or indirectly drives no fewer than 5 mainline series—the two-year-shelved extension-name case unification and Zicclsm were absorbed, ByteDance’s Qingwei Hu contributed Zic64b, do not report disabled extensions (6 patches), cpufeature BUNDLE-to-SUPERSET streamlining, and the V-off deprecation series. This year’s LPC RISC-V MC featured 10 talks in total, 3 of them from Qualcomm.
  • Kernel auto-vectorization: At LPC26, Andy Chiu presented practice on optimizing the kernel via compiler auto-vectorization—LZ4 improved by up to about 15%, Btrfs by about 8.4%, XFS by about 5%, and Nginx scenarios by about 2%, at the cost of increased time and memory overhead for vector context management. RISC-V kernel builds still do not enable the V extension; these results prompt a re-evaluation of the long-standing taboo against using vectors in kernel mode.
  • Query interface: On 10-14, Phoronix reported on the single-bit query scheme (KEY_BASE_BEHAVIOR: IMA RVA23U64, computed once at boot from the full ISA bitmap), initiated as an RFC by Andrew Jones and advanced by Guodong Xu; the accompanying “RVA23 in practice” talk materials have been published on the LPC website. Sources: Phoronix auto-vectorization, LPC26 vector talk

XiangShan: Compressed ROB, Fully Associative vBTB, and L2 Memory Access Latency Advance on Three Fronts

  • Frontend and out-of-order structures: Within the window, the main repo (kunminghu-v3) landed the compressed ROB (crob) architectural feature—implementing the compressed ROB and integrating CSR state tracking, refactoring the compression state and timing paths, carrying event locations for ArchEvent, maintaining ordered store checks via entry offsets, fixing scommit bit width, and expanding the entry count; subsequently merged the MBTB (main branch target buffer) fully associative vBTB (#6587), fixed the MMU ignoring the PTE G bit when V=0 (#6695), selected the narrow-shift bias of the ALU by output format (#6689), and fixed store-queue forwarding of stale store data (#6693).
  • Memory access and cache: On 10-14, merged reduced L2 load-to-use latency (#6713), and fixed ICache exception propagation and bank selection for the fetch-block end offset under data ECC scenarios, and added support for decoding Zimop (MOP) instructions. At period end (10-15), the main repo had no new merges, with branch-level pushes dominating (kunminghu-v2 had 1 ChiselAIA backpressure fix).
  • Simulation and verification chain: NEMU decoupled AME matrix extension instruction dispatch from PMEM access (#1249), accelerated AME matrix hashing, fixed AME matrix store rollback records (#1251) and first-page write preservation for cross-page store page faults (#1240), and released v2026.10.r3; difftest added the MCSim timing backend (alongside DRAMSim3), delta encoding for mcsr/mcfg, lane-parallel CRC-64 store hash verification, GBD1 frozen-bank DMA drain, and trace handshake gating (#990); the GEM5 branch (xs-dev) added Zimop instruction support and TRACERTL/NEMU trace formats, restored macOS builds, and added a manual smoke-test CI (#1228); on 10-15 it further merged the MLP-aware fetch policy, enabled the private MBTB victim cache by default (#1235) and fixed its invalidation under shared writes (#1236), and added a weekly ideal-BTB SPEC benchmark (#1233).
  • Assessment: This week XiangShan’s investment runs in parallel on three fronts—”frontend structures (crob/vBTB) + memory access latency + verification infrastructure (timing backend, hash verification)”—with the verification chain’s engineering maturity advancing faster than public disclosure of core performance data. Sources: XiangShan, NEMU, GEM5, difftest

Architecture Testing and Toolchains: XuanTie ATS Adds BF16 Vectors, ESWIN Open-Sources AME Test Vectors, openKylin’s RVV Gains

  • DAMO XuanTie: The damo-rv-priv-ats privileged architecture test framework merged PR #37, introducing the T-SBI (Test Supervisor Binary Interface) protocol layer and migrating all test suites to the S-mode regular execution model—the boot phase completes M-mode-only initialization and then drops to S(HS) mode before main() to correctly model HS-perspective behavior such as Smstateen-gated CSRs; damo-rv-ats merged Zvfbfmin and Zvfbfwma (BF16 vector) instruction tests (vfncvtbf16/vfwcvtbf16 and vfwmaccbf16.vf/.vv cases plus build scripts), and added four framework documents covering common infrastructure, integer vectors, floating-point vectors, and vector cryptography; damo-rv-priv-ats also upgraded its Sail formal model dependency to 0.15; thead-extension-spec merged 3 commits (RV32 LWUD fix #80, user PR #78, README update #72).
  • ESWIN Computing: Open-sourced the riscv-matrix-gemm-vectors repository, providing a matrix multiply-accumulate test vector set (BF16 × BF16 → FP32) targeting the RISC-V Matrix Extension (AME) specification proposal v0.6.0—each case is a bare-metal self-checking program, accompanied by implementation-independent reference values and a checker; the criterion uses standard rounding error bounds ( Ĉ−C* ≤ γ(G)·Σ a·b ) rather than bitwise comparison, to accommodate the unordered-summation implementation differences permitted by the spec; two cases are also provided where “all compliant implementations produce bit-identical results” to detect incorrect rounding. The suite does not depend on a specific instruction set and can be reused for other matrix extension implementations.
  • openKylin: At Open Source Summit Europe 2026 (Prague, 10-07 to 10-09), disclosed RISC-V-side progress—RVV kernel optimizations speed up ONNX Runtime FP32 inference by 2 to 5 times, and the related kernel optimizations and inference framework adaptations are planned to be contributed upstream; the AI stack supports CPU inference with vLLM on the SpacemiT K3, with delivery forms including deb, Python wheel, Conda, and Docker; a K3 laptop preinstalled with openKylin 3.0 was exhibited on site.
  • Architecture proposal discussion: Community author FProx published an analysis of RVBNA (RISC-V Bulk Normalization Algorithm)—a scalable dot-product approximation scheme centered on a fixed-point accumulator, with round-to-odd rounding in both the product and accumulation stages; it has been written into the ISA manual draft (merged in May), is currently integrated into the Zvt family of the Vector Matrix Extension (VME) and the bulk dot-product extensions Zvdota/Zvbdota, and an error evaluator has been open-sourced. Sources: damo-rv-priv-ats, AME test vector library, MarkTechPost

Open-Source Cores and Ecosystem Projects: OpenHW Continues, Simulation and Tooling Niche Ecosystem Active

  • OpenHW Foundation: A 168-hour check shows pushes within the window to five repositories—cvw, cva6, cv-hpdcache, cv32e40p, and uap (cva6 and cvw remained active from period end through the check)—continuing the design and verification cadence of the CORE-V series; the organization’s repositories have migrated from openhwgroup to openhwfoundation.
  • Others: The Rust-written memory-safe kernel Asterinas 0.19.0 introduced an initial DRM subsystem for the first time and got X.Org running on top of a modesetting driver and Mesa LLVMpipe, while adding an AArch64 target (alongside the existing x86_64, RISC-V, and LoongArch64); riscv.org published a piece on an LFX mentorship program participant’s work, whose self-developed ISA Configuration Builder and Extension Sandbox automatically classify 1,867 instructions into 83 ISA subsets, reducing the error cost of configuring custom cores and custom extensions. Sources: openhwfoundation, Phoronix Asterinas, riscv.org blog

III. Operating Systems and Distributions

openRuyi: Daily Firmware Updates, Main Repo Platform and Security Dual-Track Maintenance

  • Firmware line (ruyifirmware/edk2-ruyi): Three consecutive releases on 10-13, 10-14, and 10-15, with K3 platform support as the main thread (GOP and EDID, PCI option ROM, RTL8127 NIC, x64emu variant, dual-cluster CPU mode selection, System Information and SMBIOS DRAM reporting, A100-only interrupt routing fix), plus new raw SPI flashing installation documentation and a “selectable UEFI driver emulation” packaging option.
  • Main repo: Multiple batches of SPECS updates within the window—Go 1.27.2 and OpenSSL 3.6.5, docker-cli packaged separately (10-10); full upgrade of 19 KDE Plasma 6.7.5 packages plus addition of AGENTS.md for AI coding agents (10-12); Mesa 26.2.4 upgrade and PowerVR optimization backports (10-14); security batch for cups, python-nltk (CVE-2026-81726), capstone 5.0.9, llama-cpp 0.4.1, multipath-tools 0.15.1, and spdk bdevperf packaging (10-15).
  • Supporting tools: Version inspection tool lookout released v0.2.5 (fixes filters affecting search results, displays computed versions for release tasks, CI integration coverage reports), and advanced automatic discovery of Go components from trusted-source tags and NVD security identity verification; kiwi-image added a GitHub Action build script for riscv64 images; ceph-ci, kernel-team-tools, MultiArchUefiPkg and other repos also received pushes during the same period.
  • Dual-source verification conclusion: The openRuyi official news page for this period (including the 10-17 recheck) still has no new version announcement; the latest remains the 2026.09 release; per the monthly cadence, the next version has entered the observation window, and the next issue should focus on verifying toolchain and kernel versions, RVA23 integration, and changes to the AI/cloud-native software stack. Sources: openRuyi official news, openRuyi main repo

RevyOS: Two Rounds of Batch Configuration on the 7.3 Kernel Branch, Multi-Vendor Platforms Consolidated at Once

  • Baseline sync (10-11): 50 commits in a single window on the kernel repo, with configuration batch-synced to the 6.17.11 baseline, adding platform configs for K1/K3, DP1000, SG2042/SG2044, TH1520, etc., enabling Rust, PowerVR DRM, NTSYNC, K3 display controller and UFS, SPACEMIT PM domains, and FUSB301 Type-C controller; device tree enables GPU and USB3 for K3 Pico ITX and USB for Milk-V Meles; CI adds cross/native builds.
  • Platform expansion (10-12): A second round of 20 commits adds ESWIN EIC7700 support (ARCH_ESWIN, DWMAC_EIC7700 NIC, PINCTRL_EIC7700, and enables DRM_AST) and DP1000 config; enables USB2 for K1 (Banana F3); enables the Type-C protocol stack (TYPEC/TCPM/UCSI/FUSB301/DP_ALTMODE/PHY_SPACEMIT) and RTC_DRV_EFI, PWM fan sensor; adds linuxboot config.
  • 7.3 branch consolidation (10-15): 20 batch configuration commits merged into the revyos/7.3.y branch—dozens of items including K3 (UFS/DC), K1 (Banana F3 USB2), EIC7700 (ARCH_ESWIN/DWMAC/PINCTRL), TH1520 USB modules (including RESET_GPIO), USB Type-C and display links, DRM_AST, ERRATA_PICOHEART, with the 8250 serial runtime port count adjusted to 6. On the distribution side, platform support for domestic SoCs has essentially been consolidated this week. Source: revyos/linux

Ubuntu 26.10: RISC-V Desktop Image Lands, K3 Gains Official Support

  • Release facts: 26.10, released on 10-15, provides ubuntu-26.10-desktop-riscv64.iso (4.0 GB, labeled for RVA23 and above processors), live-server-riscv64 (1.6 GB), netboot tarball, and preinstalled-server (1.3 GB); SHA256SUMS and signatures updated at 10-15 09:38. This is Ubuntu’s first desktop image for RISC-V, and Canonical simultaneously provides official support and installation documentation for the SpacemiT K3 Pico-ITX (requires flashing newer firmware first; can be installed to internal UFS or NVMe).
  • Testing and boundaries: A week before release (10-12), NeoTeo published a “what to test” guide, followed by Chinese media; the full desktop experience targets RVA23-class hardware (Milk-V Jupiter 2, DeepComputing DC-ROMA, SiFive HiFive Unmatched, etc.), and real-hardware boot requires bringing your own first-stage bootloader and device tree; experimental Xubuntu Minimal targets QEMU (loading under pure GNOME emulation takes over 30 minutes). The next issue should track installation feedback and first-release defects. Sources: Ubuntu cdimage, NeoTeo testing guide

Other Signals on the Distribution Side

  • Kernel and hardware enablement: RevyOS and openRuyi both focused on K3’s UFS, display, Type-C, and GPU in the same week, forming a three-way resonance with Ubuntu’s official K3 support—K3 has in effect become the primary validation platform for RISC-V desktop and edge distributions in the second half of 2026.
  • openEuler: None of the five daily reports in this period included openEuler-related items, so this section does not cover it; if version or RISC-V SIG developments appear later, they will be listed separately in the weekly report.

IV. Chips and Hardware

Domestic Server Chips and SoCs: Mass Production Cadence Advances in Step with Firmware Support

  • BlueCore Computing LX500: 48-core heterogeneous (32P + 16E) plus an on-die 75 TOPS INT8 AI engine, supporting RVV 1.0 and RVA23, PCIe 5.0, and CXL 2.0; taped out and brought up in February 2026, mass production of the Lenovo Wentian WR5219 G5 rolled off the line in July, and it has been adapted to China Mobile’s BC-LINUX and completed inference validation for Kimi K2.6 and Qwen3.6-35B (see this week’s headlines for funding details).
  • Sophgo: A concentrated release of SG2042 platform software packages — SDK v20261012 and EDK2 v1.5.0 (10-12), with SDK v20261015 released again at the end of the period; the zsbl zero-stage bootloader restructures platform organization into a two-level “subsystem × application” model (PLAT_SG2044 / SG2044_MP / SG2044_MP_ZSBL, with the platform level retaining only shared headers and memory maps, and a platform-level Kconfig introduced), and PLAT_BM1690TP is renamed PLAT_BM1690; server MCU/BMC firmware merges RHS12 board compatibility into the HD12 motherboard, along with the C2C interconnect link, 64GB DDR support, and MCU/BMC boot logs exposed over I2C (firmware bumped to 14).
  • SpacemiT K3 Modularization: Zhongda Technology launches the SMSM_K3_A fully domestic mini COM-E (Type 10) module — 16-core homogeneous fused architecture, 60 TOPS AI compute, 32GB LPDDR5, 16MB NOR + 128GB UFS, 100% domestically sourced components, supporting Bianbu / Buildroot / Kylin V10, industrial-grade -40 to 70°C, typical power consumption 13W, with llama.cpp (capable of running Qwen3-30B) plus YOLO, VLM, and ASR/TTS support on the AI side, targeting AI edge gateways, industrial servers, and embodied robots.
  • Sources: sophgo/bootloader-riscv, zsbl platform restructuring, mcu HD12 firmware, Zhongda K3 module

MCUs and Development Boards: Mixed-Signal MCUs in Mass Production, Edge AI SBCs, and Linux-on-MCU

  • HPMicro HPM5100 series enters mass production: The debut HPM5151 features a 400 MHz RISC-V core, 416 KB SRAM + 1 MB Flash, and integrates four 16-bit ADCs, four op-amps, and four analog comparators; interfaces include USB 2.0 OTG (with built-in PHY), CAN FD, and 32 PWM channels, with hardware floating point and DSP instruction support; QFN48 / QFN68 / LQFP100 are priced at RMB 15.60 / 16.90 / 19.50, the EVK at RMB 258, and SDK 1.13.0 already supports it alongside SEGGER Embedded Studio for RISC-V.
  • Orange Pi O1 launches: Based on Sophgo BM1688 (8-core Arm Cortex-A53 @1.65 GHz + RISC-V C906 co-processor @1.2 GHz), 16 TOPS@INT8, supporting 16-channel 1080p decoding / 10-channel encoding, 8/16 GB LPDDR4X, M.2 NVMe, dual Gigabit Ethernet ports, and Wi-Fi 6E, priced at $195 / $325 — Sophgo’s AI SoC ecosystem extends downward from modules and server form factors into general-purpose SBC channels.
  • Espressif ESP32 family: The ESP32-S31 gets its first third-party development board (VIEWE 4.3-inch 800×480 module, $38.99, requiring ESP-IDF master with --preview); the official esp-linux-bsp merges “configurable flash layout,” and the community esp32-s31-linux releases v0.3.1 (Linux 7.2 + OpenSBI 1.9 running on 16 MiB PSRAM, adding Bluetooth and 802.15.4 RCP); the multimedia framework ESP-GMF v1.1 and the safety self-test library esp-bist v1.1.0 (targeting IEC 60730 Class B, covering RISC-V chips including C3/C5/C6/C61 and H2/H4/P4) are released in succession. On the consumer side, Meta open-sources the Muse Gadgets SDK and builds five thousand Muse Home Link units based on the ESP32-C5, a direct case of RISC-V wireless MCUs entering big-tech consumer AI hardware.
  • Other development boards: M5Stack ToughC5 (waterproof ESP32-C5 industrial IoT controller, $49.9) and Wireless-Tag WT32P4C5-43S (ESP32-P4 + C5 dual-chip 4.3-inch touchscreen, from $32) launch the same week.
  • Sources: CNX: HPM5100, CNX: Orange Pi O1, esp-linux-bsp, esp32-s31-linux v0.3.1

IP, Startups, and Capital Movements

  • Ubitium (Germany): Closes a $14 million new seed round (led by Ibex Investors, with participation from OpenOcean, KBC Focus Fund, Runa Capital, and Inflection, for $18 million cumulative), advocating replacing the patchwork “DSP + NPU + CPU” stack with a single reconfigurable RISC-V processing array; the first chip UB108 (256 processing units, Samsung 8nm) has taped out and validated three workload classes — signal processing, AI inference, and real-time control — on the same array, while the first commercial chip UB410 (4,096 processing units) is slated to deliver evaluation units in 2027, with initial customers focused on perception-layer applications such as radar and audio.
  • Yanxin Technology (Beijing): 36Kr reports that it fuses symbolism, behaviorism, and connectionism into a “general embodied intelligence brain” pre-packaged and hardened into RISC-V chips, offering plug-and-play solutions to robot makers. Caveat: the company was founded in January 2025 with RMB 1 million in registered capital and remains in early validation and fundraising roadshow stages; technical details, performance metrics, and mass production timelines are all undisclosed, so this entry is for sector observation only.
  • Industry data: SHD Group’s “2026 RISC-V Market Report” projects 35.9 billion RISC-V SoC shipments by 2031, a CAGR of about 31.7%; another industry assessment suggests RISC-V’s share of industrial edge chip shipments could rise from under 7% to over 24% by 2030 (DAMO XuanTie C950 and Nuclei NA900 have passed ASIL-D, while ESWIN R500A has passed ASIL-B). Meanwhile, trial coverage of Qualcomm v. Arm brought RISC-V data-center maturity into the courtroom conversation, with the discussion confined to enterprise data centers and not contradicting existing embedded/edge deployments.
  • Sources: Ubitium press release, 36Kr: Yanxin Technology, Bisinfotech, 36Kr: Industrial Edge

Vendor Software Support Cadence

  • Espressif: Organization push repositories climbed day by day within the window, 25→38→46, making it the most active organization watched this week; esp-vision adds nano track target tracking and sensor IPA statistics and merges an LCD touch driver, esp-idf completes a RISC-V trace snapshot refactor and several BLE/TWAI fixes, esp-sr updates precompiled libraries, and esptool fills in the ADC weight eFuse fields for the ESP32-S31.
  • Sipeed: Logic analyzer software SLogic ships v2.1.0 → v2.2.0 → v2.3.0 within a week — fixing Windows RAW_IO throughput, adding SLogic16U3 model adaptation and USB link rate detection, introducing a shared acquisition engine (0% trigger position, rate-limited per link), and adding in-browser firmware OTA (SLogic16U3/32U3); the MaixPy mainline merges 3 commits (including RVV documentation and examples).
  • SpacemiT: xslim static quantization supports skipping by operator type/name, mpp fixes video decode buffer reporting and switches to the MIT license, the vision model library merges RT-DETR and CosPlace, the reinforcement learning model library adds an MNN backend, and a dozen-plus docs repositories are updated in bulk.
  • Sources: espressif commit history, SLogic release-2.3.0, spacemit-com organization repositories

V. Open-Source Community and Industry Events

RVSC2026: Opens October 18 in Shenzhen, All Pre-Event Materials and Co-Located Events Ready

  • Time, Venue, and Scale: The 6th RISC-V China Summit is set for October 18–20 at the Shenzhen Convention & Exhibition Center (Futian), with an expected 3,000+ professional attendees and 150+ exhibitors and research institutions; Turing Award winner David Patterson and RISC-V International CEO Andrea Gallo will attend, with DAMO XuanTie, ESWIN, SpacemiT, Lanxin Computing, Tenstorrent, and others showcasing their work; summit chair Tan Zhangxi, vice chairs Meng Jianyi and He Ning.
  • Agenda Structure: 10-18 features Member Day / Workshops / Community Exchange (Narcissus Hall), a GPGPU session (organized by Tsinghua), an AI for RISC-V session, and a XiangShan processor session; 10-19 features the opening ceremony and main forum (Plum Blossom Hall); 10-20 features seven sub-forums (AI Computing, High-Performance Computing, Software Ecosystem, Embedded, Chip Design & Verification, Industry-Academia Collaboration & Innovation, Automotive Electronics), and 10-21 is RISC-V GBA / HK Day (City University of Hong Kong). Late-cycle agenda updates: the 10-20 RAG session talk is finalized as “Unlocking Cloud AI: Accelerating RAG Workloads with RISC-V CPUs” (Alibaba DAMO Academy), the XiangShan HPC session adds a joint speaker, and the DiffTest-H talk is updated to “30 MHz.”
  • Pre-Event Materials: 23 sponsor/exhibitor promotional posts went live in one batch on 10-13, followed on 10-14 by an updated ESWIN post and a roundup post covering 28 companies; the exhibition floor plan (Orchid Hall hosts open-source community booths D01–D34 and poster booths H01–H84), route and hotel guides, and organizing team have all been published; 13 commits to the summit website source repository during the window.
  • Five Co-Located Events: SpacemiT’s first Developer Conference (10-17 afternoon, Shenzhen Institute of Science and Technology Innovation, focused on the K3 series and Bianbu OS), the OpenAnolis RISC-V Ecosystem Co-Building Sub-Forum (10-18 afternoon), the “One Student One Chip” Open-Source Chip Tapeout-Ready Design Tutorial (10-19 afternoon), the XiangShan Ecosystem Conference (10-20 all day), and the AME Matrix Extension Technology Workshop (10-20 afternoon, DAMO Academy).
  • Automotive-Grade Toolchain Signal: Zhaosong Technology has announced a 10-20 13:45 talk in Rose Hall 2, “From Compiler to Runtime Library — Practical Implementation of RISC-V Functional Safety Toolchains,” aligned with the summit’s Automotive Electronics sub-forum; functional safety toolchains remain a key supporting element for RISC-V’s entry into vehicles. Sources: Summit Agenda, Exhibitor Roundup, Co-Located Events

XuanTie: Industry Technology Workshop in Beijing on October 22

  • DAMO XuanTie has released a preview for the “RISC-V Industry and Technology Workshop · Beijing Stop”: October 22, 14:00–17:15, Renaissance Beijing Zhongguancun Dongsheng Science and Technology Park Hotel, with three tracks covering next-generation high-performance RISC-V processor core architecture evolution, system-technology co-optimization (STCO / Multi-Die / high-performance software stack tuning), and computing architecture in the agent era (from AI chips to Agent chips); registration is subject to approval. Together with the 10-20 summit AME workshop, this forms the week’s peak in XuanTie event density.
  • Source: XuanTie RISC-V Industry and Technology Workshop · Beijing Stop Preview

International Community and Media Perspectives

  • riscv.org: In addition to the XuanTie Meng Jianyi interview (see this week’s top stories), the site also published an LFX Mentorship participant’s ISA Explorer practice summary (ISA configuration builder and extension sandbox).
  • The Next Platform: Published a long-form interview with zeroRISC founder Dominic Rizzo (early OpenTitan lead), whose core argument is “if there’s an open-source ISA, why not open implementations” — zeroRISC builds on a RISC-V-based OpenTitan root of trust to deliver a complete silicon + software + cloud management solution for data centers, ICS/OT, and IoT.
  • Industry Analysis: Bisinfotech analyzes how AI workloads are accelerating RISC-V adoption (the bottleneck shifting from clock frequency to data movement, memory hierarchy, and interconnect efficiency, with RISC-V well suited to control and system management roles in heterogeneous SoCs), and emphasizes hardware-software co-design and pre-silicon verification; a 36Kr long-form piece examines head-to-head competition among x86/Arm/RISC-V at the industrial edge, arguing the key battleground is toolchains, RTOS, and certification regimes.
  • Community Projects: Meta’s open-sourcing of the Muse Gadgets SDK (Apache-2.0, including an ESP32 device SDK and a Linux device SDK) is this week’s representative case of “a major vendor using RISC-V MCUs as the AI hardware foundation”; update cadence for Sipeed, Espressif, and SpacemiT open-source repositories was covered in Section 4.
  • Sources: The Next Platform, riscv.org Blog, CNX: Meta Muse Gadgets SDK

VI. Trend Watch

  • RVA23 has moved from “specification text” to “a determinable fact,” and a three-part closed loop took shape this week: eight kernel profile bits have already entered riscv/for-next (v9 in flight), the single-query interface has been covered by mainstream media, and Ubuntu 26.10 uses RVA23 directly as its image baseline and explicitly states “RVA23 and above.” This means “is this machine RVA23” will go from item-by-item comparison to a single system call, with glibc building by profile plus hwcaps automatic library selection as the next key milestone. If this chain proceeds on schedule, the binary fragmentation problem in RISC-V software distribution will have a systematic answer for the first time.

  • The high-performance narrative has split into two routes, and both gained interim evidence this week: one is “the CPU itself carries AI” — DAMO XuanTie C950, in a 64-core configuration with no dedicated accelerator, runs a 27B model at over 30 tokens/s decoding, relying on system-level coordination of quantization, matrix instructions, on-chip memory, and bandwidth; the other is “CPU + on-die AI engine” — BlueCore LX500 races toward mass production with a 48-core + 75 TOPS single-chip fusion. The former proves the upper bound of feasibility, the latter proves the commercial path, but both lack third-party benchmarks and full-system power data — the evidence most worth adding in the next stage.

  • Distribution competition is shifting from “can it boot” to “platform breadth + firmware experience + security maintenance”: openRuyi has turned firmware into a daily-update cadence (K3 dual-cluster CPU mode selection has already reached the SPI persistence and coreboot read layers), RevyOS consolidated platform configurations for K1/K3/EIC7700/TH1520/SG2042/SG2044 in one pass within two weeks, and Ubuntu participates directly with an official desktop image plus official K3 support. All three treating K3 as their primary validation platform in the same week shows that domestic SoC distribution support has moved from “patch-style adaptation” into “productized delivery.”

  • The on-device Agent stack has become a new track in the RISC-V software stack, but is still single-platform first: SpacemiT went within one week from “centralized repo creation” to a “full-stack open source + capability distribution loop” (GUI/runtime/memory/offline voice/security + APM/Agent Hub/Skills images), and added RGBD launch commands to its humanoid robot MuJoCo simulation. This combination is a first on RISC-V; the risk is that all components currently support only K3 and Bianbu 4.x, so cross-chip portability and the scale of outside community contributors are points to watch.

  • Capital and mass production appeared in the same week, but “funding amount” and “performance delivery” still need to be viewed separately: BlueCore’s nearly RMB 2 billion Series B and Ubitium’s $14 million seed round landed in the same period; the former already has full-system mass production and carrier system adaptation, while the latter is still in tape-out validation and the 2027 evaluation-sample stage. Domestic RISC-V server chips are moving from “power-on” to “mass-production validation”; the next hard metrics are orders, third-party performance reviews, and software-stack maturity, not valuation.

  • Ecosystem event density hit a year-to-date high, and a batch of technical disclosures should follow summit week: RVSC2026 (Oct 18–20) overlaps with the SpacemiT Developer Conference (Oct 17), the OpenAnolis RISC-V sub-forum (Oct 18), the XiangShan Ecosystem Conference (Oct 20), the AME Matrix Extension Workshop (Oct 20), and the XuanTie Beijing stop (Oct 22) — five events in one week covering four main threads: compilers, matrix extensions, automotive-grade toolchains, and on-device Agents. The next weekly report should redo a fact check centered on on-site summit materials, especially the progress status of the AME specification and each vendor’s chip timelines.

Appendix: Sources and Verification Notes

Sources (5 daily briefs)

Date Window Highlights of the day
2026-10-12 (Mon) 10-10 09:20 ~ 10-12 05:00 (44 hours) Back from LPC26: 8 RVA23u64 kernel profile bits merged into riscv/for-next
2026-10-13 (Tue) 10-12 05:00 ~ 10-13 05:00 SpacemiT llama.cpp standalone ggml-spacemit backend, v0.2.1
2026-10-14 (Wed) 10-13 05:00 ~ 10-14 05:00 Blue Core Computing nearly RMB 2 billion Series B financing
2026-10-15 (Thu) 10-14 05:00 ~ 10-15 05:00 SpacemiT Bianbu AgentOS full stack publicly unveiled
2026-10-16 (Fri) 10-15 05:00 ~ 10-16 05:00 XuanTie C950 runs 27B without a discrete accelerator, riscv.org interview

The five daily briefs contain roughly 60 items in total; all 5 working days in this period have a daily brief, with no missing dates.

Verification approach

  • GitHub watched organizations and key repositories (168-hour window): DAMO XuanTie XUANTIE-RV 3 repos pushed (damo-rv-priv-ats, thead-extension-spec, damo-rv-ats), ESWIN eswincomputing 1 repo (riscv-matrix-gemm-vectors), Sophgo sophgo 12 repos, Nuclei Nuclei-Software 4 repos, Espressif espressif 93 repos, SpacemiT spacemit-com 33 repos, spacemit-robotics 6 repos, Sipeed sipeed 12 repos, revyos 2 repos, OpenHW 5 repos, openRuyi-Project 17 repos, Radxa Linkr 2 repos; key repositories XiangShan / NEMU / GEM5 / difftest / XSCache all had pushes within the window.
  • Additions from period end to verification time: spacemit-robotics’ unitree-go2 and realtime-link were pushed on the morning of 10-16 (after the 05:00 cutoff of that day’s brief); this weekly report only lists them in the verification table without content judgment; cva6, cvw, XiangShan, NEMU, GEM5 still had pushes on 10-17 and are deferred to the next period for observation.
  • openRuyi dual sources: within the GitHub repo window, three firmware-line releases and multiple batches of SPECS updates in the main repo were all verified; a re-check of the official news page on 10-17 still shows no new version announcement, with the latest being 2026.09.
  • Ubuntu 26.10: directly checked the official cdimage release directory and confirmed ubuntu-26.10-desktop-riscv64.iso exists (4.0 GB), with the image described as “for 64-bit RISC-V RVA23 and above processors”; the same batch includes riscv64 server, netboot and preinstalled images, and SHA256SUMS was updated at 10-15 09:38.
  • RISC-V International member website sweep: across the five daily briefs, 391 member company websites were swept in total, with 49 to 229 sites changing pages per day, all routine marketing and university updates; no substantive product/financing/architecture developments eligible for inclusion were detected; 65 to 68 sites failed to fetch each day (mostly domestic sites and anti-scraping sites), which does not block the conclusions.
  • RVSC2026 official website and source repo: the five daily briefs continuously monitored the official website sitemap, key pages and source repo; pre-event updates (exhibitor posts, agenda, floor plan, co-events, finalized talk titles) were all checked daily.

Scope notes

  • Window differences: this weekly report covers 10-12 to 10-16, but the 10-12 daily brief window is 44 hours (starting from 10-10 09:20), so this report includes some items from 10-10 to 10-11 (such as the RevyOS 6.17.11 baseline sync, the LPC26 attendance notes, openRuyi Go/OpenSSL updates, and Sophgo zsbl v3.2.1); actual dates are noted item by item in the text.
  • Single media source and vendor self-reported figures: the Yanzin Technology item comes from a single 36Kr report and the company is at an early stage; the performance and compute figures for Ubitium and Blue Core Computing are company statements; the 27B inference speed of XuanTie C950 is from a team interview; none of the above has been validated by third-party benchmarks.
  • Branch-level pushes: some repositories (difftest, GEM5, NEMU, revyos, and several spacemit-com repos) mainly had feature-branch pushes within the window, with no new merges to the main branch; the text distinguishes “main-branch merge” from “branch progress”.
  • Items not included: none of the five daily briefs in this period contained openEuler-related items, so Section 3 does not include openEuler content; the Ubuntu 26.10 release information was added by directly checking the official image site for this report (the 10-16 daily brief did not include it due to the window cutoff and relevance judgment).

Main references