Reporting period: September 30, 2026 (Wednesday) to October 7, 2026 (Wednesday), National Day holiday special summary period (8 days); 10-01 to 10-07 was the National Day holiday, with daily reports suspended. Material is based on the 09-30 daily report, with holiday-window developments supplemented through public sources and repository verification (coverage through publication before noon on 10-08) Sources: RISC-V Global Developments Daily (09-30 issue); GitHub organizations and key repositories 216-hour window review (including Atom fallback); openRuyi dual-source verification; member company website inspection (391 companies); Google News Chinese and English multi-query 9-day window search (approximately 86 candidates) Editorial note: This period covers four thematic dimensions: instruction set and architecture ecosystem, operating systems and distributions, chips and hardware, and open-source community and industry activities; media-only claims and corporate press releases during the holiday are noted in the main text

1. This Week’s Highlights

  • openRuyi 2026.09 officially released: RVA23 support advances on three fronts, cloud and storage stacks expanded (09-30): The RISC-V rolling distribution led by the Institute of Software, Chinese Academy of Sciences, released its September edition on schedule. RVA23 improvements cover three fronts—compilation correctness (GCC 16.2 backports BCLR fix, resolving non-terminating m &= m - 1-style loops under zbb/zbs and Mesa graphics crashes), data plane (DPDK 25.07 built with rva23u64 enables RVV vector paths, covering lpm/fib/node/ACL table lookups), and containers (seccomp allows riscv_hwprobe; on SpacemiT V100, OpenSSL detects Zvkned/Zvknhb/Zvksed vector crypto extensions, and zlib-ng enables Zbc crc32). The distribution adds Cloudpods 4.0.3 multi-cloud platform, SPDK 25.09, and Ceph snapshots; it includes the NVK open-source NVIDIA Vulkan driver for the first time and upgrades the Go 1.27 build environment. GPG verification is enabled by default in the repository, and 15 groups of CVEs including expat, jq, vim, imagemagick, pcre2, runc, and crun are fixed in bulk. An experimental RVA20 version (Server/Container/Desktop) is also provided. Source: openRuyi 2026.09 Release

  • “First RISC-V stock” ESWIN Computing wraps up IPO subscription: ~4.5x oversubscribed, expected listing on 10-09 (10-01 ~ 10-07): Beijing ESWIN Computing (01256.HK) launched its global offering on 09-28 (1,570,204,000 H shares, offer price HK$1.48–1.59, raising up to ~HK$2.5 billion, 2,000 shares per lot), with subscription closing on 10-06. As of the afternoon of 10-05, margin financing reached ~HK$1.37 billion, roughly 4.5x oversubscribed relative to the public offering size; 9 cornerstone investors subscribed a total of ~HK$1.16 billion (including Hefei Construction Investment, Greater Bay Area Homeland Investments, ORIX, etc.). The company disclosed 620+ IP modules, 20+ series of RISC-V cores, 1,740+ patent applications, 150+ products, and 220 customers; approximately 35% of proceeds go to new chip development and 30% to the RISAA (RISC-V+AI) platform. Sources: Securities report (10-06), Guandian (10-05), Sina Finance (10-01)

  • International narrative intensifies around RISC-V mainstreaming: MIPS collaboration with China, 25% share, and SPMP standard (10-03 ~ 10-06): During the holiday, multiple media outlets reported intensively—an SCMP feature said MIPS is advancing RISC-V standardization with Chinese companies “as never before” (CTO Yankin Tanurhan stated at a September media briefing in Shanghai; the company previously completed ARC integration and anchored itself in RISC-V Physical AI); digitimes followed up on 10-06 with “MIPS deepens RISC-V ties with China”; MyDrivers/Sina on 10-05 summarized data: RISC-V International institutional members come from 37 countries, with 89/87 from China and the US respectively (~42% combined); Chinese Academy of Engineering academician Ni Guangnan disclosed at the 2026 XuanTie RISC-V Ecosystem Conference that RISC-V has captured 25% of the global processor market, with global shipments exceeding 10 billion units; the report also mentioned that the privileged-state physical memory protection (SPMP) instruction set standard led by a Shanghai Jiao Tong University team was approved for inclusion in the RISC-V ISA standard on 08-31. Sources: SCMP, digitimes, MyDrivers via Sina

  • Efinix releases Sapphire RV64: 64-bit RISC-V soft core brings Linux into FPGAs (reported 10-03): Configurable 1 to 4 cores, 7-stage pipeline (RV64IM, optional A/F/D/C/Zba/Zbb/Zbs/Zicbom), 4KB to 512KB on-chip RAM, multi-way L1 cache and optional 64 to 512KB L2, optional SV39 MMU, supporting DDR3/HyperRAM/LPDDR4x (up to 3,200Mbps), retaining custom instruction capability to offload signal, image, and AI compute; covers Titanium, Topaz, and Trion T20 and above devices, with software flow requiring Efinity 2026.1 or later. It forms a “hardened + configurable” dual track with the 32-bit quad-core RISC-V block already hardened in Ti375 devices. Sources: LinuxGizmos, Efinix product page

  • ESP32-S31 official Linux branch enters developer preview (10-07): i-programmer reported that Espressif’s official espressif/linux repository added an ESP32-S31 support branch (integration/v6.18-esp32s31, marked developer preview, not recommended for production yet); the S31 is a dual-core RISC-V (320MHz) with two-level page table address translation and privilege-level isolation, providing the hardware foundation for running full Linux on an MCU-class chip. The community also has grieferpig’s unofficial 6.18 port (with bundled binaries, device tree customization, libgpiod, and BusyBox). Memory size and the lack of a GPU remain the main limitations; the “official fork” itself is a roadmap signal. Sources: i-programmer, espressif/linux, unofficial port

  • XiangShan doesn’t stop for the holidays: feature branches advance on multiple fronts into the morning of release day (09-30 ~ 10-08 morning): The main repository’s default branch saw no new merges during the holiday window (the latest being the bosc IOMMU integration #6560 on 09-28), but feature branches remained active—my-crob-difftest completed the CROB slot sharing fix and advanced to 10-07; feat-mmu-h-tlb-compression fixed duplicate memory broadcasts in PTW after H-TLB sector compression (10-03); frontend-bt completed funcov runtime integration and merged with mainline (10-08 morning); victim-btb continued mbtb refactoring (through 10-08 morning). The simulation chain also converged: NEMU landed a CSR shadow invalidation fix (#1237) and AME matrix hash comparison (#1238), and difftest added matrix result hash reporting (#978). Sources: XiangShan branches, NEMU, difftest

  • SpacemiT robotics stack continuously reinforced over the holiday: operator pipeline and on-device voice take shape (10-01 ~ 10-03): humanoid_linglong added operator startup and guidance services (#17), fixed-base arm demo configuration files (#18), and split startup services by control configuration (#19); humanoid_common added operator services and remote clients (#22) and fixed-base trajectory control (#23); omni-agent connected on-device KWS wake-up with SPV full-duplex software AEC (#19, with automatic model download); model-zoo-kws launched a streaming wake-up engine and added confusable-word rejection (10-02). Sources: humanoid_linglong, omni-agent, humanoid_common

  • Allwinner V861 board goes on retail sale: first V861-based Avaota F2 listed (reported 10-02): CNX updated its report confirming the Avaota F2 is now on sale on AliExpress ($51.59)—dual-core XuanTie C907 (up to 1.4GHz, RVV 1.0) + XuanTie E907 (800MHz), 128MB on-chip DDR3, 1 TOPS NPU, 4K H.265 encoding, PTZ motor control, and dual MIC plus speaker; hardware materials are open-sourced under CC0 (schematics, PCB, and Gerber all available), with the software side following the Allwinner Tina SDK (OpenWrt 21.04 branch + Linux 6.6). Sources: CNX Software, AvaotaF2 hardware repository

II. Instruction Set and Architecture Ecosystem

XiangShan Processor: Default Branch Silent Over the Holiday, Feature Branches Advancing on Multiple Fronts

  • Default branch and review queue: The Kunminghu default branch saw no new merges during the holiday window; the latest is the 09-28 bosc IOMMU integration (#6560). Backend fix PRs opened on 09-29 (#6649 preserving the FEX0 output slot for x0 conversion, #6652 vector std issue window, #6653 inverting the StdExeUnit out-of-bounds condition) await review progress after the holiday.
  • Feature branches (development lines spanning the holiday): my-crob-difftest completed two CROB fixes (single-slot multi-member sharing of robIdx/uopIdx, restoring mainline compatibility and slot retirement, 09-30), and on 10-07 cleaned up redundant bit widths in fusionNum/MaxUopSize; feat-mmu-h-tlb-compression, building on H-TLB sector compression (09-29), fixed duplicate memory broadcasts in HPTW responses (10-03); frontend-bt completed native Toffee coverage runtime integration and funcov cycle snapshot optimization (09-30), merging with mainline on the morning of 10-08; victim-btb advanced mbtb renaming and comment refactoring (through the morning of 10-08). Branches such as test-mbtb, timing-fense, and fix-flt have seen no new commits since their last entries on 09-29.
  • Source: XiangShan branch list, default branch commit history

Simulation and Verification Chain: AME Matrix Hashing Runs Through NEMU and difftest

  • NEMU: On 09-30 fixed CSR shadow copy invalidation during implicit state updates (#1237); on 10-03 added AME matrix hash comparison (#1238); on 10-04 added support for reading large zstd checkpoint images (#1239).
  • difftest: On 10-01 fixed MinimalMatrixConfig validator compatibility (#976); on 10-07 added AME matrix result hash reporting to DiffTest (#978)—forming a closed loop with the NEMU side for “comparable matrix extension results.”
  • GEM5 (XiangShan branch): No new commits during the holiday window (the previous batch was the apf-align prefetch alignment line).
  • Observation: AME (matrix extension) verification has moved from boundary-semantics fixes into a “comparable result hashing” phase, laying the groundwork for simulation consistency of matrix instructions.
  • Source: NEMU, difftest, GEM5

Architectural Testing and Toolchain Ecosystem: XuanTie ATS Continues, mold 3.0, and a Small Simulation Ecosystem

  • XuanTie architectural test suite: damo-rv-priv-ats refactored the Hypervisor suite’s common infrastructure on consecutive days, 10-05 and 10-07 (pushing duplicate helpers down into common, centralizing suite-level shared facilities); damo-rv-ats updated vector floating-point test cases on 10-04 (#6).
  • Toolchain: mold 3.0 high-speed linker released (rewritten in Rust), fixing RISC-V relocation and TLS-related issues (reported 10-05).
  • Small simulation ecosystem: rv32emu’s Buildroot ext4 root filesystem generation pipeline (included 09-29); BasisResearch’s bare-metal verification practice for the Sail RISC-V model (Lua/OCaml, included 09-29).
  • Source: damo-rv-priv-ats, damo-rv-ats, mold 3.0 report, rv32emu

Open-Source Cores and Confidential Computing: CVW’s 20 Commits Over the Holiday, CoVE PoC Open-Sourced, GSys-LibreCore Debuts

  • CORE-V verification model cvw: 20 commits within the window (latest merge #1924, 10-06), covering a set of fixes for CBO cache block operation permissions, CSH script fixes, WFI back-to-back timing rollback, deferred exception, and spill bytemask.
  • CoVE (Confidential VM Extension): cove-dp1-poc under the DAMO XuanTie GitHub organization released v0.2.0 on 09-30 (the initial open-source version, including a TSM reference implementation written in Rust and a QEMU RV64GC demo environment); on 10-01 the component was renamed from cove_tsm_poc to xvm2.
  • GSys-LibreCore: A Linux-class configurable out-of-order/in-order multicore plus AI processor design derived from CVA6 was released on HN (09-30); the RTL uses a combination of source-available licenses such as CERN-OHL-S, with an MIT toolchain, and a commercial license is also offered.
  • Source: cvw, cove-dp1-poc, GSys-LibreCore

III. Operating Systems and Distributions

openRuyi: Official release 2026.09; code quiet over the holiday, new batch of commits starting the morning of 10-08

  • Release landed (09-30): The September release shipped on its monthly cadence (highlights in Top Stories: RVA23 three tracks, Cloudpods 4.0.3, SPDK 25.09, Ceph snapshots, NVK, Go 1.27, GPG verification with 15 CVE groups, RVA20 experimental edition); at the time of the 09-30 daily check the release had not yet shipped, and it was confirmed via two sources within this period.
  • Kernel track: linux 7.2.6 and linux-lts 6.18.54 landed with the release (included from 09-29); the accompanying k3firmware saw no new version over the holiday (latest remains 20260929).
  • First batch of commits after the holiday (morning of 10-08): concentrated SPECS updates — python upgraded to 3.14 (including the rpm-macros default version switch and setuptools/packaging/flit-core bootstrap fixes), dotnet10.0-bin bumped to 10.0.110, clang-wrap/llvmir-converter updated to 20260923, ceph dependency cycle broken (librgw merged into ceph-common).
  • Sources: openRuyi 2026.09 release, openRuyi repository commits, k3firmware Releases

RevyOS: Zhizhi Computing A210 (Melon Pi) support batch lands (included 09-29)

  • revyos/linux merged a batch of patches: a new Zhizhi Computing A210 entry in MAINTAINERS, A210 thermal and watchdog device trees, PWM reusing the TH1520 driver, Melon Pi V2 audio routing — kernel support for the A210 platform is starting to fill in; within the window the revyos side was mainly maintained via CI infrastructure (runner repository pushed 10-05), with no version-level release.
  • Sources: revyos/linux A210 commit (plus 3 others in the same batch)

(Ecosystem reference) RT-Thread: introduces optional lwIP 2.2.1 version (10-03)

  • The rt-thread main repository merged four commits on 10-03: importing the lwIP 2.2.1 source tree, listing 2.2.1 as an optional version alongside 1.4.1/2.0.3/2.x, cleaning up documentation, and fixing a sio_write signature conflict — not directly related to RISC-V, included as ecosystem reference.
  • Sources: rt-thread commit history

IV. Chips and Hardware

Domestic SoCs and Development Boards: Allwinner V861 Retail, K230D, A733, and the ESP32 Family

  • Allwinner V861 / Avaota F2: The first V861 single-board computer has gone on retail sale (see Top Stories): dual-core XuanTie C907 + E907, 128MB on-chip DDR3, 1 TOPS NPU, hardware documentation open-sourced under CC0, software following the Tina SDK (OpenWrt 21.04 branch + Linux 6.6); the report also notes that third-party channels are charging above the original price.
  • Canaan K230D: The CanMV-K230D-Zero development board (RISC-V MCU-class SoC, 128MB LPDDR4) drew attention on HN (09-30).
  • A733 Development Board: An A733 development board (LPDDR5, PCIe storage, with RISC-V coprocessor) was covered (10-01).
  • ESP32 Family: An ESP32-C5 development kit surfaced (3.5-inch touchscreen, optional camera and battery, 09-30); Waveshare launched an ESP32-C5 multi-protocol development board (Wi-Fi 6 plus Thread plus Zigbee, reported 10-04); community firmware LakeShark turns the LilyGO T-Display P4 into a handheld ESP32-P4 SDR scanner (10-01).
  • Sources: Avaota F2 (CNX), CanMV-K230D (HN), A733 (LinuxGizmos), ESP32-C5 kit (CNX), ESP32-P4 firmware (CNX)

Vendor Software Support: Espressif and Sophgo’s Holiday Pace

  • Espressif: 82 repositories across the organization saw pushes during the window; roughly 20 merges landed on the ESP-IDF mainline, concentrated on transport and security fixes—WebSocket fragmentation validation and mask out-of-bounds, AES-ECB hardware buffer overlap, mbedtls output out-of-bounds protection, VFS filesystem operation copying, FreeRTOS PIE task blacklisting (abort on execution), and more; repositories including OpenThread, esp-sr, esp-at, esp-vision, and the LLVM/Eclipse plugins were still active on the morning of 10-08.
  • Sophgo: Two fixes in sophon-tools—psewriter 2.1.4 corrected TF card misdetection (10-07), and memory_edit changed CV84X6 multi-fdt configurations to stepwise fallback with an added /boot backup pre-check (morning of 10-08); the sophon-demo and sophgo-edk2 repositories each had maintenance pushes.
  • Sources: ESP-IDF commits, sophon-tools commits

Embodied Intelligence and Robotics: SpacemiT Robotics Stack Gets Continuous Holiday Reinforcement

  • Humanoid control and operator pipeline: humanoid_linglong added operator startup and guidance services (#17), fixed-base arm demo configuration files (#18), and split startup services by control configuration (#19); humanoid_common added operator services and a remote client (#22), fixed-base trajectory control (#23), and tightened driver startup readiness checks (#21).
  • Whole-body control and perception: control_whole_body made startup gating depend on fresh device feedback (#6) and supports optional IMU feedback (#7); audio exports PortAudio duplex timing and xrun counts (#14); ros2_humanoid fixed ASR capture interruption during voice prompts (09-30), and on the morning of 10-08 migrated ROS control to the operator socket API.
  • On-device voice loop: omni-agent connected on-device KWS wake-up with SPV full-duplex software AEC (10-02, including model auto-download instructions); model-zoo-kws launched a streaming wake-up engine (10-02).
  • Sources: humanoid_linglong, humanoid_common, omni-agent, ros2_humanoid

International IP and Design Ecosystem: Efinix’s FPGA 64-bit Path and Other Briefs

  • Efinix Sapphire RV64 (reported 10-03, see Top Stories): brings a Linux-class 64-bit soft core to Titanium/Topaz and Trion T20+ devices, forming a dual track with the 32-bit quad-core RISC-V block hardened into the devices.
  • Other briefs (included in the 09-30 issue): Nuvacore unveiled its “Core First” development model (keeping ISA choice open); SignOff demonstrated full custom-chip flow capabilities with its RISC-V “Kaveri” soft IP.
  • Sources: Efinix Sapphire RV64, Nuvacore report, SignOff report

V. Open Source Community and Industry Events

International Community and Media: Automotive Software Perspective and the Approaching Summit

  • RISC-V International Foundation Blog (10-07): Published a Codethink perspective article discussing economic control of automotive software—porting CTRL OS to an FPGA development board based on the RISC-V architecture, with reference to UN R155/ISO 21434 and EU CRA compliance obligations; the article notes the industry is in a “wait-and-see” phase, with early adopters bearing the cost of standards and tooling.
  • RISC-V Summit China 2026 (10-18 ~ 10-20, Shenzhen): The official website confirms a three-day event at the Shenzhen Convention and Exhibition Center (Futian); keynote speakers include David Patterson and Andrea Gallo; diamond sponsors include DAMO XuanTie, ESWIN Computing, Lanxin Computing, SpacemiT, and Tenstorrent; the call for papers closed on 08-31, and the organizing committee is reviewing submissions.
  • Other: At Singapore Tech Week 2026, SingNova showcased a full-stack RISC-V and AI solution (09-30, per company press release).
  • Sources: Codethink article, Summit website, SingNova report

Community Projects: PasRISCV Gains Traction and OpenC6 v2.0

  • PasRISCV: The RV64GCV/RVA23 emulator written in Object Pascal continues to attract attention—on 10-04, a Chinese-language article dissected its use in driving in-game Linux in the game “SEEDS,” and on 10-07 the Adafruit blog reposted an introduction.
  • OpenC6 v2.0: The bare-metal BIOS and RISC-V microkernel project for ESP32-C6 released v2.0 (10-01, Show HN).
  • Sources: PasRISCV, OpenC6

VI. Trend Observations

  • No pause during holidays; development cadence decoupled from statutory holidays: XiangShan feature branches (my-crob-difftest, frontend-bt, etc.) and the SpacemiT robotics stack continued to advance during the holiday period, with openRuyi even rolling out a new batch including Python 3.14 on the morning of 10-08—the observation that “official channels go silent while code channels stay active” held true again during the long holiday, as the engineering cadence of institutionalized open source teams no longer pauses with holidays.
  • openRuyi’s monthly rhythm takes shape; RVA23 moves from “declared support” to “fixed until usable”: In 2026.09, issues that actually block users—such as BCLR miscompilation and container hwprobe—were closed one by one, and an experimental RVA20 version was provided for the first time—parallel dual baselines mean the distribution has begun conducting comparative experiments outside the RVA23 mainline.
  • Capital narrative and industry narrative resonate; “mainstreaming” becomes a cross-language media theme: ESWIN’s IPO approaching pricing and listing, the 25% share and ten-billion-unit shipment figures, and MIPS’ statement on China cooperation all appeared in concentrated fashion around the National Day period; the first-day performance of the 10-09 listing will be the first test point on the capital side.
  • Hardware form factors continue to expand: FPGA soft cores (Efinix RV64), camera SoCs (Allwinner V861), MCUs approaching Linux capability (ESP32-S31)—RISC-V’s presence in “non-general-purpose CPU” form factors is strengthening, and the experimental ground for hardware-software co-design is extending from single boards to programmable logic.
  • Verification and security become shared infrastructure keywords: AME matrix result hashing landed synchronously in NEMU/difftest, XuanTie open-sourced CoVE PoC (Rust TSM), and SPMP entered standardization—”verifiable, isolatable” underlying capabilities are the prerequisite for the next stage of productization.
  • Watch in the next issue: ESWIN Computing’s first day of listing on 10-09; RISC-V Summit China (10-18 ~ 10-20) agenda and on-site announcements; openRuyi 2026.10 and RVA20 experimental version feedback; XiangShan my-crob-difftest/frontend-bt merge trends with mainline; ESP32-S31 Linux BSP promotion timeline.

Appendix: Sources and Verification Notes

Sources (one regular daily issue + holiday-window verification)

  • 09-30 issue: research window 09-29 05:00 ~ 09-30 05:00; the only regular daily issue in this cycle, serving as the source base (status descriptions in that issue, such as “openRuyi 2026.09 not yet released,” have been updated per holiday-window verification).
  • 10-01 ~ 10-07: National Day holiday, daily issues suspended, no daily-issue sources; developments were supplemented through public-source verification during the holiday window, including the latest commits and batches from the morning of the release day (10-08 AM).
  • Cycle continuity: developments from 09-26 ~ 09-29 were covered by the three daily issues 09-28 ~ 09-30; this cycle starts from the 09-30 issue, and the previous weekly report covered 09-21 ~ 09-25.

Verification Method

  • GitHub organizations and key repositories (216-hour window): covered organizations including DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT (including its robotics organization), Sipeed, revyos, OpenHW, Radxa Linkr, and openRuyi-Project, as well as key XiangShan-family repositories; where API rate limits applied, commits.atom was used as a fallback (cvw, openRuyi, XiangShan feature branches, XuanTie ATS, etc. were re-checked via Atom). No pushes within the window: ESWIN Computing, Nuclei, Radxa Linkr, etc.
  • openRuyi dual-source verification: cross-checked between the official website news page (2026.09 released on 09-30, date confirmed via page metadata) and the GitHub repository (11 commits within the window plus the 10-08 morning batch).
  • Member company website sweep: 391 completed (no change 175 / changed 150 / failed 66); all changes were homepage marketing and news-roll updates, with no substantive developments confirmable as new products, funding, or architecture releases; failed sites were mainly domestic and anti-scraping sites, and did not block the process.
  • News side: multiple Google News queries in Chinese and English over a 9-day window (about 86 candidates), each included after verifying headline semantics against the original source.

Scope Notes

  • Media-attributed items are labeled in the body: SCMP and digitimes wording on MIPS, the Ni Guangnan-related data aggregated by MyDrivers (including “25% share”), and “first RISC-V stock” as a market label rather than company-disclosed wording.
  • Company press-release attribution: SingNova (Tech Week Singapore); Avaota F2 retail information comes from third-party reporting, with a channel-premium caveat.
  • Core attribution boundaries: ESP32-S2/S3 use Xtensa cores (related items not included); ESP32-C series, P4, and S31 use RISC-V cores. The Allwinner V861 main core is XuanTie C907/E907 (RISC-V).
  • Time-period note: this issue includes the latest commits verified on the morning of the release day (10-08 AM), and the body labels them by actual date; the absence of daily issues from 10-01 ~ 10-07 was a planned suspension.

Main References