Research window: 2026-10-29 05:00 ~ 2026-10-30 05:00 (Beijing time, 24 hours).

Sources: Google News aggregation (26 query sets in Chinese and English, via proxy), Hacker News, Phoronix, CNX Software, LinuxGizmos, LWN, the official riscv.org blog, the openRuyi official news page and main repository, website inspections of RISC-V International member companies (391), the riscv100.top leaderboard inspection, and commit and release searches across GitHub organizations and key repositories including XiangShan, NEMU, difftest, XSCache, CORE-V CVW, DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT and spacemit-robotics, Sipeed, revyos, openRuyi-Project, and Radxa Linkr.

In This Issue

  • Today’s Highlights: Post-quantum instruction set extension runs Classic McEliece on Cyclone V, cutting decapsulation cycles by 86.1% (10-29)
  • I. Open-Source Community and Software Ecosystem
    • openRuyi: 20 commits in a single day — vkpeak merged, clang-wrap follow-up, batch upgrade of KDE Frameworks 6.31.0 (10-29)
    • XiangShan difftest: three commits — MMA write-back reuses pooled buffers, gsim supports FST waveforms (10-29)
    • XiangShan NEMU adds NutShell quick-reference config, CI reuses PR-Agent review comments (10-29)
    • XiangShan XSCache switches CoupledL2 hint arbitration to round-robin, fixing long-term blocking (10-29)
    • XiangShan CI performance flow allows difftest to be disabled (10-29)
    • CORE-V CVW trims license boilerplate to SPDX identifiers, README adds gc-configured SRAM macro capacity (10-29)
  • II. Product and Ecosystem News
    • Tenstorrent and Vayavya Labs’ RISC-V virtual platform collaboration picked up by Indian localization coverage (10-29)
    • SpacemiT docs-product adds MCU firmware flashing resources for the CoM260 module (10-29)
  • III. Deep Dive on Domestic Teams
    • Sophgo sophon-demo adds SE7 platform Python performance row for PaddleOCR-VL (10-29)
    • DAMO XuanTie, ESWIN, and Nuclei: zero organization-level new development in the window (10-29)
  • IV. Embodied Intelligence and Robotics Special Section
    • Chen Mingxiu, head of DAMO’s Leyun embodied platform, leaves to found Muling Technology, betting on Physical RSI (10-30)
    • RISC-V robotics stack: zero commits for the day; spacemit-robotics’ four repositories remain at the previous day’s state (10-29)
  • V. Summary and Trend Observations

Today’s Focus: Post-Quantum Instruction-Set Extension Runs Classic McEliece on Cyclone V, Cutting Decapsulation Cycles by 86.1% (10-29)

A paper published in Discover Computing provides full FPGA validation of this design. The authors are Haridhayal Maheswaran, Samuel Kennedy, and Basel Halak (paper title “Architectural exploration and FPGA validation of a RISC-V instruction-set extension for Classic McEliece,” Volume 29, Issue 1, Article 808, DOI 10.1007/s10791-026-10770-1), reported on 10-29 by Scienmag and Bioengineer.

There are three core conclusions. First, a tightly coupled instruction-set extension is feasible on real hardware: the full design occupies 10,531 adaptive logic modules on a Cyclone V, achieves a maximum fitted clock of 118.89 MHz, and fits on a DE1-SoC board. Second, the speedup is verifiable: under the same asynchronous-memory simulation setup, encapsulation cycles drop by 87.4% and decapsulation by 86.1%, equivalent to 7.18× the unaccelerated baseline; the synchronous FPGA version performs both operations using host-generated keys, requiring 3,654,113 cycles for decapsulation and 13,585 cycles for encapsulation including SHA-256. Third, the gains are unevenly distributed: the Berlekamp-Massey sub-operation drops from 5,832 cycles to 40, and Gaussian elimination cuts minimal-polynomial generation from 297 to 38 cycles (7.8×), but nearly all remaining decapsulation cost lies in support-list generation—over 99% of cycles under both memory configurations—with the bottleneck being the Benes permutation network that drives the support, not the already-accelerated decoding logic.

The most methodologically valuable part of the paper is a rejected approach. The authors originally intended to add a DMA-assisted instruction mapping for composeinv; after integration profiling, it yielded only a 1.0–1.1× improvement in the controlbits stage, because the recursive call structure repeatedly crosses narrow memory boundaries, canceling out all kernel-level gains, so they abandoned it outright. From this the authors derive an accelerator-selection rule: when call structure dominates data-movement cost, making only the bulk kernel faster is ineffective. This criterion applies equally to teams in China currently working on custom RISC-V instruction-set extensions.

Engineering details are also worth recording. The authors moved custom instructions into the standard RISC-V custom-0 opcode space, replacing the original binary patch stubs with GCC’s .insn directive, saving roughly 20 cycles of function-call overhead per invocation and letting the compiler schedule custom instructions into surrounding code. The inherited Berlekamp-Massey state machine revealed four defects during bring-up: an incorrect shift-loop bound, negated operands in field-fraction arithmetic, an implicit 32-bit promotion that broke mask computation, and a missing zero-extension on multiplier inputs that let high bits leak into the result; the transpose path also required a 64×64 crossbar transpose memory rather than an ordinary register file—an issue exposed only by full-system decapsulation testing. To fit the board’s area budget, test parameters were reduced to error-correction capability t=2, code length n=48, and field degree 12.

The limitations are stated clearly. Because controlbits remain on the software side, the key-generation path exceeded the 300-million-cycle simulation budget and can only be given as a lower bound: over 60 seconds at the board’s 5 MHz clock, and over 2.52 seconds if the entire system ran at 118.89 MHz; full device-side key generation was neither timed nor demonstrated on the board, and the FPGA image loads host-generated keys. On power, Quartus PowerPlay estimates 458.34 mW total at 5 MHz, with a single decapsulation taking about 731 ms and consuming about 335 mJ, roughly 90% of which is static leakage. Neither production parameters nor side-channel resistance were evaluated, and no side-channel experiments were performed; a scaling analysis using the full mceliece348864 parameter set shows that the packing matrix, the 255 KB public key, and processor memory cannot all fit within the target device’s roughly 496 KB of block memory, and the toy-scale acceleration block would need to be redesigned rather than simply scaled up.

Date: 2026-10-29　Source: Bioengineer: RISC-V Chip Design Brings Post-Quantum Cryptography Closer to FPGA Reality, Paper DOI: 10.1007/s10791-026-10770-1

I. Open-Source Community and Software Ecosystem

openRuyi: 20 commits in a single day — vkpeak lands in the repo, clang-wrap follows up, KDE Frameworks 6.31.0 bulk upgrade (10-29)

The 20 commits fall into three groups. The largest is 13 kf6-* packages synced to KDE Frameworks 6.31.0, covering kio, kwallet, ksvg, prison, kguiaddons, threadweaver, syntax-highlighting, syndication, sonnet, solid, qqc2-desktop-style, purpose, and networkmanager-qt. The second is the addition of the vkpeak package (upstream version 20260527), a synthetic Vulkan device peak-performance benchmark that measures peak vector and matrix throughput for fp32/fp16/fp64 and int8 through int64, bf16, and fp8; it depends on vulkan-headers and vulkan-loader, and the SPEC was submitted by a maintainer at the Institute of Software. The third is build-chain maintenance: clang-wrap updated to 20261029, ecbuild relocated its cmake modules to the multi-architecture library directory, three Go ecosystem packages had dependencies and build support fixed, and the duplicate package go-github-smartystreets-assertions was removed.

The real significance of vkpeak landing in the repo lies in the measurement baseline: Vulkan devices on RISC-V platforms previously had no unified peak-compute comparison tool, and can now be compared directly against x86 and Arm boards. The latest release on the official news page is still the 2026.09 version, and the October version has not yet been released, so these 20 commits are rolling maintenance rather than a release sprint.

Date: 2026-10-29　Source: openRuyi commit log, vkpeak SPEC

XiangShan difftest: three commits — MMA writeback reuses pooled buffers, gsim supports FST waveforms (10-29)

All three commits target verification efficiency. No. 1014 changes MMA writeback from “allocating and zeroing an entire physical result buffer per instruction” to reuse from a bounded pool, falling back to ordinary allocation when the pool is full; the new MatrixResult transfers result ownership from the software ROB to asynchronous verification, with its deleter responsible for returning pooled storage or freeing an ordinary array, and the shared pool’s lifetime guarantees that not-yet-completed results remain valid, with retirement, replay, and destruction paths finalized by RAII. No. 1013 fixes physical register layout fidelity on the MMA path on both the CPU and CUDA sides. No. 867 adds FST waveform output to gsim, making it easy to feed simulation waveforms directly into standard viewing tools.

Date: 2026-10-29　Source: difftest #1014, #1013, #867

XiangShan NEMU adds a NutShell fast-reference config, CI reuses PR-Agent review comments (10-29)

No. 1273 adds a NutShell fastref configuration profile to NEMU, allowing differential comparison against NutShell as a reference to take a lighter reference path; the PR description includes a host instruction count and throughput comparison table for XS interpreter tests, covering benchmarks such as bitmanip. No. 1263 changes the CI flow so the pipeline reuses review comments already generated by PR-Agent, avoiding repeated analysis of the same diff.

Date: 2026-10-29　Source: NEMU #1273, #1263

XiangShan XSCache switches CoupledL2 hint arbitration to round-robin, fixing long-term blocking (10-29)

Commit No. 46 changes the arbiter in CoupledL2 from fixed priority to round-robin arbitration, resolving an issue where one hint path continuously held the arbitration and left the other path unable to obtain a grant for a long time. The change itself has only a one-line description, but it is a classic starvation-type defect in the cache hierarchy that only shows up under prolonged stress testing.

Date: 2026-10-29　Source: XSCache #46

XiangShan CI performance flow allows disabling difftest (10-29)

No. 6804 adds a switch to disable difftest in the perf flow of the main XiangShan repo’s CI, allowing benchmark scenarios to skip differential comparison and devote machine time to performance measurement. The PR has no text description, and the change is limited to CI scripts without touching RTL.

Date: 2026-10-29　Source: XiangShan #6804

CORE-V CVW trims license boilerplate to SPDX identifiers, README adds gc-config SRAM macro capacity (10-29)

No. 1950 is a pure comment change: 3,868 lines deleted with no additions, each file retaining its SPDX identifier line and the lengthy license paragraph condensed to a single line. The review record also flags two to-dos — the nine test files that entered main after the branch was created still carry full license paragraphs and need another trim after merging main; and this change conflicts with No. 1954 (cleaning src header files) and No. 1952 (cleaning comments and whitespace and removing unused modules), so a merge order must be agreed. No. 2014 merges README configuration notes, giving the total SRAM macro capacity for the gc-series configurations.

Date: 2026-10-29　Source: CVW #1950, CVW commit log

II. Product and Ecosystem Developments

Tenstorrent and Vayavya Labs’ RISC-V virtual platform collaboration picked up by Indian localization coverage (10-29)

The collaboration itself was announced on 10-08: Vayavya Labs is building a SystemC virtual platform for Tenstorrent’s security and system management IP using its TvastaaVP platform, letting software development and verification begin before silicon is available and reducing integration risk. The 10-29 Indian media report adds two incremental points: the line began as a one-off SystemC modeling engagement in 2024 and later evolved into a multi-year agreement; and Vayavya is using the collaboration to strengthen its position in India’s semiconductor ecosystem. The direct reason the collaboration continues is Tenstorrent’s continuously expanding RISC-V roadmap.

Date: 2026-10-29　Source: Tenstorrent newsroom, Ahmedabad Mirror report

SpacemiT docs-product adds CoM260 module MCU firmware flashing resources (10-29)

Two commits: merging PR No. 152 and adding MCU firmware flashing resources for CoM260. On the documentation side, the module’s MCU firmware flashing path is now complete; this is product delivery documentation refinement and does not involve kernel or compiler code changes.

Date: 2026-10-29　Source: docs-product #152

III. Deep Dives on Domestic Teams

Sophgo sophon-demo adds an SE7 platform Python performance row for PaddleOCR-VL (10-29)

sophon-demo adds an SE7 platform Python inference performance row to the PaddleOCR-VL README comparison table. PaddleOCR-VL is a vision-language model for document parsing; this row brings measured data for the model on SE7 into the official baseline, making it easier to compare against other SE-series platforms during selection.

Date: 2026-10-29　Source: sophon-demo commit log

DAMO XuanTie, ESWIN, and Nuclei: zero organization-level new development in the window (10-29)

All six XUANTIE-RV repositories — torq-tile, llvm-project, gcc, CubeSandbox, riscv-aosp, and xuantie-yocto — had no commits in the window; ESWIN’s linux-sdk and riscv-matrix-gemm-vectors had no commits; Nuclei’s nuclei-sdk had no commits. None of the three had verifiable new development output within 24 hours, a gap compared with the previous day’s dense commits. On the Espressif side, the routine pace of dozens of component repos syncing daily continues and does not count as new development.

Date: 2026-10-29　Source: XUANTIE-RV, eswincomputing, Nuclei-Software

IV. Embodied Intelligence and Robotics Special Section

Chen Mingxiu, head of DAMO’s Leyun embodied platform, leaves to found Muling Technology, betting on Physical RSI (10-30)

According to reports, Chen Mingxiu (head of the Leyun embodied intelligence platform at DAMO Academy’s Embodied Intelligence Lab) has founded Muling Technology in Yuhang, Hangzhou. The company was established on 2026-06-25 with registered capital of about RMB 1.5625 million, and focuses on Physical RSI (embodied recursive self-improvement, i.e., letting robots continuously update task capabilities through feedback from physical-world interaction). His career began as head of visual algorithms at Rokid; after joining Alibaba he first worked on edge-camera AI algorithms, then led the Leyun platform (device-cloud collaboration, zero-GPU deployment on device). This is the third core personnel change at DAMO within two months, following chief scientist Zhao Deli on 9-14 and scientific intelligence head Rong Yu on 10-15. Supporting industry evidence in the same direction is the AgiBot Genie Master framework and the autonomous improvement of Genie G2 in real convenience-store scenarios, also mentioned in the report. It should be noted that this item concerns personnel and industry developments in DAMO’s embodied team and has no direct technical connection to the RISC-V instruction set or XuanTie IP.

Date: 2026-10-30　Source: NetEase / Embodied Emergence report

RISC-V robotics stack has zero commits for the day: spacemit-robotics’ four repos stall at the previous day (10-29)

The four spacemit-robotics repositories — humanoid_common, control_whole_body, unitree-go2, and peripherals-imu — had zero commits in the window, with their latest commits all stalled at 10-28. The previous day’s 10 substantive commits included motion adapter and operator client integration, tabular coupling for whole-body control, Go2 switching to a terrain-only V2 policy, and IMU support extended to a third vendor’s serial protocol. A one-day gap is a normal pace and does not by itself justify a directional judgment, but it must be distinguished from “bulk mirror syncing” — yesterday’s assessment was substantive development; today is a pause.

Date: 2026-10-29　Source: spacemit-robotics

V. Summary and Trend Observations

1. The crux of post-quantum cryptography is “where to draw the instruction-set boundary,” not “making the big core compute faster.” Today’s paper provides a verifiable selection map: Berlekamp-Massey and Chien search deliver the highest cycle gains per unit of logic, each nearly eliminating a sub-operation within 1,000 adaptive look-up tables; streaming public-key generation occupies 4,705 adaptive look-up tables and is only worthwhile when keys must be generated on-device; the rejected DMA-based composeinv shows that accelerating batch kernels is ineffective when call structure dominates data-movement cost. This criterion is more practical than “how many times faster the benchmark runs,” and is directly usable by domestic teams building RISC-V custom instruction extensions.

2. Verification infrastructure continues toward “resource pooling + trimmability.” difftest pools MMA result buffers and replaces per-entry allocation with ownership transfer; the XiangShan CI perf flow allows difftest to be disabled. Both changes point the same way—treating verification as a budget to be managed rather than an overhead that must always be fully on. XSCache’s switch of arbitration to round-robin fixes a starvation-class defect, a long-term stability issue, and belongs with the previous two under “first make the infrastructure stop being a drag.”

3. openRuyi is filling in the “measurable” layer. With vkpeak merged, Vulkan peak compute on RISC-V boards now has a unified metric directly comparable with x86 and Arm; the continued follow-through on clang-wrap and KDE frameworks shows a steady rolling-release cadence. However, the official news page still shows the 2026.09 release as latest, with the October release unpublished; this period’s 20 commits are mainly framework and ecosystem packages, not a pre-release sprint.

4. The domestic side has entered a lull, and the lull is on the development side rather than the delivery side. XuanTie, ESWIN, and Nuclei had zero new development in the window; SpacemiT had only two documentation commits to docs-product, with its four robotics-stack repos stalled; Sophgo had only one line of performance data. In parallel, the DAMO embodied-AI team saw its third core personnel change in two months—this has no direct technical link to RISC-V, but it reflects talent and capital in embodied intelligence flowing from big-platform roles to startups in the Physical RSI direction, and the main suppliers of domestic RISC-V robotics software stacks are precisely the external partners of such teams; the impact of this personnel flow on future roadmaps is worth tracking.

5. Information volume and basis for judgment this period. After deduplication across 26 Chinese and English Google News queries in the window, only three substantive new items emerged: the post-quantum paper, the Tenstorrent India localization report, and the DAMO personnel change; dimensional, browser, and consumer-electronics items (XHEART X7 Ultra, LattePanda Sigma 2, BeagleConnect QuadESC) were verified to use Armv9, Intel, and TI solutions respectively, unrelated to RISC-V, and were excluded. Open source remains the main body this period: openRuyi’s 20 commits, XiangShan’s 6, CORE-V’s 4, and Sophgo’s 1 all have verifiable commit records. The GitHub organization-level API’s anonymous quota was exhausted in the latter part of this period’s collection, so commit feeds were used as a fallback; consequently, full push lists for organizations such as Espressif and Sipeed could not be expanded repo by repo.

Full Source List

Source Verification Table

Source Verification Result
Google News aggregation (26 Chinese/English queries, 24-hour window) After deduplication, 3 substantive new items in the window: the post-quantum instruction-set-extension paper, the Tenstorrent–Vayavya India localization report, and the DAMO embodied platform personnel change. XHEART X7 Ultra (released 10-29, 700 TOPS, CPU is China’s first mass-produced automotive-grade Armv9), LattePanda Sigma 2 (Intel Core Ultra X7 358H), and BeagleConnect QuadESC (TI AM13E23019) were verified as non-RISC-V and excluded; the RISC-V Industry Alliance’s Zhou Meng “15th Five-Year Plan” article is a re-publication of 10-18 to 10-20 summit remarks and was not included per deduplication rules; the “Sophgo” query pulled in coal-transport and stock-market pieces, the “ESWIN” query pulled in Xi’an ESWIN buyback and block-trade pieces, and the “SpacemiT” query pulled in mobile-game and local-GDP pieces, all excluded
Post-quantum paper Cross-checked against the original: 10,531 ALMs, 118.89 MHz, decapsulation 3,654,113 cycles, encapsulation 13,585 cycles, Berlekamp-Massey 5,832 to 40 cycles, Gaussian elimination 297 to 38 cycles, power 458.34 mW, about 731 ms and 335 mJ per decapsulation, key generation lower bound over 60 seconds—all taken from the paper as quoted in the original
XiangShan / NEMU / difftest / XSCache / GEM5 Kunminghu V3 branch: 1 commit (CI perf can disable difftest); difftest: 3 commits (MMA pooled writeback, CPU and CUDA register layout, gsim FST); NEMU: 2 commits (NutShell fastref, CI reuse of PR-Agent); XSCache: 1 commit (CoupledL2 arbitration switched to round-robin); GEM5 and llvm-project had no commits in the window
openRuyi main repo and official site 20 commits in the main repo in the window: 13 kf6-* packages bumped to 6.31.0, clang-wrap bumped to 20261029, vkpeak added, ecbuild module path adjusted, three Go ecosystem packages had dependencies fixed, one duplicate package removed; the official news page still shows the 2026.09 release as latest, with the October release unpublished
CORE-V and OpenHW CVW: 4 commits (SPDX trimming merge, README gc-configured SRAM capacity, two merges); cva6 had no commits in the window
DAMO XuanTie, ESWIN, Nuclei, Espressif XuanTie’s six repos (torq-tile, llvm-project, gcc, CubeSandbox, riscv-aosp, xuantie-yocto) had zero commits; ESWIN’s two repos had zero commits; Nuclei’s nuclei-sdk had zero commits; Espressif’s 30-plus repos sync daily as routine maintenance
SpacemiT spacemit-com and spacemit-robotics docs-product: 2 commits (CoM260 MCU firmware flashing resources); spine-FlagGems, spine-triton, linux, etc. had zero commits; spacemit-robotics’ four repos (humanoid_common, control_whole_body, unitree-go2, peripherals-imu) had zero commits in the window, all last updated 10-28
Sophgo, Sipeed, revyos, Radxa Linkr Sophgo sophon-demo: 1 commit (PaddleOCR-VL adds a SE7 Python performance row); LLM-TPU and tpu-mlir had zero commits; Sipeed NanoKVM and MaixPy had zero commits; revyos’ linux and edk2-platforms had zero commits; Radxa Linkr’s linkr and linkrd had zero commits
riscv.org official blog and RSS No new articles in the window; latest are the 10-20 SoCMake feature and the 10-15 interview with DAMO’s Meng Jianyi
Phoronix, CNX Software, LinuxGizmos, LWN Zero RISC-V-specific hits in the window: Phoronix’s items that day centered on Linux 7.4 subsystems and NVIDIA/AMD drivers; CNX covered LattePanda Sigma 2 and BeagleConnect QuadESC, neither RISC-V; LinuxGizmos covered a Jetson carrier board; LWN covered scheduler and container topics
Member company website sweep (391) Swept 391 sites: 219 unchanged, 105 changed, 67 fetch failures. Changes were mainly homepage refreshes at universities and research institutions (MIT, KU Leuven, KTH, TUHH, FURG, University of Athens, etc.), plus homepage rotations at corporate sites including Google, AMD, Huawei, Andes, and OpenChip; a spot check of Andes’ news page found the latest entries still from 2025, with no substantive developments such as new products, funding, or architecture launches
riscv100.top sweep No changes (no additions or numeric changes in What’s New, Upcoming, committee members, or the six SPEC rankings)

Limitations

The GitHub organization-level API’s anonymous quota was exhausted in the latter part of this period’s collection, so full push lists for organizations such as Espressif, Sipeed, revyos, and OpenHW could not be expanded repo by repo; commit feeds were used as a fallback, so activity in non-priority repos of these organizations may be missed. Key repos at XiangShan and openRuyi were checked commit by commit via commit feeds, so those conclusions are unaffected. For 67 member company sites, body text could not be retrieved due to anti-scraping, redesigns, or overly short above-the-fold content, so their website updates were not included in this period’s judgment. The 6th RISC-V China Summit ended on 10-20, and change verification of the official site and source repos stops as of this period.