Research window: 2026-10-27 05:00 ~ 2026-10-28 05:00 (Beijing time, 24 hours).

Sources: Google News aggregation (17 query sets in Chinese and English, via proxy), Hacker News, Phoronix, CNX Software, LinuxGizmos, riscv.org, the openRuyi official news page and main repository, website inspections of RISC-V International member companies (391 companies), and commit and release searches on GitHub (XiangShan/NEMU/difftest/XSCache, DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT and spacemit-robotics, Sipeed, revyos, openRuyi-Project, Radxa Linkr, OpenHW, and other organizations and key repositories).

In This Issue

  • Today’s Highlight: XiangShan matrix extension verification chain completes FP8 precision, NEMU and difftest land in sync (10-27)
  • I. Open-Source Community and Software Ecosystem
    • XiangShan NEMU supports FP8 MMA, difftest adds synchronized verification build option (10-27)
    • XiangShan Kunminghu V3 merges seven fixes: PC guard bits and StoreQueue prefix dequeue (10-27)
    • openRuyi: 20 commits in a single day: Samba suite upgraded to 4.25.1 and migrated to Waf build (10-27)
    • Pharo 14 released: VM adds RISC-V JIT (10-26)
    • Sipeed SLogic completes USB bulk transfer, Radxa Linkr creates new linkrd repository (10-27)
  • II. Product and Ecosystem News
    • WuQi Micro showcases full RISC-V chip lineup at summit: WQ9301 already in mass production and shipping (10-26)
    • Keybytes open-source modular keyboard: one RISC-V microcontroller per key (10-26)
    • Mijia desktop water purifier 3 carries RISC-V chip for mineral slow-release and filter life management (10-27)
    • 36Kr reviews the year RVA23 lands: three hurdles and three time points (10-27)
  • III. Deep Dive on Domestic Teams
    • WuQi Micro: 600 million RISC-V cores used cumulatively, AI glasses main control adopted by over ten brands (10-15~10-26)
  • IV. Embodied Intelligence and Robotics Special Section
    • Embodied intelligence chip market: RISC-V penetration 10.7% in 2025, projected 28.2% by 2030 (10-27)
    • ZeroDynamics Robotics: multiple compute cadences coexist on device, RISC-V enters via communication and control (10-27)
    • SpacemiT robotics repositories synced in bulk, no substantive new commits in window (10-27)
  • V. Summary and Trend Observations

Today’s Highlight: XiangShan Matrix Extension Verification Chain Completes FP8 Precision, NEMU and difftest Land in Sync (10-27)

Within the window, the XiangShan team advanced matrix extension (AME/MMA) support from instruction semantics to two further layers: data types and verification methodology. The reference model NEMU adds FP8 matrix multiply-add; the differential verification framework difftest adds a synchronized verification build option; and the integer saturation semantics of MMA are fixed to be consistent between the CPU and CUDA sides.

This thread has appeared for three consecutive days, forming a clear technical evolution curve. The 10-26 progress was difftest running INT8 matrix comparisons on Tensor Cores, solving “comparing too slowly”; the 10-27 progress changed the type encoding of MMA events to decode according to mcfg register semantics, solving “comparing incorrectly”; today’s addition is the FP8 data type and the synchronized verification switch, solving “comparing incompletely.” Three actions in three days point to the same fact: the core being verified has become so complex that cycle-by-cycle software simulation can no longer keep up, and the verification infrastructure itself must be hardware-accelerated and parallelized.

The significance for the industry does not lie in a single XiangShan core. Matrix extension is a mandatory question for RISC-V to enter AI inference workloads, and the specification is still being advanced—during the summit, some vendors judged that “it will take another one or two years for the matrix extension specification to take shape and enter products.” By building FP8 and integer saturation semantics into the reference model and differential verification now, XiangShan is effectively preparing in advance the step of “how to verify once the specification lands.” What really bottlenecks domestic AI accelerators is often not peak compute, but inconsistent boundary behavior between floating-point and integer across different implementations; only when differential verification covers this layer can multi-platform comparability even be discussed.

I. Open-Source Community and Software Ecosystem

1.1 XiangShan NEMU Supports FP8 MMA; difftest Adds Synchronous Verification Build Option

Date: 2026-10-27　Source: GitHub: OpenXiangShan/NEMU commit history, GitHub: OpenXiangShan/difftest commit history

NEMU merged 4 commits in the window, the core one being feat(ame): support FP8 MMA with FP32 accumulation (#1266): the matrix extension now supports multiply-accumulate with FP8 inputs and FP32 accumulation, one of the most commonly used precision combinations for large-model inference. The same batch also includes a layered BOOM reference configuration (#1262), a performance optimization that reuses HostTLB when sharing the FAST reference (#1270), and raising the NEMU guest memory for diff-spike to 32 GiB (#1267).

difftest had 3 commits over the same period, focused on MMA verification methodology: a new synchronous verification build option (#1009) for deterministic comparison of the MMA path, a fix to integer saturation handling on both the CPU and CUDA sides (#1008), and separating the DiffTest pipeline from reference-model checks in FPGA scenarios (#1006).

  • Observation: With FP8 in the picture, numerical differences between the reference model and real silicon widen, and any inconsistency in saturation, rounding, or NaN propagation will break differential comparison. This batch effectively brings “precision-semantics consistency” into the verification scope, which matters more than simply increasing comparison throughput.

1.2 XiangShan Kunminghu V3 Merges Seven Fixes: PC Guard Bits and StoreQueue Prefix Dequeue

Date: 2026-10-27　Source: GitHub: OpenXiangShan/XiangShan commit history

The Kunminghu V3 branch had 7 commits in the window, all functional fixes: on the core side, “carry real PC guard bits” (#6751) and removal of dead code in the floating-point area (#6765); on the store-queue side, two fixes in the same batch are the most critical—decoupling physical-address matching from virtual-address matching (#6769), and allowing only completed store-queue prefixes to dequeue (#6768). The latter targets a typical ordering error in out-of-order cores: partially completed queue entries released early cause memory access order to diverge from architectural semantics.

  • Observation: Fixes like these never show up on performance charts, but they determine whether an out-of-order core is production-ready. Store-queue prefix dequeue is one of the most error-prone spots under the RISC-V weak memory model, and two consecutive fixes merged in the same batch show the team is converging on memory-subsystem correctness.

1.3 openRuyi 20 Commits in a Single Day: Full Samba Stack Upgraded to 4.25.1 and Migrated to Waf Builds

Date: 2026-10-27　Source: GitHub: openRuyi-Project/openRuyi commit history

The openRuyi main repo had 20 commits in the window, concentrated in three areas. First, an overall upgrade of the Samba ecosystem with a unified build system: samba bumped to 4.25.1, with tdb 1.4.15, talloc 2.5.0, and tevent 0.17.2 upgraded in tandem, all switched to Waf build macros, and Waf support added to rpm-config-openruyi. Second, audio-stack fixes: jack2 fixes client connections and enables resampling. Third, infrastructure and security: cmocka bumped to 2.0.2 with unit tests enabled, ceph backports fixes for ceph-volume, mgr, cephfs-mirror, and rgw, and rust-aws-lc-sys 0.46 added with rust-aws-lc-rs upgraded to 1.18.2.

  • Observation: Unifying the build method of the four Samba components on Waf and providing macro support at the distro meta-config level is a classic case of “upstream changed its build system, so the distro has to redo it.” This kind of behind-the-scenes work determines whether SMB file services on RISC-V servers can keep pace with upstream security updates.

1.4 Pharo 14 Released: VM Adds RISC-V JIT

Date: 2026-10-26　Source: Pharo Official: Pharo 14 Released, OSChina: Pharo 14 Released

The Smalltalk development environment Pharo has released version 14. Of the three structural VM overhauls, the most directly relevant to the RISC-V community is the new RISC-V JIT support; the other two are unified frame and stack management (a major cleanup of the interpreter and execution engine) and expanded memory management (direct old-generation allocation and garbage collection improvements). There are also numerous fixes to the Slang/C translation layer, expanded command-line testing and debugging tools, and a release cadence moved to autumn.

  • Observation: Pharo’s RISC-V JIT is a signal of the “niche language stack filling in a mainstream backend” variety. Language VMs are the most easily overlooked layer of an ISA ecosystem—they generate no headlines, but a missing JIT backend means an entire class of developers cannot get usable performance on RISC-V.

1.5 Sipeed SLogic Completes USB Bulk Transfer; Radxa Linkr Creates linkrd Repository

Date: 2026-10-27　Source: GitHub: sipeed/SLogic commit history, GitHub: radxa-linkr/linkrd

The Sipeed SLogic logic analyzer had 4 commits in the window, all in the USB transport layer: assigning a new PID (0x3000) to SLogic8U2 and unifying device tables and naming across applications, cutting a single USB transfer to about 5 milliseconds while guaranteeing at least 4 transfers in flight, with self-tests failing outright when fewer than 4 transfers are in flight; libsigrok, all-logic, scopehal-apps, and slogicview were also advanced together. The linkrd repository under the Radxa Linkr organization completed its first init proj commit the same day, marking the establishment of a new repository.

  • Observation: These SLogic commits expose an old problem with sampling peripherals—the throughput bottleneck is not the sample rate but USB transfer scheduling. Encoding “at least 4 transfers in flight” as a self-test assertion embeds a performance constraint into testing, an approach worth referencing for domestic teams building RISC-V instrument peripherals.

II. Product and Ecosystem Updates

2.1 WuQi Microelectronics Showcases Full RISC-V Chip Lineup at Summit: WQ9301 Already in Mass Production and Shipping

Date: 2026-10-26　Source: WuQi Microelectronics: WuQi Microelectronics Showcases Full RISC-V Chip Lineup at the 6th RISC-V China Summit, Sina Finance: Domestic Router Wi-Fi 6 Chip Breaks Through (10-27)

Chongqing WuQi Microelectronics showcased two product lines at the 6th RISC-V China Summit: network communications and edge intelligence. The company officially states that its entire product lineup is based on the open-source RISC-V architecture, with cumulative use of over 600 million RISC-V cores. The highlight product is the Wi-Fi 6 AP chip WQ9301: RISC-V multi-core architecture, supporting 802.11 a/b/g/n/ac/ax, uplink and downlink MU-MIMO and OFDMA, 160MHz bandwidth and 1024QAM, dual-band concurrent physical layer up to 3Gbps, with baseband and RF integrated on a single chip. The company claims it is one of the very few RISC-V Wi-Fi 6 AP chips in China to achieve mass production and shipping, targeting domestic substitution for routers, smart gateways, and FTTR.

  • Observation: Router AP chips are the segment of the Wi-Fi supply chain with the highest R&D investment and certification barriers, long dominated by overseas vendors. The significance of WQ9301’s mass production lies not in its specs, but in the fact that “the AP side of RISC-V has completed the entire journey from tape-out to volume shipping”—an order of magnitude harder than the STA side.

2.2 Keybytes Open-Source Modular Keyboard: One RISC-V Microcontroller per Key

Date: 2026-10-26　Source: The Register: Open source keyboard lets you swap parts like magnetic Lego bricks, Tom’s Hardware (10-27)

The open-source hardware project Keybytes takes modularity down to the single-key level: each key is an independent 1u circuit board (called a Keybit), each carrying a CH32V003-series RISC-V microcontroller, with pogo pins on all four sides for power and I2C transmission. Keys attach magnetically and can be rearranged into arbitrary layouts. The entire keyboard requires only one additional controller module (called a Keyword) to aggregate the keys and communicate with the host; this module uses the same form factor but houses two circuit boards. The design and firmware are open-sourced on GitHub. A single Keybit board costs about $2, a Keyword about $30, and a full-size assembled unit with materials and contract manufacturing costs about $900.

  • Observation: Conventional keyboards use a single chip to scan the entire matrix; Keybytes inverts this by distributing scanning capability to each key. This offers no cost advantage whatsoever, but it turns “rearranging layouts” from a soldering task into a plug-and-play action—a genuinely viable path for specialized input devices that require frequent layout changes (one-handed keyboards, accessible input, split ergonomic designs). Cheap RISC-V MCUs like the CH32V003, costing just cents, are the prerequisite for this approach.

2.3 Mijia Desktop Water Purifier 3 Features RISC-V Chip for Mineral Slow-Release and Filter Life Management

Date: 2026-10-27　Source: IT Home: Xiaomi Launches Mijia Desktop Water Purifier 3

Xiaomi has listed the Mijia Desktop Water Purifier 3 at 1,499 yuan. The product features a RISC-V chip, which works with patented slow-release technology to steadily release 6 natural minerals including strontium, zinc, and calcium into the water (measured strontium content no less than 0.2mg/L), and dynamically extends RO filter life to 3 years based on this. Other specs: 2100W thick-film heating for 3-second instant hot water, maximum flow rate of 786mL/min, temperature adjustment from 40 to 99 degrees Celsius in 1-degree increments, dual-cartridge 9-stage filtration with DuPont RO membrane (0.0001 micron precision), 6L raw/waste water separation tank plus 2L external pure water pitcher, and NFC cup stickers that remember custom water temperature and volume.

  • Observation: This is a rare case of RISC-V in home appliances “handling control algorithms rather than just switching”—mineral slow-release and dynamic filter life calculation both require sensor closed loops and model computation, which are control-type workloads. Domestic appliance makers pushing such algorithms down to RISC-V MCUs is a quiet but real substitution path for ARM Cortex-M.

2.4 36Kr Reviews the Year of RVA23 Implementation: Three Hurdles and Three Timelines

Date: 2026-10-27　Source: 36Kr: From PPT to Data Center—RISC-V Enters the Year of RVA23 Implementation, Breaking Through on AI and Physical AI Dual Fronts

36Kr published a long-form summit retrospective (the platform notes it as user-published with AI assistance, with key data cross-checked against official media sources). The article cites RISC-V International CEO Andrea Gallo’s assessment: 2026 is the year of RVA23 application processor implementation, with three simultaneous inflection points over the past year—RVA23 profile implementation, release of the Server Platform Specification 1.0, and the collective debut of high-performance chips.

Regarding obstacles before scale-up, Xu Qingwei, Ecosystem Marketing Lead at Blue Core Computing, offered a “last 1% to 5%” framing: over 90% of the foundation of an industry solution is generic; what truly blocks progress is which databases and middleware finance needs to adapt, and which specialized toolchains industry needs to adapt—which can only be driven by real customers. He gave three timelines: by 2028, four or five similar players will appear on the market; by 2030, the RISC-V plus AI server ecosystem will be initially established; by 2035, the ecosystem will reach a baseline of usability. Feedback from Chen Zhibiao, CEO of YashanDB at the Shenzhen Institute of Computing Sciences, was more direct: this year they completed code-level adaptation on RISC-V, functionality is usable, but there is still a significant gap in core performance scenarios.

  • Observation: The value of this retrospective is that it shifts the discussion from “what was announced” to “where things are stuck.” Among the three timelines, 2028 is the most noteworthy—most vendors are betting the scale inflection point on two years out, meaning 2027 will be a year of concentrated investment in capacity, certification, and software adaptation.

III. Deep Dive on Domestic Teams

3.1 WuQi Microelectronics: 600 Million RISC-V Cores Cumulative, AI Glasses SoC in Over a Dozen Brands

Date: 2026-10-15 to 10-26　Source: WuQi Microelectronics: World’s First Brain-Computer Interface AI Glasses Launched, WuQi Microelectronics: Full RISC-V Chip Lineup Showcased at Summit

WuQi Microelectronics (Chongqing) is one of China’s earliest chip design companies to develop and mass-produce chips based on RISC-V. Its product lines span two pillars: “connectivity” and “edge AI.” The former is represented by the Wi-Fi 6 AP chip WQ9301 and the STA series; the latter by smart audio SoCs and machine vision chips. During the summit, the company disclosed cumulative use of over 600 million RISC-V cores. Its Wi-Fi AP chips have previously received MIIT autonomous-controllable certification, and its STA chips have passed AEC-Q100 automotive-grade certification.

The edge AI line’s landing point is AI glasses. Its WQ7036 series smart audio SoC integrates VAD and KWS algorithms, call noise reduction, and low-power Bluetooth control. The company states it has been adopted by over a dozen brands including INMO, XGIMI, NIMO, Jianan, Looktech, LOHO, and VITURE for AI audio glasses, AI camera glasses, and AR glasses. The new-generation Looktech product launched on 10-15 at the SILMO optical fair in Paris uses this solution, featuring built-in EEG sensors and a six-axis IMU, with total weight under 30 grams and temple wall thickness of 0.4mm.

  • Observation: The SoCs in domestic AI glasses have long been a combination of “Bluetooth audio SoC plus external ISP.” WuQi’s approach is to compress voice front-end algorithms (wake word, noise reduction) and wireless connectivity into a single RISC-V SoC. For teams planning to build AI glasses, this is a low-cost solution that bypasses general-purpose application processors—at the cost of compute ceiling limited by the SoC’s positioning, with imaging and display still requiring external components.

IV. Special Chapter on Embodied Intelligence and Robotics

4.1 Embodied Intelligence Chip Market: RISC-V Penetration at 10.7% in 2025, Projected to Reach 28.2% by 2030

Date: 2026-10-27　Source: 36Kr: From PPT to the Server Room

The summit recap cites Frost & Sullivan data: China’s embodied intelligence chip market grew from RMB 34.1 billion in 2021 to RMB 129.7 billion in 2025 (CAGR 39.6%), and is projected to reach RMB 387.7 billion by 2030; over the same period, RISC-V penetration in this market rose from 1.7% to 10.7% and is projected to reach 28.2% by 2030, while the shares of x86 and Arm fell from 40% and 49% to 31% and 41%, respectively. Another dataset shows China’s RISC-V main control chip market growing from RMB 1.1 billion in 2021 to RMB 37.7 billion in 2025, and projected to reach RMB 219.4 billion by 2030 (CAGR 139.5%).

  • Observation: The two figures are more meaningful taken together—the main control chip market grew roughly 34x in four years, yet RISC-V’s absolute share of embodied intelligence chips remains only about one-tenth. This indicates that growth is coming mainly from general-purpose main control and consumer segments, while the high-compute chips inside robot bodies remain Arm and x86 territory. This also explains why domestic vendors can make inroads on the “cerebellum” side but are still validating on the “cerebrum” side.

4.2 Zero One Robotics: Multiple Compute Cadences Coexist on the Device Side; RISC-V Enters via Communication and Control

Date: 2026-10-27　Source: 36Kr: From PPT to the Server Room

Cheng Yi, co-founder and CTO of Zero One Robotics, offered a roadmap judgment from the perspective of a complete-robot manufacturer: the robot device side requires multiple compute cadences to coexist—tasks break down into hundreds of milliseconds to seconds, VLA action policies into tens to hundreds of milliseconds, and high-frequency perceptual adjustments after contact follow yet another cadence, all of which must be coordinated within the same system. He believes the reasonable near-term path is to retain the mature application host and first introduce RISC-V in areas such as communication and control, since these positions have clear responsibilities and interfaces, and the benefits can be proven quickly.

  • Observation: This is the most pragmatic embodied intelligence judgment in this issue. Putting RISC-V into communication and control rather than replacing the main control outright means that domestic robot makers’ RISC-V adoption phase will take the form of “coprocessor/real-time domain.” This is an actionable window for teams building RISC-V MCUs and real-time operating systems, while for teams building high-compute SoCs it means a longer validation cycle.

4.3 SpacemiT Robotics Repositories Bulk-Synced, No Substantive New Commits in Window

Date: 2026-10-27　Source: GitHub: spacemit-robotics organization

Eight repositories in the spacemit-robotics organization showed pushes within the window, but these completed within the same second (humanoid_common, humanoid_unitree_g1, control_whole_body, target, peripherals-motor, peripherals-imu, etc.). A commit review confirmed no new commits on the main branches within the window, so this is judged to be branch or mirror synchronization rather than new development. During the same period, four repositories under revyos (opensbi, ruyiedk2, edk2, coreboot) and six under sipeed exhibited the same second-level bulk-push pattern.

  • Observation: Treating such bulk pushes as development output is a common misjudgment. Real development activity in the robotics stack requires examining main-branch commit contents; in this window, SpacemiT had no includable new progress in the robotics direction.

V. Summary and Trend Observations

1. Verification infrastructure has become the invisible battleground in open-source core competition. The XiangShan thread has advanced for three consecutive days: from difftest borrowing Tensor Cores to boost comparison throughput, to decoding MMA event types according to mcfg semantics, and now to NEMU supporting FP8 multiply-add plus difftest adding a synchronous verification switch and integer saturation fixes. Taken together, these three moves support one judgment—the cores being verified have grown so complex that pure software simulation can no longer keep up, and verification itself must be moved into hardware; and with FP8 in the picture, consistency of precision semantics matters more to success than throughput. This lesson holds for every team in China building AI extensions.

2. The edge side was the only RISC-V direction with real new product launches that day. Wuqi’s Wi-Fi 6 AP chip has reached mass production and shipment, and its AI glasses main control has entered more than ten brands; Xiaomi has put mineral slow-release and filter-life algorithms into RISC-V chips in home appliances; and Keybytes used the CH32V003 to build a keyboard with one MCU per key. What these three have in common is cheap chips, closed-loop algorithms, and volume on the consumer side—in contrast with server-side scenarios that are still arguing over performance.

3. In the post-summit review period, discussion has shifted from “what was announced” to “where things are stuck.” The bulk of this issue’s Chinese coverage is follow-up interpretation of the summit; hardware launches and items such as XuanTie’s 6 billion units, Xinji Wuxian’s funding, and Tenstorrent’s $1.5 billion Series E were already covered in issues 10-19 through 10-20 and are not repeated under the deduplication rule. The genuinely new incremental content is industry judgment: the year RVA23 lands, the “last 1% to 5%” before scale, the three time points of 2028/2030/2035, and YashanDB’s hands-on feedback that it is “functionally usable but still behind on core performance.”

4. Determination of a quiet window and its basis. This issue’s Chinese and English Google News produced 57 deduplicated in-window hits in total; after removing gambling and gaming noise, stock-market pieces, and duplicate summit coverage, there were about 5 substantive new items; on the GitHub side, most key organizations had no in-window commits to their main branches. This is a low-news-volume day, and the report is delivered under the quiet-day protocol, with the main content falling on open-source progress and edge-side product launches.

Full Source List

Source Verification Table

Source Verification Result
Google News aggregation (17 Chinese and English query sets, 24-hour window) 57 deduplicated in-window hits, about 5 substantive new items: the Wuqi WQ9301 report, Mijia water purifier 3, the Keybytes keyboard, Pharo 14, and 36Kr’s RVA23 retrospective; Tenstorrent’s $1.5 billion Series E (announced 10-19, followed up by multiple English financial media within this issue’s window) was already covered in issue 10-20, while XuanTie’s 6 billion units and E908A, Xinji Wuxian’s Pre-A funding, SpacemiT V100, Lanxin LX500, Sophgo SRM31, Chaorui UR-CP400, onsemi taking over Codasip’s business, and S2C and Imagination’s summit showcase are all existing content in circulation and are not re-covered under the deduplication rule; the report on machine learning detecting RISC-V hardware attacks was verified to have originally been published on 09-24 and has been removed; the Chinese queries for “Sophgo” and “XuanTie” still mixed in mobile-game and stock-market pieces, which have been removed
XiangShan / NEMU / difftest / XSCache 7 fixes on the Kunminghu V3 branch; NEMU 4 commits (FP8 MMA, tiered BOOM configuration, HostTLB reuse, diff-spike memory); difftest 3 commits (MMA synchronous verification, integer saturation, FPGA link split); XSCache had no commits in the window
openRuyi main repo and official site Main repo 20 commits (Samba 4.25.1 full suite and Waf build migration, jack2, cmocka, ceph backports, rust-aws-lc series); the latest release on the official news page is still the 2026.09 version, and this month’s version has not yet been released
DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT Key repositories of XuanTie (opensbi / zero_stage_boot / qemu) had no commits in the window; SpacemiT and Sipeed showed second-level batch pushes, but commit-stream checks found no new in-window commits on the main branches, judged to be synchronization rather than development; the remaining organizations could not be fully checked because the GitHub anonymous API rate limit was exhausted, and commit streams were used as a fallback to cover key repositories
Member company website inspection (391 companies) 391 inspected, 86 homepages changed, all routine marketing and content updates with no substantive RISC-V developments; 68 failed to fetch or had content too short, not blocking
Sipeed, Radxa Linkr Sipeed SLogic 4 commits (USB transfer scheduling and SLogic8U2 support); Radxa Linkr created the linkrd repository and completed its first commit
Summit official site and source repos The 6th RISC-V China Summit ended on 10-20, with Bay Area and Hong Kong Day on 10-21; the official site monitoring period has passed, with no new content this issue

Limitations

During collection for this issue, the anonymous call quota for GitHub organization-level APIs was exhausted, so some watched organizations (DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT) could not have their in-window pushed-repository lists obtained, and commit streams of each organization’s key repositories were used as a fallback check instead. As a result, if non-key repositories of these organizations had activity in the window, this issue may have missed it. The openRuyi official news page, key repositories of XiangShan and RT-Thread, and the member company website inspection results were all obtained in full.