Research window: 2026-10-22 05:00 ~ 2026-10-23 05:00 (Beijing time, 24 hours; continuing from the previous daily’s cutoff).

Sources: Google News aggregation (18 supplementary queries in Chinese and English, via proxy), Hacker News, Phoronix, CNX Software, LinuxGizmos, riscv.org, the openRuyi official news page and main repo, website inspections of RISC-V International member companies (391 companies), and GitHub (pushes, commits, and release searches across organizations and key repositories including XiangShan/XSCache/GEM5/difftest, DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT, Sipeed, revyos, openRuyi-Project, Radxa Linkr, and OpenHW).

In This Issue

  • Today’s Highlight: Kehua Data signs with SpacemiT, bringing RISC-V server chips into computing infrastructure (10-22)
  • I. Open Source Community and Software Ecosystem
    • openRuyi: 20 commits, Python 3.14.9, nginx 1.31.8, and Node.js 24.22.1 land (10-22)
    • Community project runs Linux 7.3 and OpenSBI 1.9 on ESP32-S31 (10-22)
    • XiangShan Kunminghu V3 and CORE-V cvw: mnret/dret decoding fixes, jalr errata (10-22)
  • II. Product and Ecosystem Updates
    • The RISC-V path for mmWave radar: domestic chips land first, CPU slot remains a second option (10-22)
    • International media perspective: after server CPUs make their collective debut, porting cost becomes the real barrier (10-22)
    • Espressif ESP32-S31 spills over into finished products: GUITION knob screen moves to the new SoC (10-22)
  • III. Deep Dive on Domestic Teams
    • DAMO XuanTie CubeSandbox: 12 consecutive RISC-V CI pushes, micro-VM control plane runs MySQL (10-22)
    • SpacemiT software stack iterates on three fronts: unified vision model interface, llama.cpp prefill optimization (10-22)
    • Sophgo sophon-demo adds a Python sample for PaddleOCR-VL (10-22)
  • IV. Embodied Intelligence and Robotics Special Section
    • 21st Century Business Herald interview with Sun Yanbang: K3 powers humanoid robot to finish a race, robots will move toward single-chip designs (10-22)
    • spacemit-robotics: action recognition config aligned to 13-point skeleton (10-22)
  • V. Summary and Trend Observations

Today’s Highlight: Kehua Data signs with SpacemiT, bringing RISC-V server chips into computing infrastructure

Date: 2026-10-22　Sources: Guandian: Kehua Data and SpacemiT sign strategic cooperation agreement to jointly build a domestic computing ecosystem (10-22), Sohu: Joining the “chip” journey together — Kehua Data and SpacemiT reach strategic cooperation (10-22)

Kehua Data Co., Ltd. and SpacemiT (Beijing) Intelligent Technology Co., Ltd. signed a strategic cooperation agreement covering four dimensions — technology, products, market, and ecosystem — with the goal of connecting the AI chip layer and the computing infrastructure layer and jointly building a domestic computing ecosystem.

  • Kehua’s capabilities: Nearly 40 years in the power electronics industry and over a decade of data center construction and operations experience, with business covering high-end power supplies, precision temperature control, and full-lifecycle data center operations management; it led the drafting of the association standard “Technical Specification for Collaboration between Domestic Chips and Computing Hardware Infrastructure (CCHS)” and has partnered with multiple leading domestic and international AI chip vendors.
  • SpacemiT’s products: K3 is the world’s first mass-produced RISC-V AI CPU compliant with the RVA23 specification; V100 was released during the summit held 10-18 to 20, officially described as the world’s first high-performance server-class CPU meeting full server specifications and compliant with the RISC-V Server SoC specification, accompanied by three system types: the C2201 compute server, G5201 intelligent compute server, and S5236 storage server.
  • Where the cooperation lands: Driving an autonomous, controllable computing solution through the full process from chip definition and system porting to large-scale deployment; technically, advancing co-optimization between RISC-V AI chips and computing infrastructure; on the product side, jointly building solutions for different computing scenarios.

Launching a server chip only means the hardware exists; whether it can get into the data center depends on whether power, cooling, system design, and operations teams are willing to change for it. The real significance of this signing is that it turns “porting” from something chip companies push unilaterally into joint work with infrastructure vendors; meanwhile, foreign media analysis published around the same time points out precisely that porting cost is the decisive variable in whether customers migrate. Both threads lead to the same conclusion: the next stage of RISC-V in the cloud will not be decided at launch events, but in the data center.

I. Open-Source Community and Software Ecosystem

1.1 openRuyi: 20 Commits, Python 3.14.9, nginx 1.31.8, and Node.js 24.22.1 Land

Date: 2026-10-22　Source: openRuyi main repo commit log (10-22), openRuyi official news page

The openRuyi main repo recorded 20 commits in the window, mainly version upgrades and security fixes in the SPECS directory, plus some packaging-spec cleanup.

  • Runtime and language stack: python bumped to 3.14.9 (commits tagged security-fixes), nodejs to 24.22.1, openjdk-17 to 17.0.21.9, openjdk-21 to 21.0.13.9.
  • Services and middleware: nginx bumped to 1.31.8 (security-fixes), python-pillow to 13.0.0 (security-fixes), rdma-core to 65.0, libudev-zero to 1.0.5. rdma-core is the RDMA userspace library for high-speed networking and HPC clusters, a foundational component of a server distribution.
  • Engineering cleanup: opencv now uses a build-directory variable instead of a hardcoded /home path; xmltoman, xinetd, xdg-utils, xcb-util-renderutil, xcb-util-image and other packages gained source checksums and switched to the automatic changelog macro.
  • Dual sources on the official site: the latest announcement on the news page is still the 2026.09 release; no new release in the window.

Looking at three consecutive days of commits, openRuyi’s fill-in order is Go cloud-native components, then uv’s Rust dependencies, then the major runtime versions of Python and Node. Commits tagged security-fixes appear in batches, indicating that security updates have entered a process-driven channel rather than being scattered patches.

1.2 Community Project Runs Linux 7.3 and OpenSBI 1.9 on ESP32-S31

Date: 2026-10-22　Source: GitHub: annoyedmilk/esp32-s31-linux (10-22)

The community project esp32-s31-linux runs the upstream Linux 7.3 kernel and OpenSBI 1.9 on Espressif’s ESP32-S31, using 16 MB octal PSRAM as main memory.

  • Boot chain: ESP ROM to ESP-IDF second stage, then loader, OpenSBI, Linux, and finally a Buildroot root filesystem (SD card, USB drive, or flash).
  • Usable userspace: a shell on the LCD, wpa_supplicant networking, BlueZ Bluetooth, SSH, USB keyboard/mouse and USB drives, vim, gdb, strace, MicroPython, and the text browser links.
  • Technical highlights: the SoC has no PLIC, no Zicbom, and no coherent DMA; the project provides alternative implementations in a few hundred lines of code and wrote internal implementation docs aimed at kernel developers.
  • Hardware coverage: three builds — ESP32-S31-Korvo-1, ESP32-S31-Function-CoreBoard-1, and the ESP32-S31-WROOM-3-N16R16V module.

That a dual-core RV32 designed as an MCU (320 MHz, 512 KB SRAM, 16 MB PSRAM) can run a full Linux userspace shows how thin the software stack’s hardware requirements have become. Such projects are not a product path, but they are an extreme test case for toolchain, kernel porting, and driver maturity, with direct value for teaching and porting reference.

1.3 XiangShan Kunminghu V3 and CORE-V cvw: mnret/dret Decode Added, jalr Erratum

Date: 2026-10-22　Source: XiangShan commit log (10-22), cvw commit log (10-22)

The XiangShan Kunminghu V3 branch had 3 commits in the window, all in details rather than features: decode now covers the mnret and dret privileged return instructions (#6692), the ROB redirect start index was corrected (#6729), and the README gained Dashboard and star-history links (#6696).

  • CORE-V side: 2 commits in the cvw repo, adding an erratum entry for the jalr instruction in Table I.1 (PR #1996) and merging it.
  • Interpretation: mnret and dret are the return-path instructions for M mode and debug mode respectively; adding their decode means XiangShan is refining privileged-state and debug support. The jalr erratum is a documentation-level fix, more valuable to verification teams than to external users.

Progress on open-source cores often consists mainly of commits that “show no features.” Whether an open-source core is advancing is judged by easily overlooked corners like privileged state, exceptions, and debug — not by which benchmark it just passed.

II. Product and Ecosystem Updates

2.1 The RISC-V Path for mmWave Radar: Domestic Chips Land First, CPU Slot Remains a Second Option

Date: 2026-10-22　Source: RFID World: mmWave Radar RISC-V Domestic Players Race Ahead (10-22)

An article surveying instruction-set choices for mmWave radar chips offers a fairly pragmatic judgment: in radar chips, RISC-V and Arm are currently coexisting options, not a generational replacement.

  • Domestic players land first: Zhenghe Microelectronics’ RS6240 (released in 2024, dual-core RISC-V) is already used in smart home, elderly care monitoring, and security alerting; Kaiku’s K60213 integrates a RISC-V MCU and AI accelerator and has entered indoor interactive devices such as TVs, air conditioners, and fans.
  • Automotive-grade penetration: Nuclei’s NA900 has obtained ISO 26262 ASIL-D certification, and Calterah’s Kunlun-Pro integrates this core, with dual-issue dual-core total compute of 3668 DMIPS, roughly 5x the previous-generation Alps-Pro, and is advancing toward L2 ADAS forward perception.
  • Division of labor: The 10x signal-processing compute that outsiders focus on comes from Calterah’s in-house RSP 2.0, not the RISC-V core; RISC-V handles point-cloud post-processing and target tracking—stages where algorithms update quickly and must remain on a programmable CPU. Vendors use open extension interfaces to turn sorting, interpolation, and trigonometric functions into hardware instructions, with measured clustering time roughly halved and tracking time down more than 50%.
  • International majors: TI’s AWR2188 and NXP’s TEF8388 and SAF8444 still use Cortex-A53 and M7, with no short-term incentive to switch; ESWIN’s Hong Kong IPO prospectus also concedes that RISC-V remains in the early stage of market validation, with user awareness and trust not yet fully established.

The value of this piece lies in giving RISC-V’s real coordinates within a specific category: not “what it replaces,” but “which slot it is more cost-effective in.” The driving forces are supply-chain controllability, cost, and freedom to customize—not a performance gap; functional safety is not a weakness either, since NA900 already has ASIL-D capability. What is truly lengthy is the three-to-five-year certification cycle for the entire chip.

2.2 An International Media Perspective: After Server CPUs Debut En Masse, Adaptation Cost Becomes the Real Barrier

Date: 2026-10-22　Source: Global Times: Chinese chipmakers roll out new RISC-V server CPUs for AI demand (10-22)

A roundup from overseas media after the summit places SpacemiT’s V100 and Lanxin Computing’s LX500 in the same narrative: Chinese vendors are pushing RISC-V from embedded into AI servers.

  • The facts: V100 has 46 cores, up to 2.4 GHz, supports DDR5 and PCIe 5.0, and comes with three types of complete systems—compute, AI, and storage; LX500 has 48 cores and integrates a dedicated AI engine, is being adapted for models such as Qwen, DeepSeek, and Kimi, and targets scenarios including enterprise knowledge-base retrieval, office assistants, financial compliance inference, and industrial inspection.
  • The opinions: Analysts interviewed argue that competition in server CPUs goes beyond single-chip performance and that replacing a processor is not swapping a part; whether operating systems, applications, and development tools run smoothly, and whether adaptation and maintenance costs are acceptable, are what really determine whether customers migrate. When adaptation costs are too high, customers hesitate even if the new chip has technical advantages.

By separating “launch” from “deployment,” this piece provides an external yardstick: complete systems at the show prove the hardware form factor is ready, while cost accounting on the ecosystem side is what decides orders. This dovetails with today’s Top Story in this issue.

2.3 Espressif ESP32-S31 Spills Over into Finished Products: GUITION Rotary Knob Display Switches to the New SoC

Date: 2026-10-22　Source: CNX Software: Rotary encoder with 1.8-inch touch display gets upgrade to ESP32-S31 SoC (10-22)

GUITION JC3636F118C-I-YR1 is a rotary knob display product that upgrades the original ESP32-S3 version to the ESP32-S31NRV16: a 1.8-inch 360×360 round TFT (ST77916 driver plus CST816 touch), 16 MB flash and 16 MB PSRAM, a speaker and MEMS microphone, a DRV2605 haptic driver, and USB-C power.

  • Wireless specs: Wi-Fi 6, Bluetooth 5.4 (including LE Audio, direction finding, and Mesh 1.1), and 802.15.4 tri-mode, with a 320 MHz RV32IMAFCP high-performance core plus a low-power MCU core.
  • Product significance: Less than ten days after the ESP32-S31 first appeared on a third-party development board (10-14), finished products have begun switching over. The pace of complete-product adoption for MCU-class RISC-V is markedly faster than for previous generations of architecture.

III. Deep Dive on Domestic Teams

3.1 DAMO XuanTie CubeSandbox: 12 Consecutive RISC-V CI Commits, MicroVM Control Plane Runs MySQL

Date: 2026-10-22　Source: XUANTIE-RV/CubeSandbox: feat/riscv64-ci branch commits (10-22)

During the window, XuanTie-maintained CubeSandbox shifted its focus from “opening a RISC-V branch” to a CI push: the feat/riscv64-ci branch recorded 12 commits, all centered on getting the microVM control plane running stably on RISC-V.

  • Kernel configuration: enabled CONFIG_NUMA for the 7.2 L1 kernel, built XFS and the dummy driver into the kernel, and completed the tc-bpf, bridge, and tap network stack.
  • Observability: capture L1 dmesg and L2 guest console output on failure; added an environment variable switch to make the guest console observable; disabled dirty log by default, with CUBE_DISABLE_VM_DIRTY_LOG as an escape hatch.
  • Process: extended the shim’s VM startup wait and shut down L1 on exit; switched the C1 control-plane demo to an apt-installed mysql systemd unit, first fixing mysqld observability and then verifying the service stops cleanly.
  • Upstream context: upstream is Tencent Cloud’s open-source AI Agent sandbox (Apache 2.0, hardware-level isolation, millisecond startup, E2B-compatible interface); RISC-V-side snapshot and restore still await vAIA state migration and remain in developer preview.

Not one of these dozen-plus commits is a “feature release”—all of them nail down instability one item at a time: kernel configuration, serial observability, dirty-page logging, MySQL start/stop verification. Taking a microVM on RISC-V from booting to carrying real workloads costs almost entirely this kind of work, and it is also the most reliable vantage point for judging the maturity of this stack.

3.2 SpacemiT Software Stack Iterates on Three Fronts: Unified Vision Model Interfaces, llama.cpp Prefill Optimization

Date: 2026-10-22　Source: model-zoo-vision commits (10-22), llama.cpp: mtmd-backend branch commits (10-22), ai-sdk commits (10-22)

After the V100 launch, SpacemiT’s software stack is iterating in small steps on three lines at once, all aimed at “letting external developers use it directly.”

  • Vision model library: three commits in model-zoo-vision; the core refactor unifies the Run interface across tasks and removes the task-layer interface (#109), unifies the READMEs of the model examples (#110), and adds Python examples for the track and match model types (#111).
  • Inference stack: two commits on the llama.cpp mtmd-backend branch—the SpacemiT prefill optimization on the ggml side (#49) and cleanup of outdated duplicate -lm and –load-mode options (#50).
  • SDK: two ai-sdk submodule updates pointing to the vision module.
  • Supporting docs: two docs-ros commits the same day align the perception and vision docs with the new node behavior and SDK interfaces (#217, #218).

Unifying interfaces and filling in examples signals that the model library is opening up to external developers; the prefill optimization directly affects long-context processing efficiency and first-token latency, among the most sensitive metrics in server scenarios. How fast the software follows a chip launch often matters more than the specs.

3.3 Sophgo sophon-demo Adds a Python Sample for PaddleOCR-VL

Date: 2026-10-22　Source: sophgo/sophon-demo commit history (10-22)

Sophgo’s example repository sophon-demo added a Python sample for PaddleOCR-VL (paddleocr_vl.py) on the release branch, completing a directly runnable version of this document-intelligence model on its own platform.

  • Background: on 10-19 the same repo had just been tidied up, removing the bundled tpu-mlir wheel download; this time the Python version was completed, forming a full docs-plus-sample combination.
  • Pace over the same period: from 10-19 to 10-21 the repo continuously added C++ samples for SAM3, SAM2, BLIP, MP_SENet, and YOLO_world, plus MiniCPM4, InternVL3, and MiniCPMV adaptations for the CV84X6 platform.
  • Interpretation: within two months the example library expanded from “Python reference implementations” to “C++ engineering samples + day-one adaptation of hot models.” The competitiveness of edge chips increasingly depends on whether a model runs once it arrives and whether it can be reproduced by following the docs—this layer is more practical than spec marketing.

IV. Special Chapter on Embodied Intelligence and Robotics

4.1 21st Century Business Herald Exclusive Interview with Sun Yanbang: K3 Powers Humanoid Robot to Finish Race, Robots Will Move Toward Single-Chip

Date: 2026-10-22　Source: 21st Century Business Herald (reposted by Sina Finance): The RISC-V Force Behind the Humanoid Robot Marathon (10-22)

An in-depth interview published after the summit, with interviewee Sun Yanbang, co-founder of SpacemiT, offering several verifiable developments and judgments.

  • Developments that have already occurred: In the April 2026 Beijing Yizhuang humanoid robot half-marathon, Linglong 2.0 completed the race using SpacemiT’s K3 chip; cumulative shipments of K1 reached 150,000 units, and K3 is the world’s first mass-produced RISC-V chip compliant with the RVA23 specification and has already entered large-scale mass production and delivery. The accumulation across these two generations of edge-side chips is described as the starting point for extending toward the cloud.
  • Market forecast: Citing Omdia data, RISC-V processor annual shipment growth rate is 50%, and by 2030 global market share will approach 25%, meaning roughly one in every four processors will be RISC-V.
  • Judgment one: Once the robotics industry enters a cycle of large-scale deployment, it will inevitably move toward a single-chip integration approach; next-generation robots will rely more on RISC-V, driven by extreme safety requirements and the fusion of a strong CPU with AI capabilities.
  • Judgment two: The real-time requirements of robots “never have a ceiling”; AI Agent escape incidents occur frequently, and neither virtualization nor physical isolation can thoroughly guarantee that the system always remains within controllable bounds—open-source and open mechanisms may instead be the breakthrough point; Physical AI is the biggest opportunity.
  • Judgment three: The R&D roadmap must match financial strength; beyond PPA, hardware must be over-provisioned so that the software ecosystem has room to perform; the iteration speed of the domestic supply chain is worth anticipating, but the ultimate measure remains order conversion.
  • External viewpoint: Also cites the judgment of Turing Award winner David Patterson that AI is driving up memory bandwidth and capacity pressure, performance improvements in mainstream standard memory have stalled, and domain-specific storage (DSA) has become viable against a backdrop of scarce compute.

This piece grounds “RISC-V for robots” from concept into two concrete coordinates: an edge-side chip already in mass production, and an architectural rationale of “safety plus real-time.” Compared with compute figures, the latter better explains why robot makers are willing to switch architectures; and the line “hardware must be over-provisioned” precisely explains the current common practice of robot chips reserving compute headroom in advance.

4.2 spacemit-robotics: Action Recognition Configuration Aligned to 13-Point Skeleton

Date: 2026-10-22　Source: ros2_action_recognition commits (10-22), spacemit-com/docs-ros commits (10-22)

SpacemiT’s robotics software line completed an interface alignment within the window: the action recognition repository merged a fix aligning the STGCN configuration with the 13-point skeleton definition to the vision API (#8); meanwhile, two docs-ros commits synchronized the perception and vision documentation to the new node behavior and SDK interfaces, and two ai-sdk submodule updates point to vision.

  • Repository positioning: spacemit-robotics covers gesture recognition, action recognition, real-time links, and peripheral control, and is supporting software for robots on the K3 platform; within the same window there were also pushes for realtime-link, manifest, and peripherals_led.
  • Interpretation: Converging skeleton keypoints from the common 17-point or 21-point schemes to 13 points is a typical step when aligning an upstream model with one’s own inference pipeline; the synchronized documentation and SDK updates indicate that this line is preparing for external delivery rather than internal experimentation.

V. Summary and Trend Observations

  • The center of gravity of the server narrative is shifting from “chip launches” to “infrastructure adaptation”: At the summit, V100, LX500, and C950A were unveiled in a concentrated fashion; the first batch of new moves after the summit was the signing between Kehua Data and SpacemiT, along with overseas media discussion of adaptation costs. The hardware form factor is already in place; what comes next is acceptance on the data-center side and the migration cost of the software stack.
  • RISC-V’s position in niche categories is clearer: The millimeter-wave radar report shows that in chips where DSPs and hardware accelerators carry the main compute load, the CPU instruction set is a “solution choice” rather than a “generational replacement”; the reason domestic vendors adopt it first is supply-chain controllability and freedom to customize, not a performance gap.
  • The pace of distribution completion is steady and moving up the stack: openRuyi, over three consecutive days, respectively added Go cloud-native components, uv’s Rust dependencies, and Python, Node, and Java runtime versions, and security fixes are beginning to go through the process with tags. RISC-V distributions are moving from “installable” toward “safe for production.”
  • The micro-VM stack on RISC-V has entered a debugging phase: All 12 CubeSandbox commits are kernel configuration, observability, and process validation—not a single feature release. This is an unavoidable stage from being able to boot to being able to carry workloads, and also the best window for observing the maturity of RISC-V virtualization.
  • Spillover effects are appearing on the edge side: It took only about ten days for ESP32-S31 to go from a preview device to third-party finished products, and community projects have even run a complete Linux and a full userland beyond the graphical on it. This kind of “squeezing downward” play will continue to amplify developer exposure for RISC-V MCUs.
  • Evidence on the robotics side still comes from edge-side and real-time control: K3 powered a humanoid robot to finish a race, and joint-control chips are already in mass production, while high-compute “brain” chips are mostly in the tape-out stage. The first wave of real RISC-V shipments in robotics is likely to still come from motion control rather than general-purpose AI compute.
  • Limitations note: Details of the Kehua Data–SpacemiT cooperation come from the two companies’ public statements and financial media paraphrase, with no disclosure of contract amount, timetable, or specific projects; the performance figures in the millimeter-wave radar report (3668 DMIPS, clustering and tracking latency) come from vendor testing and have not been reproduced by third parties; the interviewees in the Global Times piece are industry analysts, and their views do not represent industry consensus; ESP32-S31-Linux is a community project, and the author describes it as a porting experiment on a device “not designed for Linux,” which does not constitute a productization path; the content of openRuyi commits is judged based on commit titles and was not checked against the changelog item by item; CubeSandbox’s RISC-V support remains a developer preview, and no official release images are provided; the 95 changes detected in the member website inspection are all routine updates to the homepages of universities, institutions, and vendors, with no substantive product, funding, or architecture announcements found.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Google News aggregation (18 supplementary queries in Chinese and English) About 58 hits within the window; after removing financial, automotive, and sports noise and cross-validating against GitHub, most English reports on server chips were post-summit roundups overlapping with items already reported domestically
Hacker News, Phoronix, CNX Software, LinuxGizmos, riscv.org Phoronix and CNX each had entries related to Linux 7.4 and ESP32-S31; riscv.org and LinuxGizmos had no new RISC-V entries within the window
GitHub organizations and key repositories check (24-hour window) Pushes within the window: espressif 40, spacemit-com 28, spacemit-robotics 5, sipeed 3, openhwfoundation 2, openRuyi-Project 2, XUANTIE-RV 1, sophgo 1, Nuclei-Software 1 (PR activity only, no new commits); eswincomputing, revyos, radxa-linkr had no pushes
openRuyi dual sources 20 commits in the main repo; the latest item on the official news page remains the 2026.09 version, with no new release within the window
DAMO XuanTie, Sophgo, SpacemiT key repositories CubeSandbox 12 (CI branch), sophon-demo 1 (PaddleOCR-VL sample), model-zoo-vision 3, llama.cpp 2, ai-sdk 2, docs-ros 2, ros2_action_recognition 1 — all listed separately or incorporated into items
RISC-V International member website sweep (391 sites) Took 195 seconds: 224 unchanged, 95 with page content changes, 72 failed to fetch; changed items were routine updates to the homepages of universities, institutions, and vendors (Google, NVIDIA, AMD, MIT, etc.), with no substantive product, funding, or architecture announcements detected
6th RISC-V China Summit official website The summit concluded on 10-18 to 20; the website change-monitoring window has expired, and this check will no longer be listed separately starting this issue