Research window: 2026-10-21 05:00 ~ 2026-10-22 05:00 (Beijing time, 24 hours; continuing from the cutoff of the previous daily briefing).

Sources: Google News aggregation (24 query sets in Chinese and English, via proxy), Hacker News, Phoronix, CNX Software, LinuxGizmos, riscv.org, the RISE project blog, the openRuyi official news page and main repository, website inspections of RISC-V International member companies (391 companies), monitoring of the official website and source code repositories of the 6th RISC-V China Summit, and GitHub (pushes and commit searches for organizations and key repositories including XiangShan/NEMU/GEM5/XSCache, DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT, Sipeed, revyos, openRuyi-Project, Radxa Linkr, and OpenHW).

In This Issue

  • Today’s Highlights: Qualcomm acquires RISC-V server IP company Akeana, as major US firms accelerate the consolidation of architecture assets (10-21)
  • I. Open Source Community and Software Ecosystem
    • RISE releases the first Android 17 open-source version based on RVA23 (10-20)
    • Linux 7.4 crypto library: optimized AES implementations for RISC-V and x86 merged into lib/crypto (10-21)
    • openRuyi: 20 SPECS submissions, uv’s Rust dependencies merged in batches (10-22)
  • II. Product and Ecosystem Updates
    • Espressif ESP-Mosaico goes on sale: ESP32-S31 modular AI hardware kit, starting at $59 (10-21)
    • Radxa Linkr releases v1.6.0 (10-21)
  • III. In-Depth on Domestic Teams
    • DAMO XuanTie opens a CubeSandbox RISC-V support branch: CubeShim interfaces with KVM/AIA VMM backends (10-21)
    • ESWIN Computing and SiFive sign a Gold Partner Alliance MOU, expanding cooperation from edge AI to Agentic AI (10-21)
    • Sophgo sophon-demo completes CV84X6 adaptation: adds MiniCPM4, InternVL3, and MiniCPMV samples (10-21)
  • IV. Special Chapter on Embodied Intelligence and Robotics
    • Summit automotive electronics, industrial, and robotics sub-forums: Zijing M100 enters mass production in vehicles, IAR and Nuclei fill out the toolchain and IP (10-21)
    • On the robotics compute side, the narrative shifts from financing to mass-production validation: joint-control chips are already in mass production, while brain chips remain at the tape-out stage (10-21)
  • V. Summary and Trend Observations

Today’s Focus: Qualcomm Acquires RISC-V Server IP Company Akeana, US Giants Accelerate Consolidation of Architecture Assets

Date: 2026-10-21　Sources: Dealroom: Qualcomm buys RISC-V startup Akeana to push into AI and data-center chips (10-21), Sammy Fans: Qualcomm acquires Samsung foundry partner Akeana to expand AI chip business (10-21)

According to reports on 10-21, Qualcomm has completed its acquisition of RISC-V processor IP startup Akeana, with the transaction amount undisclosed. Akeana founder and CEO Rabin Sugumar confirmed on a professional social platform that Akeana’s IP and team “have become part of Qualcomm,” and that he has joined Qualcomm as Vice President of Engineering.

  • Company background: Akeana was founded in 2021, with its core team coming from the ThunderX server processor team at Marvell/Cavium; in August 2024 it emerged from stealth and disclosed more than $100 million in funding (with participation from Kleiner Perkins, Mayfield, Fidelity, and others). Its IP covers three tiers — Akeana 100/1000/5000 (MCU-class 32-bit cores, 64-bit cores with MMU, and ultra-high-performance cores for notebooks and data centers) — and also provides an AI matrix compute engine plus system IP for security, debug, RAS, and telemetry.
  • Industry-side clues: Akeana partnered with Samsung Foundry to advance 4nm server chips; in December 2025 the two parties completed the design of a server test chip codenamed Alpine, which is where this item directly connects to the “Samsung Foundry ecosystem.”
  • Qualcomm’s successive moves: In December 2025 Qualcomm acquired RISC-V server CPU IP company Ventana Micro Systems; it subsequently completed its $2.4 billion acquisition of Alphawave and announced a custom AI inference collaboration with Amazon. With this Akeana deal, Qualcomm has brought in two RISC-V server IP teams within 10 months.
  • Scope of interpretation: The transaction amount, customer commitments, and product timelines have not been made public, and there is no official statement on whether Akeana’s IP line will be merged into Qualcomm’s own CPU roadmap (Oryon) or remain a separate product line; this item only confirms the M&A at the factual level, and the commercial returns remain to be seen.

Comparison with the domestic route: In the same week, SpacemiT, together with XiangShan, released the server-class CPU V100 (6 XiangShan Kunminghu V2R2 cores + 40 in-house X100 cores, 46 cores total), following a productization path of “open-source cores + in-house cores.” Overseas, IP teams are consolidating into large companies; domestically, open-source cores are penetrating commercial chips. Both paths answer the same question: where will the IP supply for server-class RISC-V come from.

I. Open Source Community and Software Ecosystem

1.1 RISE Releases First Open Source Android 17 Build on RVA23

Date: 2026-10-20　Source: RISE: Android 17 Available on RVA23 with RISE (10-20), RISE android_manifest: android-17-v1.0 (10-20)

The RISE project announced delivery of the first Android 17 build running on RVA23 hardware, released as open source, with support for two boards: the SpacemiT K3 Pico-ITX and the Alibaba A210 EVB. The project is numbered RP024, funded and led by RISE, with member organizations SpacemiT and Alibaba DAMO Academy providing platform expertise and hardware, and BayLibre handling the engineering implementation, building on its earlier Android port to SpacemiT K1.

  • Release contents: android-17-v1.0 provides binary images for both boards, a version-locked source manifest, checksums, flashing tools, and rebuild instructions; source history and authorship are fully preserved, making it reproducible and extensible.
  • Degree of openness: It uses an open source boot chain of U-Boot + OpenSBI, with a graphics stack based on the upstream Imagination kernel driver and Mesa; the project explicitly states this is an open source release for developers, not a production or certified version.
  • Next phase: Phase 2 of RP024 will automate the build, hardware testing, and release process, starting with tests on the existing A210 systems in the RISE Board Farm and adding K3 within a few weeks; RISE also previewed that subsequent RFPs will cover Bionic, BoringSSL, ART, V8, Chrome, and multimedia libraries, and will push vendors to upstream platform support into the Linux kernel, U-Boot, and OpenSBI.

RVA23 is the specification watershed for RISC-V application processors. Getting Android 17 running on it and open-sourcing it means the most demanding combination—”mobile operating system + application processor specification”—now has a reproducible public baseline for the first time.

1.2 Linux 7.4 Crypto Library: Optimized AES Implementations for RISC-V and x86 Merged into lib/crypto

Date: 2026-10-21　Source: Phoronix: Linux 7.4 Kernel Crypto Library Enjoying Optimized AES Implementations On x86 & RISC-V (10-21)

Crypto subsystem performance work by Google kernel engineer Eric Biggers has been merged into Linux 7.4: optimized AES implementations for each mode on x86/x86_64 and RISC-V have been moved into the lib/crypto kernel crypto library.

  • Modes covered: ECB, CBC, CBC-CTS, CTR, XCTR, XTS—six in total; after the move, the library API gains acceleration directly on these architectures, and consumers on the crypto_skcipher side continue to benefit as well.
  • x86 side: Uses AVX-optimized code and AES-NI instructions; the RISC-V side uses accelerated implementations based on the vector and crypto extensions.
  • Incidental benefit: A large amount of duplicated glue code is cleaned up, reducing the maintenance surface. The same batch also includes an optimized AES-XTS implementation for SPARC64 by developer Stian Halseth.

For RISC-V, the value here is not “yet another optimization commit” but where it lands: accelerated implementations move from architecture-private directories into the generic library, so other in-kernel consumers (filesystem encryption, IPsec, dm-crypt, etc.) benefit without modification—a reusable gain at the infrastructure layer.

1.3 openRuyi: 20 SPECS Commits, uv’s Rust Dependencies Landed in Bulk

Date: 2026-10-22　Source: openRuyi main repo commit log (10-22), openRuyi official news page

The openRuyi main repo recorded 20 commits in the window, concentrated in a batch of SPECS additions in the early hours of 10-22, all rust-uv-* 0.0.96 series packages: pep440, pep508, platform-tags, pypi-types, options-metadata, normalize, toml, version, small-str, globfilter, git-types, fs, errors, logging, macros, redacted, static, preview, warnings, windows.

These packages are dependency components of uv (a Python package and project manager written in Rust). The previous daily briefing recorded 40 commits concentrated on Go cloud-native components such as minio, Prometheus, and sarama; this issue shifts to the Python toolchain. Taken together over two days, openRuyi is filling out the RISC-V distribution with two categories of software: “common data center services” and “Python development toolchain.” The latest announcement on the official news page is still the 2026.09 release; no new version was released within the window.

II. Product and Ecosystem Updates

2.1 Espressif ESP-Mosaico Goes on Sale: ESP32-S31 Modular AI Hardware Kit, Starting at $59

Date: 2026-10-21　Source: CNX Software: ESP-Mosaico — An ESP32-S31-based modular development platform for AI-assisted hardware creation (10-21), Mosaico Store

Espressif has launched ESP-Mosaico: a modular development platform built around the ESP32-S31, positioned at the intersection of “AI and hardware” and targeting magnetic snap-on expansion toys, motion sensing, square touch HMI, and edge voice/multimedia scenarios.

  • Core board: ESP32-S31NRV16 (320MHz RV32IMAFCP high-performance core + low-power MCU core, 512KB SRAM + 32KB low-power SRAM + 16MB PSRAM), Wi-Fi 6, Bluetooth 5.4 (including LE Audio, direction finding, Mesh 1.1 and Classic), 802.15.4; 128MB SPI NAND + 16MB SPI NOR.
  • HMI and peripherals: 2.16-inch 480×480 QSPI touchscreen (CO5300 + CST9220), NS4150B amplifier and ES8311 codec, dual BMM150 magnetometers, BMI270 6-axis IMU, vibration motor, USB-C power and flashing; the baseboard expands via a 60-pin board-to-board connector and includes a speaker and a 3.7V/65mAh battery.
  • Modularity: A camera module (OV3640 3.2MP or SC101IOT) and a multi-function interaction module (photoresistor, PIR, infrared LED, 6× WS2812, mechanical keys/capacitive touch pads) are already available.
  • Development approach: The official documentation offers two paths — natural-language “conversational coding” via ESP-Claw, and “vibe coding” via ESP-ZeroCode AI, with AI agents handling implementation, deployment, on-device testing, and iteration.
  • Pricing and status: The full kit including the camera and interaction modules is $59; the battery module is $15. It had already been sold on Taobao and through third-party channels for several months, and is now officially available through the official store.

It took only about two months for the ESP32-S31 to go from “preview part” to a finished kit (the first third-party development board appeared only on 10-14), and this generation makes the development experience itself the selling point: natural-language firmware generation and AI agents running on-device tests — a rare point of differentiation for RISC-V MCUs competing with the ARM ecosystem at the edge.

2.2 Radxa Linkr Releases v1.6.0

Date: 2026-10-21　Source: radxa-linkr/linkr: v1.6.0 (10-21)

Radxa Linkr has released v1.6.0, with a same-version commit appearing on the main branch the same day. The project is Radxa’s browser-based remote management product line for development boards and NAS devices, maintained across the main linkr repository plus six others: plugins, linkr-skills, linkr-docs, linkr-docs-en, and docs; during the window, all three documentation-site repositories and the main repository received pushes.

  • Release cadence: The previous version, v1.5.2, was released on 10-08, while v1.5.0/v1.4.2/v1.3.3/v1.3.0 clustered around 09-24, maintaining a biweekly release frequency over the past month.
  • Note: The repository release page does not include a changelog; this entry only records the release cadence and repository activity. Refer to the official documentation for specific features.

III. In-depth Look at Domestic Teams

3.1 DAMO XuanTie Opens CubeSandbox RISC-V Support Branch: CubeShim Connects to KVM/AIA VMM Backend

Date: 2026-10-21　Source: XUANTIE-RV/CubeSandbox: add_riscv_support branch (10-21), TencentCloud/CubeSandbox upstream repository

The add_riscv_support branch of CubeSandbox maintained by DAMO XuanTie (XUANTIE-RV) on GitHub saw new commits during this window: registering the riscv64-control-plane-demo.yml workflow for manual triggering. CubeSandbox is an AI Agent sandbox service open-sourced by Tencent Cloud (Apache 2.0, hardware-level isolation, millisecond-level startup, E2B interface compatible, already in the CNCF Landscape), and the XuanTie branch is precisely porting it to RISC-V.

  • Build path: make all-riscv64 can cross-compile the architecture-independent control plane, guest tools, Cubelet, and CubeVS/eBPF, with cross-build images generated automatically; the guest kernel is built separately with make guest-kernel KERNEL_TARGET_ARCH=riscv64.
  • Cold start: CubeShim has been switched to connect to the experimental RISC-V KVM/AIA VMM backend, supporting direct kernel cold start.
  • Current boundaries: On the RISC-V side, snapshot/restore remains disabled, pending implementation of vAIA state migration; no official release images or supported deployment paths are provided, so this is in the developer preview stage.

The code execution sandbox for AI Agents is one of the fastest-growing infrastructure categories this year, and its underlying layer depends on the completeness of virtualization and privileged instructions. By moving this stack onto RISC-V, XuanTie points to the specific proposition of “whether RISC-V servers can carry Agent workloads”—also the most direct application-side validation of RISC-V after the landing of AIA (Advanced Interrupt Architecture).

3.2 ESWIN Computing and SiFive Sign Gold Partner Alliance MOU, Expanding Cooperation from Edge AI to Agentic AI

Date: 2026-10-21　Source: NetEase (Huashang Taolue): ESWIN Computing and SiFive Sign Gold Partner Alliance MOU (10-21), Guandian: ESWIN Computing and SiFive Sign Gold Partner Alliance MOU to Deepen RISC-V+AI Cooperation (10-21)

ESWIN Computing and RISC-V processor IP company SiFive formally signed a Gold Partner Alliance Memorandum of Understanding (Gold Partner Alliance MOU). This is an international industry cooperation advanced by ESWIN Computing after its listing on the Hong Kong Stock Exchange on 10-09.

  • Basis for cooperation: ESWIN Computing’s EIC7700 SoC is already used in SiFive’s flagship development board HiFive Premier P550, providing a high-performance RISC-V hardware platform to global developers and already shipping at scale; the two sides’ technical collaboration already has verifiable products.
  • Upgrade direction: The cooperation expands from edge AI to applications such as Agentic AI, jointly exploring demand for low-power, high-performance AI solutions, and exploring multi-tier RISC-V product forms according to customer integration requirements.
  • Positioning of both sides: SiFive was founded by members of the RISC-V instruction set founding team and is strong in architecture and core IP; ESWIN Computing is strong in product implementation and commercialization, and describes itself as one of the leading domestic RISC-V main control chip providers.

Worth noting is the timing of the cooperation: ESWIN’s first publicly disclosed international cooperation after listing is not capacity or foundry, but an alliance upgrade with an IP supplier. In contrast to Qualcomm’s approach of directly acquiring IP teams during the same period, domestic vendors have chosen a hybrid route of “in-house cores + external IP alliances.”

3.3 Sophgo sophon-demo Completes CV84X6 Adaptation: Adds MiniCPM4, InternVL3, and MiniCPMV Samples

Date: 2026-10-21　Source: sophgo/sophon-demo commit records (10-21)

Sophgo’s example repository sophon-demo merged the commit “CV84X6 adaptation: MiniCPM4 + InternVL3 + MiniCPMV” into the release branch, adding three multimodal/on-device large model samples for the CV84X6 platform.

  • Model coverage: MiniCPM4 (on-device small-parameter language model), InternVL3 (multimodal vision-language model), MiniCPMV (ModelBest’s multimodal on-device model)—all three are oriented toward on-device deployment, consistent with the edge inference positioning of Sophgo’s SoCs.
  • Repository cadence: Recently the same repository has also added C++ samples for PaddleOCR-VL, SAM3, SAM2, BLIP, MP_SENet, and YOLO_world; the example library is expanding from Python reference implementations to engineering-oriented C++ samples.
  • Other commits in the same window: One commit on the zsbl main branch, moving application selection up to SoC-level Kconfig, a structural cleanup of the boot firmware.

The competitiveness of edge chips increasingly depends on “whether models can run once they arrive, and whether they run efficiently”—filling in samples for the hottest multimodal models of the year on one’s own platform is more practical than track marketing.

IV. Special Chapter on Embodied Intelligence and Robotics

4.1 Summit Automotive Electronics, Industrial and Robotics Sub-forum: Zijing M100 in Mass Production on Vehicles, IAR and Nuclei Complete the Toolchain and IP

Date: 2026-10-21　Source: People’s Daily Online (Beijing Youth Daily): The Golden Moment for Open Architectures — 2026 RISC-V China Summit Sub-forums Convey New Industry Signals (10-21)

A retrospective report on the seven parallel sub-forums of the 6th RISC-V China Summit (10-20) lays out the specific progress in the automotive electronics, industrial and robotics tracks:

  • Zijing Semiconductor: A chip company incubated by Great Wall Motor, whose Zijing M100 has become a mass-production, vehicle-installed RISC-V automotive-grade chip. An RISC-V automotive-grade product incubated inside an OEM moving from samples to mass production is the hardest evidence in this round of “getting onto vehicles” narratives.
  • IAR: From a toolchain perspective, it identified three major challenges for RISC-V in automotive, industrial and robotics domains, and launched RISC-V development tools, focusing on compliant development for safety-critical scenarios.
  • Nuclei: Shared its IP solutions for RISC-V in AI chips, emphasizing dynamic vector length, extensible instruction sets and a unified software ecosystem, covering full-scenario AI compute from cloud to MCU.
  • Zhaosong Technology: Participated in sessions on real-time control and automotive-grade MCU architecture implementation; the same sub-forum also featured Alibaba DAMO Academy presenting its automotive-grade roadmap.

The overall message of the sub-forum was that “RISC-V has moved from whether it can be used to being usable and commercial,” but when it comes down to engineering details, the discussion still centered on the three hard problems of safety certification, real-time control, and toolchain compliance—precisely the common threshold for robot joint control and automotive-grade chassis domain control.

4.2 On the Robot Compute Side, the Narrative Shifts from Financing to Mass-Production Validation: Joint Control Chips Already in Mass Production, Brain Chips Still in Tape-out

Date: 2026-10-21　Source: People’s Daily Online (Beijing Youth Daily): 2026 RISC-V China Summit Sub-forums Convey New Industry Signals (10-21), East Money: What Embodied AI Company AgiBot Invested in Across 47 Deals (10-20)

Within the 24-hour window, there were no new standalone financing rounds or full-robot launches in the embodied intelligence space; verifiable progress was concentrated in capacity and validation:

  • Mass-production side: XChip’s robot joint control chips are already in mass production; the mid-range compute XC64AE has started mass-production validation with leading embodied intelligence companies, and its first cerebellum chip has completed tape-out and returned from the fab; on the automotive side, shipments of its automotive-grade intelligent motor control MCU exceeded 1 million units, with 5.2 million units in new orders signed in 2026.
  • Not yet landed: The V1000 positioned as the brain (2.5D Chiplet, designed for 1000 TOPS) is still in tape-out, and the full second-generation XC64AE series is planned for tape-out in 2027.
  • Capital side: After AgiBot took a stake in XChip (Pre-A round), its investment portfolio has covered the robot body, key components and underlying compute chips; body makers are locking in upstream suppliers with capital, binding the instruction set choice at an early stage.

The significance of this thread lies in the pace gap: links such as the cerebellum and joint control—real-time, low-compute, certification-heavy—have entered mass production, while the high-compute “brain” chip is still in tape-out and benchmarking. The first wave of real RISC-V shipments in robotics is likely to come from joints and motion control, not general-purpose AI compute.

V. Summary and Trend Observations

  • Ownership of server IP is concentrating: Qualcomm has absorbed two RISC-V server IP teams, Ventana and Akeana, within ten months, and the number of independent IP suppliers is shrinking; domestically, open-source cores (XiangShan Kunminghu V2R2) are being put into commercial server chips (V100). Two events in the same week show that server-class RISC-V IP supply is splitting into two paths: “in-house assets of big vendors” and “productization of open-source cores.”
  • Android on RVA23 is a platformization milestone, not just another port: What RISE delivered this time is a locked manifest, checksums, flashing tools and a rebuild path, plus fully automated builds and Board Farm testing in the second phase. Reproducibility and regression capability are the real threshold for an application processor ecosystem.
  • Performance work is moving from architecture-private to general reuse: Linux 7.4 moves the AES mode implementations for RISC-V and x86 into lib/crypto, deleting duplicated glue code. Such changes are inconspicuous, but they automatically benefit upper-layer consumers such as encryption, storage and networking.
  • The layers being filled in by distributions are moving upward: openRuyi batch-imported Go cloud-native components the day before, and on this day packaged uv’s 20 Rust dependencies into SPECS. From the kernel and toolchain to Python development tools, the “daily usability” of RISC-V distributions is being filled in layer by layer.
  • Edge competition is shifting to developer experience: ESP-Mosaico’s selling points are a $59 kit, natural-language firmware generation, and AI agents running tests on real hardware. When chip specs converge, whoever shortens the path “from idea to hardware” is more likely to win developers.
  • Automotive-grade and robotics remain the main domestic deployment lines: Zijing M100 in mass production on vehicles, XChip’s joint control chips in mass production, and the ESWIN–SiFive IP alliance—these three lines correspond to complete vehicles, robotics and general IP supply, respectively. The summit’s tone was optimistic, but certification, real-time performance and toolchains remain the decisive variables.
  • Limitations: Qualcomm’s acquisition amount for Akeana, customer commitments and product integration plans have not been disclosed; the available information comes from Dealroom and Sammy Fans reports and confirmation on the parties’ social platforms, with no official Qualcomm press release seen; RISE’s Android 17 is a developer version and explicitly not for mass production; the Linux 7.4 crypto library item is based on Phoronix reporting and the patches were not checked one by one; the purpose of openRuyi’s uv dependency import was judged only from commit titles, with no distribution announcement seen; Radxa Linkr v1.6.0 came without a changelog; the summit sub-forum content comes from media retrospective reports, and vendor statements may not have been third-party verified; the changes detected in the member website inspection were all routine updates to the official websites of universities, institutions and vendors, with no substantive product, financing or architecture releases found; the XiangShan family and some key repositories showed pushes in pushed_at, but there were no new commits within the review window on the default branch, judged to be activity on non-default branches or PR head branches.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Google News aggregation (24 Chinese and English query sets, via proxy) 58 items after deduplication within the window; substantive news concentrated in two stories: Qualcomm’s acquisition of Akeana and the ESWIN–SiFive MOU; the summit sub-forum recap (People’s Daily Online, Guancha, TechWalker, Sohu) was included from a single pick; V100, UR-CP400, Tenstorrent, and XuanTie’s 6-billion-core shipment figures were second-hand reposts of content already covered on 10-19/10-20 and are not repeated this issue; Chinese queries for “Sophgo,” “Espressif,” and “ESWIN” returned large volumes of stock-market quotes, fund-flow, and lock-up-expiry articles, which were excluded
GitHub organization check (24-hour window) Pushes within the window: espressif 31, spacemit-com 9, radxa-linkr 4, sipeed 4, XUANTIE-RV 3, spacemit-robotics 3, openhwfoundation 3, sophgo 2, revyos 1, openRuyi-Project 1; eswincomputing and Nuclei-Software had no pushes within the window (most recent 10-19 and 10-14)
Key XiangShan repository check XiangShan (kunminghu-v3), XSCache, and GEM5 (xs-dev) default branches all had 0 commits in the atom review window; pushed_at for all three repos shows pushes on 10-21, judged to be activity on non-default branches or PR head branches, so not included as items this issue
openRuyi dual-source The official website news page still shows 2026.09 as the latest version, with no new release announcement in the window; the GitHub main repo had 20 commits in the window (a batch of uv Rust dependencies merged), included and referenced in 1.3
DAMO XuanTie (XUANTIE-RV) 3 repos pushed within the organization window: CubeSandbox (add_riscv_support branch, riscv64 control-plane demo workflow), bcc and xuantie-yocto (no new commits on the default branch 1.0/master within the window, judged to be branch-level syncs); CubeSandbox included and referenced in 3.1
ESWIN, Nuclei, Sophgo, and Sipeed eswincomputing had 0 pushes in the window; Nuclei-Software 0 pushes; sophgo had 2 repo pushes (sophon-demo’s CV84X6 multimodal adaptation included and referenced in 3.3; zsbl was boot-firmware Kconfig cleanup); sipeed’s 4 repo pushes centered on logic analyzers (SLogicWeb, slogic16u3-tools) and the NanoKVM multi-user permission system, which are product-line iterations and did not meet the daily-brief item threshold
spacemit-com and spacemit-robotics spacemit-com had 9 repo pushes, mainly revisions to docs-chip’s V100 product introduction and K3 hardware guide, the bibit file-search plugin, and small-step iterations of spine-runtime and model-zoo-vision; spacemit-robotics had 3 repo pushes (peripherals_led, manifest, realtime-link), all supporting engineering work, not listed as separate items
Radxa Linkr (6 repos) 4 repos pushed; the main repo released v1.6.0 and the three documentation repos were updated in sync, included and referenced in 2.2
RISC-V International member website sweep (391 sites) Took 209 seconds: 227 unchanged, 87 with content changes, 77 failed to fetch; changes concentrated in routine updates to university, research-institute, and vendor websites (NVIDIA blog, TUM admissions page, Greek and Czech university homepages, etc.); no substantive RISC-V product, funding, or architecture announcements detected
RVSC2026 official website and source repo monitoring No changes (sitemap, 11 key pages, and source repo all unchanged; source HEAD still 10-20 22:06), not listed as a separate item this issue
riscv.org blog and email subscription No new substantive RISC-V-related articles in the window; the RISE project blog’s Android 17 entry is included and referenced in 1.1
Pending-inclusion queue The queue directory contains a 2026-10-22 file, but it holds only FlagOS daily-brief items and notes that other topics should not be taken from it; there were no pending RISC-V daily-brief items this issue, and nothing was moved