Research window: 2026-10-20 05:00 ~ 2026-10-21 05:00 (Beijing time, 24 hours; continuing from the cutoff of the previous daily report).

Sources: Google News aggregation (21 query groups in Chinese and English, via proxy), Hacker News, Phoronix, CNX Software, LinuxGizmos, riscv.org, the openRuyi official news page, website inspections of RISC-V International member companies (391 companies), monitoring of the official website and source code repositories of the 6th RISC-V China Summit, and push and commit searches across GitHub organizations and key repositories including XiangShan/NEMU/GEM5/difftest/XSCache, DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT, Sipeed, revyos, openRuyi-Project, Radxa Linkr, and OpenHW.

Index

  • Today’s Highlights: BlueCore Computing releases the ZhiTong Fusion Super Node, RISC-V AI compute moves from single chips to clusters (10-20)
  • I. Open Source Community and Software Ecosystem
    • openRuyi: 40 commits in a single day, Go ecosystem packages merged in batches (10-20)
    • OpenHW CVW: QM Tech K7 development board support merged, new page table A/D bit regression tests added (10-20)
    • riscv.org: CERN discloses progress on SoCMake and TriglaV radiation-tolerant RISC-V SoC (10-20)
  • II. Product and Ecosystem Developments
    • Ruixin Gaoguang D35 debuts at the Summit: RISC-V dataflow architecture, runs a 35B model locally with 128GB memory (10-20)
    • Zhongke Tongliang full-stack RISC-V product line: 12-core AI workstation, video encoding all-in-one machine, and intelligent computing accelerator card (10-20)
  • III. In-depth Coverage of Domestic Teams
    • DAMO XuanTie: first disclosure of autonomous driving and embodied intelligence roadmap, C950A targets a 5x performance improvement (10-20)
    • SpacemiT completes B+ round of financing: Qiming Venture Partners, Shenzhen Capital Group, CMBI, and Biyi Shares among investors (10-20)
    • Espressif esp-emu 0.50.0: P4/S31 fused multiply-add sped up by about 3x, P4 video memory window follows the MMU (10-20)
  • IV. Special Chapter on Embodied Intelligence and Robotics
    • MIIT: humanoid robot output exceeded 40,000 units in the first half of the year, set to surpass 100,000 units for the full year (10-19)
    • AgiBot invests in 47 companies over two years, Plan A to incubate more than 50 early-stage projects in three years (10-20)
    • Summit 10-21 Hong Kong Day: Demo Talk venue confirmed, agenda and speakers continuously updated (10-20~21)
  • V. Summary and Trend Observations

Today’s Highlights: BlueCore Computing releases the ZhiTong Fusion Super Node, RISC-V AI compute moves from single chips to clusters

Date: Released 2026-10-19 (widely reported on 10-20)　Sources: Economic Information Daily: BlueCore Computing releases the ZhiTong Fusion Super Node (10-20), Securities Daily Online: BlueCore Computing releases the ZhiTong Fusion Super Node (10-20), 36Kr: BlueCore Computing releases the ZhiTong Fusion Super Node, RISC-V accelerates expansion into new AI inference scenarios (10-20), PEdaily: BlueCore Computing releases the ZhiTong Fusion Super Node (10-20)

On the third day of the 6th RISC-V China Summit (10-19), BlueCore Computing (Shenzhen) released the ZhiTong Fusion Super Node, advancing RISC-V-based AI computing capabilities from single chips and servers to clustered computing infrastructure. On the same day, CTO Jia Xinxia delivered a keynote titled “LX500: Unlocking a New Path for AI Inference.”

  • Architectural proposition: Traditional “CPU + discrete accelerator card” solutions rely on PCIe to move data between different memory spaces, and the long context and first-token latency of large model inference are amplified by bandwidth and power consumption. ZhiTong Fusion integrates general-purpose computing and AI computing on the same chip and uses a unified memory architecture to reduce data movement; the super node is an extension of this approach toward larger-scale systems.
  • Chip specifications: The LX500 integrates 48 RISC-V cores (32 performance cores + 16 efficiency cores), along with AI Vector and Matrix compute engines, delivering 75 TOPS INT8 of AI compute and supporting multiple precisions from INT4 to FP32; it shares DDR5 memory resources and supports CXL expansion.
  • Product cadence: The chip powered on in February 2026, made its first public appearance in April, an all-in-one prototype was released in May, the Lenovo Wentian WR5219 G5 server equipped with the LX500 debuted in July, and since August samples have been sent to multiple industry customers and entered small-batch deployment testing. This has formed a four-tier product matrix: LX500 chip, WR5219 G5 server, LX5000 ZhiTong Fusion all-in-one machine, and ZhiTong Fusion Super Node.
  • Software and scenarios: Adaptation work has been carried out around large models such as Qwen, DeepSeek, and Kimi, covering different parameter scales, different precisions, and long-context scenarios; deployment directions include enterprise private knowledge base RAG, Agent office assistants, financial compliance inference, government offline Q&A, and industrial on-site inspection.

I. Open-Source Community and Software Ecosystem

1.1 openRuyi: 40 commits in a single day, Go ecosystem packages merged in batches

Date: 2026-10-20　Source: openRuyi main repo commit log (10-20), openRuyi official news page

The openRuyi main repo recorded 40 commits during the window, concentrated in a batch merge on the morning of 10-20: the minio series (server build switched to not using bundled vendor dependencies, plus a new console, the mc client, and madmin-go v3), Prometheus and prom2json, IBM sarama (TLS helper functions retained), gobwas-ws (DEFLATE compatibility and dependency fixes), xdg-scram (library dependencies completed), technosophos-moniker, plus two new packages, uwsgi and dropwatch. The focus of this batch is the cloud-native and message middleware stack, indicating that what openRuyi is filling in on RISC-V is not just the compilation toolchain but also commonly used data-center server software. The latest announcement on the official news page is still the 2026.09 release; no new version was released during the window.

1.2 OpenHW CVW: QM Tech K7 board support merged, new page-table A/D bit regression test added

Date: 2026-10-20　Source: openhwfoundation/cvw commit log (10-20)

The open-source core verification platform CVW (CORE-V Wally) merged 3 commits during the window: added support for the QM Tech K7 development board (PR #1601, further expanding FPGA board-level support), and added the hptwReservedAD regression test (PR #1993), providing targeted coverage for A/D bit update behavior on reserved leaf PTEs. For CVW, which is known for formal verification and regression suites, filling in such edge-case tests reflects verification maturity more than new features do. The CVA6 main branch under the same organization had no new commits during the window.

1.3 riscv.org: CERN discloses progress on SoCMake and the TriglaV radiation-tolerant RISC-V SoC

Date: 2026-10-20　Source: RISC-V International: SoCMake — Modular RISC-V SoCs for Radiation-Harsh and Safety-Critical Environments (10-20)

The RISC-V International blog published a summit poster paper from the CERN team (Benoît Denkinger et al.): SoCMake, developed under the SOCRATES (System-on-Chip Radiation-Tolerant Ecosystem) project, is used to modularly build radiation-tolerant RISC-V SoCs for high-energy physics; the companion prototype chip TriglaV is a fully radiation-tolerant ASIC targeting harsh-radiation environments such as LHC detector front-end readout. The technical combination presented in the paper—triple modular redundancy, hardened interconnect, memory protection—also applies to safety-critical scenarios in automotive and industrial control, with the goal of extending optimization from the design phase to the in-field operation phase.

II. Product and Ecosystem Updates

2.1 RICORE’s Gaoguang D35 Debuts at the Summit: RISC-V Dataflow Architecture, Running a 35B Model Locally with 128GB Memory

Date: 2026-10-20　Source: Shanghai Securities News (reposted by Sohu): When RISC-V Meets Dataflow, RICORE Delivers a New High-End Domestic AI Chip Answer (10-20), CSDN: RISC-V China Summit Opens, On-Site Photos of RICORE’s Gaoguang D35 (10-20)

Suzhou RICORE showcased its Gaoguang D35 chip at the summit: 128GB memory, Chiplet packaging, capable of running a 35B-parameter large model locally, with the booth also displaying a sign that its core IP has passed Intel’s global procurement validation. Its technical approach is “RISC-V + dataflow” — the dataflow architecture lets computation happen where data arrives, bypassing the power overhead of instruction scheduling and data movement, while RISC-V provides an autonomous and controllable instruction set foundation; the company calls it the world’s first mass-produced RISC-V dataflow physical AI chip (company claim). Target scenarios include embodied intelligence, video intelligence, smart campuses, cockpit-driving integration, satellites, and communications; the company also claims revenue exceeding RMB 100 million in 2024 and break-even in 2025.

2.2 Zhongke Tongliang’s Full-Stack RISC-V Product Line: 12-Core AI Workstation, Video Encoding Appliance, and Intelligent Computing Accelerator Card

Date: 2026-10-20　Source: CSDN: Zhongke Tongliang Appears at the 2026 RISC-V China Summit, Full-Stack RISC-V Intelligence Covering All Video + Intelligent Computing Scenarios (10-20), Official Website of the 6th RISC-V China Summit

Beijing Zhongke Tongliang exhibited under the theme “Full-Stack RISC-V Intelligence, Covering All Video + Intelligent Computing Scenarios,” showcasing three product categories:

  • SmarCo AI Workstation: A desktop-class high-performance intelligent computing terminal with a 12-core RISC-V processor at 2.0GHz, 250 TOPS INT8 compute, 128GB LPDDR5 ECC unified memory, support for real-time hardware decoding of 128 channels of 1080P HD video, and all interfaces opened up for research and debugging.
  • SmarCo Intelligent Video Encoding Appliance: Focused on video encoding without changing the existing architecture.
  • SmarCo Intelligent Computing Accelerator Card: An acceleration solution for existing AI frameworks.

The company says its core team has over 20 years of accumulated video intelligence experience, has won both the large and small dataset global championships of GreenGraph 500, holds more than 140 granted patents in total, and has R&D staff accounting for over 50%; its technical path is “dataflow-native architecture × RISC-V open ecosystem.”

III. In-Depth Look at Domestic Teams

3.1 DAMO XuanTie: First Public Roadmap for Autonomous Driving and Embodied Intelligence, C950A Targets 5x Performance Gain

Date: 2026-10-20　Sources: Sina Tech (KuaiTech): Accelerating RISC-V Adoption in Vehicles, Alibaba DAMO Academy First Publishes Automotive-Grade Processor Product Roadmap (10-20), Sohu (Drivehome): DAMO Academy First Publishes Automotive-Grade Processor Product Roadmap (10-20), Weibo Long Post: XuanTie Shipments Exceed 6 Billion Units, DAMO Academy Fills Out Software and Hardware Ecosystem (10-20)

Yesterday’s daily already covered XuanTie’s 6 billion unit shipments and the automotive-grade E908A (dual ASIL certification, single-point safety metric SPFM above 90%); today’s additions are the roadmap and ecosystem-side data:

  • Product roadmap: DAMO Academy for the first time published an automotive-grade processor roadmap targeting autonomous driving and embodied intelligence, with C925A, C930A, and C950A to follow the E908A, among which C950A targets 5x the overall performance of the first-generation automotive-grade product.
  • Server side: C950 serves as the high-performance foundation, paired with the multi-core interconnect product XT-LINK to further improve multi-core performance linearity; C950 is the first to achieve deep adaptation between RISC-V and server-side Java, with a 30% performance gain.
  • Open-source contributions: RISC-V-related contributions to the GCC community rank second worldwide, delivering more than 10% typical performance gains for the processor; more than half of the RISC-V code in the OpenJDK community comes from DAMO Academy; it participates in CSC certification baseline construction at RISC-V International and has open-sourced 2796 test cases.
  • Frontier collaboration: Together with the Beijing Institute of Open Source Chip and ZTE Microelectronics, it has achieved interim results on spatial multithreading (SMT), with a 30% performance gain from dual threads; it participates in building the Ruyi community of the Institute of Software, Chinese Academy of Sciences, and works with more than 20 institutions at home and abroad to advance software adaptation for the matrix computation AME extension.

3.2 SpacemiT Completes B+ Round: Qiming Venture Partners, Shenzhen Capital Group, CMBI, and Biyi Shares Among New Investors

Date: 2026-10-20　Sources: Sohu (Dahe Cube): Qiming Venture Partners and Others Invest in SpacemiT (10-20), Stockstar: Biyi Shares Adds a New Outbound Investment, in SpacemiT (Beijing) Intelligent Technology Co., Ltd. (10-21)

Business registration change information shows that SpacemiT (Beijing) Intelligent Technology Co., Ltd. has completed a B+ round, with new investors including Qiming Venture Partners, Guoxiang Capital, Shangqi Capital, Woan Robotics, C&D Emerging Investment, Biyi Shares, CMBI, Shenzhen Capital Group, and Yaotu Capital. Listed company Biyi Shares (603215) disclosed the outbound investment on the evening of 10-20, which was relayed by financial media in the early hours of 10-21.

The capital move comes hard on the heels of the product cadence: on 10-19 SpacemiT had just unveiled its server-class CPU V100 at the summit (6 XiangShan Kunminghu V2R2 cores + 40 in-house X100 cores, 46 cores, 8-channel DDR5), alongside three classes of complete systems for compute, intelligent computing, and storage. Taking the cloud product line from launch to mass production and ecosystem building requires a new round of funding — the most direct reading of this round.

3.3 Espressif esp-emu 0.50.0: P4/S31 Fused Multiply-Add Roughly 3x Faster, P4 PSRAM Window Follows the MMU

Date: 2026-10-20　Source: espressif/esp-emulator: esp-emu 0.50.0 (10-20)

Espressif’s open-source emulator esp-emu 0.50.0 was released on 10-20, with RISC-V-side changes concentrated on ESP32-P4/S31/C3:

  • Performance: Single-precision fused multiply-add on P4 and S31 now takes a host passthrough path, roughly 3x faster, with math functions such as sinf, expf, and powf benefiting accordingly, while results and flag bits remain consistent.
  • Memory model: The P4 PSRAM window now follows the PSRAM MMU, so firmware that remaps the external memory window at runtime no longer reads all zeros and no longer traps on illegal instructions.
  • Bug fixes: The BLE transmit power API on C3 and S3 no longer triggers a Load access fault after the controller is enabled; P4 boot for rev 0.x/1.x firmware is now rejected early on the emulator side, with two fixes offered: switch to the corresponding ROM or recompile.

The more precisely the emulator aligns with silicon behavior, the more viable it becomes as a substitute for real hardware in RISC-V endpoint firmware CI — which is the practical value of Espressif’s continued investment in this toolchain.

IV. Special Chapter on Embodied Intelligence and Robotics

4.1 MIIT: Humanoid Robot Output Exceeded 40,000 Units in the First Half of the Year, Set to Break 100,000 Units for the Full Year

Date: Published 2026-10-19 (widely reported on 10-20)　Sources: Sina Tech (IT Home): China’s humanoid robot output exceeded 40,000 units in the first half of this year, expected to break 100,000 units for the full year (10-19), Sohu (Nanfang Plus): MIIT says China’s humanoid robot output exceeded 40,000 units in the first half of the year (10-20)

The State Council Information Office held a press conference on 10-19. Wei Wei, Director-General of the Department of Science and Technology of MIIT, stated: in the first half of this year, China’s humanoid robot complete-machine products exceeded 400 models, with output surpassing 40,000 units, and are expected to break 100,000 units for the full year; related products have been validated and deployed across more than 300 key scenarios, including warehousing and logistics, food and retail, and home services. Next steps include: using humanoid robots as a small entry point to drive the embodied intelligence industry, tackling key common technologies through the “open competition” mechanism, advancing real-world training, publishing the 2026 edition of the National Humanoid Robot Industry Standards System Construction Guide, building a high-quality humanoid robot open-source community, and establishing an industry monitoring system while strengthening quality and data security testing.

Interface with RISC-V: This scale simultaneously amplifies cost and energy-efficiency pressure across the “body—joints—controller” chain, and embodied intelligence chips are precisely where domestic RISC-V teams are currently most concentrated (Xinji Infinite’s full-stack RISC-V chips, SpacemiT’s robot perception stack, and Ruixin’s deployments in embodied intelligence scenarios). The two policy levers—the open-source community and the standards system—also directly address the software and interface specifications that the RISC-V side has long lacked.

4.2 AgiBot Invests in 47 Companies Over Two Years; Plan A to Incubate 50+ Early-Stage Projects in Three Years

Date: 2026-10-20　Sources: [Dahe Cube: AgiBot invested in 47 companies over two years list (10-20)](https://app.dahecube.com/article.html?artid=290407), Sina Finance: AgiBot’s investment landscape (10-20)

According to Cailian Press Chuangtoutong—Zhizhong data, AgiBot has invested in 47 companies within two years and established at least 17 new companies through joint ventures, reaching cooperation—including capital participation—with more than 40 listed companies; the “AgiBot Plan A” launched this year aims to incubate 50+ early-stage projects within three years. The investment thesis is clear: on one end, direct investment in body and large-model companies (Digital Huaxia, Shouxing Technology, Lingchu Intelligence, Xingyuanzhi Robotics); on the other,锁定 key components (Qianjue Robotics, Linghou Robotics, Fuxing Motor). On shipment cadence, the company expects several thousand units this year and tens of thousands next year.

Connection to RISC-V: AgiBot is a co-investor in Xinji Infinite’s Pre-A round on 10-19, and Xinji Infinite focuses precisely on full-stack RISC-V chips for embodied intelligence. Body manufacturers binding upstream chips through capital means the instruction-set choice for embodied intelligence is locked in by industry capital at an early stage—a hidden thread worth tracking this year.

4.3 Summit 10-21 Hong Kong Day: Demo Talk Venue Confirmed, Agenda and Speakers Continuously Updated

Date: 2026-10-20 ~ 10-21　Sources: 6th RISC-V China Summit official agenda (10-21), Summit official website source repository commit log (10-20)

The main session of the 6th RISC-V China Summit (10-18 ~ 10-20, Shenzhen Convention & Exhibition Center Futian) has concluded. 10-21 is RISC-V Hong Kong Day, held at City University of Hong Kong, ICP Room B-101, from 9:00 to 17:10. The summit website and source repository saw two more updates within the window: on 10-20, the Demo Talk venue was added as Sunflower Hall 5F, and confidential computing speaker information was updated; the source repository had 3 commits within the window (HEAD 10-20 22:06), with the agenda page text growing from 15,316 to 15,343 characters.

V. Summary and Trend Observations

  • RISC-V’s AI narrative is upgrading from “chip” to “system”: Bluecore Computing pushes intelligent-computing integration from single chips to supernodes, Ruixin uses a dataflow architecture to handle local inference of 35B models, and Zhongke Tongliang directly offers a trio of workstation + all-in-one machine + accelerator card. All three coincidentally bypass “benchmarking general-purpose CPUs” and instead organize compute around inference scenarios—the clearest industry signal this issue.
  • Domestic teams’ differentiation lies at the architecture layer, not the process layer: dataflow (Ruixin, Zhongke Tongliang), unified memory and CXL (Bluecore), SMT and AME matrix extensions (DAMO)—under advanced-process constraints, these are performance gains that can be recovered through design. DAMO’s five-fold target for the C950A is essentially an extension of the same logic.
  • Software stack completion is shifting from toolchains to server-side middleware: among openRuyi’s 40 commits in a single day, cloud-native components such as minio, Prometheus, sarama, and uwsgi account for the bulk; Espressif, meanwhile, brings emulator silicon consistency down to the single-instruction level. The former determines whether RISC-V servers can handle real business workloads; the latter determines the iteration speed of edge firmware.
  • Capital and products are starting to synchronize: SpacemiT released the V100 on 10-19 and closed its B+ round on 10-20—a one-day gap; AgiBot ties bodies and upstream chips together with 47 investments. Compared with the past two years’ “raise first, then find scenarios,” this year’s order looks more like “ship products first, then replenish ammunition.”
  • The policy foundation for embodied intelligence is taking shape: MIIT gives a full-year expectation of 100,000 units and explicitly plans to publish the 2026 edition of the standards system construction guide and build a humanoid robot open-source community. For RISC-V, this is a window to write chips, middleware, and scenario interfaces into the specifications together.
  • Limitations: The number of chips per node, interconnect method, and delivery timeline for Bluecore Computing’s supernode are not public; existing reports offer only directional statements. Ruixin’s “world’s first mass-produced RISC-V dataflow physical AI chip” and “Intel global procurement recognition” are both company claims, with no public confirmation from Intel. Zhongke Tongliang’s product specifications come from the vendor’s public presentation at the summit, lacking third-party testing. The MIIT data was released on 10-19, and this issue’s inclusion is based on the press conference transcript and concentrated reporting on 10-20. Changes detected in the member website inspection are all routine homepage updates at universities and institutions, with no substantive product, funding, or architecture announcements found. The XiangShan repository organization-side pushed_at shows pushes, but atom re-checks of the default branch found no new commits within the window, judged to be non-default-branch activity.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Google News aggregation (21 queries in Chinese and English, via proxy) 127 items after deduplication within the window; substantive news concentrated on the third day of the summit and closing coverage: Lanxin Computing super node, Ruixin Gaoguang D35, Zhongke Tongliang full-stack product line, DAMO Academy automotive-grade roadmap, SpacemiT B+ round — all included; V100, E908A, UR-CP400, ZhuFeng 200, and Tenstorrent are secondary reposts of content already included on 10-19 and are not repeated in this issue; Chinese queries for “Sophgo” and “ESWIN” returned large volumes of stock market updates and lock-up expiration releases unrelated to RISC-V computing business, and were excluded
GitHub organization check (24-hour window) Pushes within the window: espressif 44, openhwfoundation 4, sipeed 3, spacemit-com 2, sophgo 1, openRuyi-Project 1; XUANTIE-RV, eswincomputing, Nuclei-Software, spacemit-robotics, revyos, radxa-linkr had no pushes within the window (most recent: 10-15, 10-19, 10-14, 10-19, 10-19, 10-15 respectively)
Key XiangShan repository check XiangShan (kunminghu-v3), NEMU, and difftest default branches all had 0 commits in the atom review window (NEMU’s latest release remains v2026.10.r7 from 10-17); pushed_at for all three repos shows pushes on 10-20, judged to be non-default branch or PR head branch activity, not included as items in this issue
openRuyi dual-source Official website news page latest remains the 2026.09 version, no new version announcement within the window; GitHub main repository had 40 commits within the window (Go ecosystem and cloud-native components merged in batches), included — see 1.1
DAMO Academy XuanTie (XUANTIE-RV) 0 pushes within the organization window (most recent 10-15); all XuanTie developments in this issue come from the summit (automotive-grade and embodied roadmap, GCC and OpenJDK contributions, SMT and AME collaboration), noted in the body text as product- and ecosystem-side progress
ESWIN, Nuclei, Sophgo, and Sipeed eswincomputing had 0 pushes within the window (linux-stable and opensbi most recent commits are 10-19 mirror syncs, no substantive updates to main branch content); Nuclei-Software 0 pushes; sophgo only 1 commit in zsbl (fixing SMP configuration symbol naming under the RISC-V architecture, as the original naming is no longer recognized in upstream builds); sipeed had pushes in 3 repos (SLogicWeb 16 commits for frontend splitting and on-demand loading of USB drivers, slogic16u3-tools 8 commits for test cases), belonging to logic analyzer product line iteration, below the daily briefing item threshold
spacemit-com and spacemit-robotics spacemit-com had pushes in 2 repos (ai-sdk 3 commits for submodule updates, model-zoo-vision 3 commits for threshold validation and pose parameter fixes), belonging to supporting iteration after the V100 release; spacemit-robotics had no pushes within the window (perception most recent 10-19)
RISC-V International member website inspection (391 sites) Took 178 seconds; 305 unchanged, 21 with content changes, 65 failed to fetch; changes concentrated in routine updates to university, research institute, and semiconductor vendor websites (DFRobot, NXP, Microchip, Marvell Asia, European Space Agency, INESC TEC, etc.), with no substantive RISC-V product, funding, or architecture announcements detected
RVSC2026 official website and source repository monitoring Official website sitemap latest lastmod is 10-16; agenda page grew from 15,316 to 15,343 characters, adding the 10-20 Demo Talk venue (Sunflower Hall 5F) and updating the confidential computing speaker; source repository had 3 commits within the window (HEAD 10-20 22:06) — included as 4.3
riscv.org blog 1 new post within the window (SoCMake/TriglaV), included — see 1.3
Pending inclusion queue No pending items in this issue (no files for the day in the queue directory)