Research window: 2026-10-19 05:00 ~ 2026-10-20 05:00 (Beijing time, 24 hours; continuing from the cutoff of the previous daily report).

Sources: Google News aggregation (14 query sets in Chinese and English, via proxy), Hacker News, Phoronix, CNX Software, LinuxGizmos, riscv.org, the openRuyi official news page, website inspections of RISC-V International member companies (391 companies), monitoring of the official website and source code repositories of the 6th RISC-V China Summit, and push and commit searches on GitHub (XiangShan / NEMU / GEM5 / difftest / XSCache, DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT, Sipeed, revyos, openRuyi-Project, Radxa Linkr, OpenHW and other organizations and key repositories).

Index

  • Today’s Highlights: SpacemiT and XiangShan jointly release the server-class CPU V100, the industry’s first chip fully compliant with the RISC-V server specification (10-19)
  • I. Open Source Community and Software Ecosystem
    • Linux 7.3 officially released: RISC-V adds RVA23 identification, counter delegation and KVM extensions (10-19)
    • XiangShan: XSCache merges coupled L2 banked SRAM and prefetch admission throttling (10-19)
    • openRuyi: dpdk backports RISC-V lpm and fib lookup optimizations, spdk upgraded to 26.09 (10-19)
  • II. Product and Ecosystem News
    • Lizrui Micro, under ZTE Microelectronics, first reveals the Everest 200 intelligent computing center RISC-V CPU (10-19)
    • Tenstorrent closes a $1.5 billion Series E round at a post-money valuation of $6.2 billion (10-19)
    • UltraRISC UR-CP400 processor core unveiled: RVA23, 8-wide out-of-order, SPECint above 22 points per GHz (10-19)
  • III. In-depth Coverage of Domestic Teams
    • DAMO XuanTie: shipments exceed 6 billion units, unveils the first dual-ASIL-certified automotive-grade CPU IP E908A (10-19)
    • Xinji Wuxian completes Pre-A round: AgiBot and Anhui state capital join as investors, focusing on full-stack RISC-V chips for embodied intelligence (10-19)
    • Sophgo: batch deployment tool rewritten in Go and Fyne, sophon-demo adds multiple C++ samples (10-19)
  • IV. Special Chapter on Embodied Intelligence and Robotics
    • Ubitium closes a $14 million seed round: reconfigurable RISC-V array targets physical AI (released 10-13, Chinese coverage 10-19)
    • Summit 10-20 agenda finalized: Demo Talk added, automotive electronics, industrial and robotics sub-forums held today (10-19~20)
    • SpacemiT robotics perception stack: plane reconstruction falls back to CPU image decoding when VDEC is unavailable (10-19)
  • V. Summary and Trend Observations

Today’s Focus: SpacemiT and XiangShan Jointly Release Server-Class CPU V100, the Industry’s First Chip Fully Compliant with the RISC-V Server Specification

Date: 2026-10-19　Sources: EETrend: SpacemiT Releases Server-Class CPU V100 (10-19), Shenzhen News: SpacemiT Releases Server-Class CPU V100 (10-19), Phoronix: SpacemiT Announces The V100 Server-Class RISC-V Processor (10-19), 21st Century Business Herald: First Chip Fully Compliant with the RISC-V Server Specification Released (10-19)

On the second day of the 6th RISC-V China Summit (10-19), SpacemiT and the XiangShan team jointly released the server-class CPU V100, alongside three categories of complete servers: compute, AI compute, and storage. The company calls it the industry’s first general-purpose compute chip fully compliant with the RISC-V server specification.

  • Specification coverage: The server specification is implemented across three layers—chip, firmware, and operating system—covering five specifications: RVA23, server SoC, server platform, Boot and Runtime Services (BRS), and security model. The BRS specification tests pass in full, and the chip supports direct installation, boot, and operation of mainstream Linux distributions including openEuler, openRuyi, openKylin, Debian, Ubuntu, Fedora, Red Hat, and Rocky, eliminating the need for a separately customized OS for each chip.
  • Microarchitecture: A 46-core hybrid design—6 XiangShan Kunminghu V2R2 cores plus 40 in-house X100 cores, with a maximum clock of 2.4 GHz and dual-socket coherent interconnect scaling up to 92 cores; a single chip provides 8-channel DDR5-4800 and 52 PCIe 5.0 lanes. Process and power (per overseas media) are 12nm and 120W TDP, with support for UEFI, ACPI, and SMBIOS.
  • Essentials for the data center: Supports the H extension, AIA, and IOMMU, with hardware virtualization of CPU, memory, interrupts, and I/O; the virtualization extensions are natively supported upstream in Linux, requiring no custom kernel. It integrates a hardware root of trust on-die and supports RISC-V native TEE, plus the RERI RAS specification. For cloud Agent applications, it offers a lightweight virtual machine approach that achieves VM-level isolation at resource overhead close to that of containers.
  • Complete systems and ecosystem: C2201 compute server, G5201 AI compute server, and S5236 storage server; the G5201 supports 8 full-height, full-length, double-width accelerator cards, has validated domestic accelerators such as Kunlunxin M100, and supports high-speed RDMA networking. Companion motherboards, firmware, BMC management, and hardware reference designs are open to external parties.
  • Statement: Founder and CEO Chen Zhijian said, “V100 is not only an important step for SpacemiT from edge to cloud, but also represents RISC-V moving toward a truly deployable, scalable data center market.”

I. Open Source Community and Software Ecosystem

1.1 Linux 7.3 Officially Released: RISC-V Adds RVA23 Detection, Counter Delegation, and KVM Extensions

Date: 2026-10-18 (media coverage 10-19)　Source: Phoronix: Linux 7.3 Released (10-18), Kernel Newbies: Linux 7.3 changelog

Linux 7.3 was released on schedule on October 18. On the RISC-V side, this release includes: hwprobe now exposes the RVA23U64 base behavior, allowing user space to directly determine whether a machine is RVA23-compliant; support for counter delegation-related extensions (Smcdeleg/Ssccfg/Smcntrpmf) and resctrl support for Ssqosid and CBQRI; KVM adds FWFT support for Svadu, Zicfiss, and Zicfilp; shutdown and reboot now use EFI runtime services; arm64 and RISC-V both gain crashkernel CMA reservation support; alternative section boundaries are statically computed to fix vDSO compatibility, and xip support is further removed. On the platform side, an initial device tree for StarFive JHB100 and support for Canaan K230 (a 64-bit RISC-V AI SoC) are added; detection and enumeration are also added for extensions including Smcsrind/Sscsrind, Zicclsm, Ziccamoa, Ziccif, Ziccrse, and Za64rs. For distributions, RVA23 detectability is a key step from “guessing via Kconfig” to “determining at runtime.”

1.2 XiangShan: XSCache Merges Coupled L2 Banked SRAM and Prefetch Admission Throttling

Date: 2026-10-19　Source: XSCache PR #36 (10-19), XiangShan PR #6738 (10-19), GEM5 PR #1241 (10-19)

The main XiangShan repo (kunminghu-v3) had 1 commit in the window: #6738 bumps the XSCache submodule version. On the cache side, XSCache #36 is a substantive performance commit—it splits CoupledL2’s L2 SRAM by set and bank and throttles prefetch admission, targeting two issues: last-level cache bandwidth contention and prefetch pollution. On the simulation side, GEM5 (xs-dev) #1241 fixes the out-of-order model: when store and AMO sends fail, it skips the replay flag in the load pipeline, avoiding incorrect replay accounting. The reference model NEMU and the difftest main branch had no new commits in the window (the most recent was the CRC check overhead optimization on 10-16).

1.3 openRuyi: dpdk Backports RISC-V lpm and fib Lookup Optimizations, spdk Upgraded to 26.09

Date: 2026-10-19　Source: openRuyi main repo commit log (10-19), openRuyi official news page

The openRuyi main repo had 15 commits in the window, with two performance-related ones most worth noting: dpdk backports RISC-V lpm and fib lookup optimizations, directly affecting the virtual switching and routing forwarding paths; spdk is upgraded to 26.09, following the upstream storage stack version. On the packaging side, the Rust ecosystem continues to be filled in as a group: rust-brotli-7, brotli-decompressor-4, botan-0.10, alloc-stdlib-2, alloc-no-stdlib-2, winreg-0.52, sequoia-man-0.3, and self-replace-1 are added, while rust-regex is upgraded to 1.13.1, regex-automata to 0.4.18, and regex-syntax to 0.8.11; go-gopkg-h2non-gock is upgraded to 1.2.0 and duplicate providers are cleaned up. During the same period, lookout, kiwi-image, and TakoPack within the organization also had pushes. The latest version on the official news page remains 2026.09 (released September 30; this version improves RVA23 support, expands the cloud and storage software stack, and upgrades the Go 1.27 build environment), with no new version announcement in the window.

II. Product and Ecosystem Updates

2.1 ZTE Microelectronics’ subsidiary Lirui Micro unveils Zhifeng 200, a RISC-V CPU for intelligent computing centers

Date: 2026-10-19　Source: 21st Century Business Herald (STAR Market Daily): ZTE Micro’s subsidiary Lirui Micro debuts high-performance RISC-V chip for intelligent computing centers (10-19), NetEase: Lirui Micro’s RISC-V chip debuts (10-19)

During the 6th RISC-V China Summit, Lirui Micro, a subsidiary of ZTE Microelectronics, publicly showcased for the first time Zhifeng 200, a high-performance RISC-V CPU chip built for intelligent computing centers. The company describes it as the industry’s first RISC-V CPU chip targeting intelligent computing center scenarios, focusing on three use cases: Agent clusters, inference super-node hosts, and enterprise-grade hybrid intelligent computing inference. It natively features RISC-V AI instruction acceleration and is optimized for KV Cache and long-context LLM inference. On the hardware side, it integrates multiple acceleration engines for Matrix, Vector, compression, and encryption, supports high-speed interconnect interfaces including DDR5, PCIe, and CXL, and can accommodate a “RISC-V native AI + GPU accelerator card” MoE hybrid inference solution. Detailed product specifications will be officially released at the end of this year; this issue only confirms the direction and scenarios, with performance data not yet disclosed.

2.2 Tenstorrent closes $1.5B Series E at a $6.2B post-money valuation

Date: 2026-10-19　Source: Tenstorrent press release: Tenstorrent Announces a $1.5B Series E at a $6.2B valuation (10-19), Dealroom: Tenstorrent raises $1.5B Series E (10-19), Quartz: Tenstorrent raised $1.5 billion (10-19)

Tenstorrent announced on October 19 that it had closed a $1.5 billion Series E at a $6.2 billion post-money valuation, more than double its valuation of roughly $2.6 billion in 2024, making it one of the largest Series E rounds for a U.S. semiconductor company. The round was co-led by newly formed Trace Capital (founder Ben Mahdavi) and Innovation X, with participation from Fidelity, T. Rowe Price, Morgan Stanley, Sandisk, Tether Investments, Cadence Ventures, ARK Invest, Agostinelli Group, and others. The funds will be used for volume production and global commercialization expansion, and to drive Galaxy servers toward large-scale deployment. The outcome contrasts with reports two days earlier that “Intel and Qualcomm were simultaneously in acquisition talks”—media say the company chose to reject a sale and raise independently. Tenstorrent, led by Jim Keller, is a leading company in high-performance RISC-V AI acceleration and IP.

2.3 UltraRISC’s UR-CP400 processor core debuts: RVA23, 8-wide out-of-order, SPECint above 22 points per GHz

Date: 2026-10-19　Source: Sohu (90 Says Tech): UltraRISC appears at the 2026 RISC-V China Summit (10-19)

UltraRISC showcased its UR series high-performance RISC-V processor cores and multi-scenario system-level solutions based on UR-DP1000 in the summit’s core exhibition area. The highlight of this generation is UR-CP400: it complies with the RVA23 specification, supports RVV 1.0, adopts an out-of-order, 8-wide, 14-stage pipeline microarchitecture, and achieves SPECint_base2006 above 22 points per GHz under an FPGA emulation configuration; it adds virtualization enhancements for multi-tenant cloud environments and targeted hardware optimizations for Agentic AI, with an FPGA prototype system demonstrated on site. The UR-CP400 IP is scheduled for delivery in Q1 2027. The company also presented a layered product lineup spanning processor core IP, multi-core CPU chips, and AI edge, multi-node cluster, and virtualization applications. CTO Jiang Jiang gave a technical talk at the data center and high-performance computing sub-forum.

III. In-depth coverage of domestic teams

3.1 DAMO XuanTie: Over 6 billion units shipped, first dual-ASIL-certified automotive CPU IP E908A released

Date: 2026-10-19　Source: Eastmoney (Shanghai Securities News): Meng Jianyi says XuanTie chips have shipped over 6 billion units stably (10-19), Sohu (TMTPost): DAMO releases automotive-enhanced processor XuanTie E908A (10-19), IT Home: XuanTie chips shipped over 6 billion units (10-19), UDN: RISC-V accelerates penetration into end devices (10-19)

At the summit, DAMO chief scientist Meng Jianyi said cumulative XuanTie chip shipments have stably exceeded 6 billion units (first surpassing 4 billion in 2024), and cited an Omdia forecast: by 2030, global RISC-V processor annual shipments will grow nearly 30% year over year, accounting for about 25% of global processor shipment share.

At the same event, the automotive-enhanced processor XuanTie E908A was released: officially described as the first RISC-V CPU IP to simultaneously meet ASIL-B and ASIL-D standards, with a single-point fault metric (SPFM) exceeding 90% for the first time in the industry, providing a real-time computing foundation for scenarios such as safety islands, domain controllers, and automotive gateways. DAMO also released its autonomous driving and embodied intelligence product roadmap for the first time, with the next-generation C950A targeting 5x the performance of existing RISC-V automotive products. On the hardware side, there were no new open-source repository commits this period (0 pushes in the XUANTIE-RV organization window; the most recent was the 10-15 update to the ATS/extension specification repositories). This period’s XuanTie developments centered on IP products and the roadmap, representing commercial-side progress.

3.2 Xinji Infinite completes Pre-A round: AgiBot and Anhui state capital join, focusing on full-stack RISC-V chips for embodied intelligence

Date: 2026-10-19　Source: Eastmoney (Jiemian News): Xinji Infinite completes Pre-A round (10-19), Sina Tech (CVSource): Xinji Infinite completes Pre-A round (10-19), NetEase (Wenxin): Tsinghua-affiliated RISC-V chip company raises tens of millions; AgiBot strategic investment (10-19)

Shanghai Xinji Infinite Intelligent Technology announced on October 19 the completion of a Pre-A round, jointly invested by AgiBot together with the Anhui Automotive Innovation Center, Guoyuan Equity, and Hefei Baohe Venture Capital, with total funding in the tens of millions of RMB; Wanchuang Investment Bank served as financial advisor. The funds will focus on R&D and industrialization of full-stack RISC-V chips for embodied intelligence. This round is the formal disclosure of the “AgiBot strategic investment” item from the previous daily briefing, adding details on the investor composition, amount, and advisor.

Additional company facts: founded in 2023 (originally named “Xinche Infinite”), renamed in 2026 and completed Tsinghua Huakong technology transfer with core RISC-V intellectual property contributed as equity; it is Tsinghua’s only technology-transfer RISC-V AI chip company in which Tsinghua holds equity; the core team has been engaged in RISC-V R&D since 2016. Two product lines:

  • Automotive XC32 series: the XC32MC body motor control MCU is already in volume production on vehicles, with over 1 million units shipped and 5.2 million units in new orders signed in 2026, with customers including JAC and Chery; XC32LS (ASIL-D dual-core lockstep) has taped out and lit up, entering testing with automakers and Tier-1 suppliers, with mass production in 2027; XC32DC central domain control is planned for design-win and mass production in 2028.
  • Embodied intelligence XC64AE series: the cerebellum chip XC64AE (12-core RISC-V + in-house NPU) has taped out and returned from the fab for its first product, with a standardized development solution launched; the cerebrum chip V1000 is based on 2.5D Chiplet with planned compute of 1000 TOPS; the joint control chip is already in mass production; the full second-generation XC64AE series is planned to tape out in 2027.

3.3 Sophgo: batch deployment tool rewritten in Go and Fyne; sophon-demo adds multiple C++ samples

Date: 2026-10-19　Source: sophgo/sophon-tools commit history (10-19), sophgo/sophon-demo commit history (10-19)

Two product lines saw concentrated updates in the Sophgo window, both focused on deployment efficiency rather than chip specifications:

  • sophon-tools: 7 commits in one day: the batch deployment tool pqt_batch_deployment was rewritten in Go + Fyne, producing a single binary for both Linux and Windows; subsequent versions progressed to 2.1.0 adding a Web UI and headless builds without a graphics stack, 2.2.0 reworking the desktop GUI and Web UI visuals, 2.3.0 supporting LAN scanning and batch device discovery and addition by MAC prefix, and 2.4.0 adding a no-MAC fallback mode (Ping only). Separately, seskill now pre-builds the vector index when packaging and binds the index to document content (bmssm 2.3.18 / se-rag-core 1.4.0).
  • sophon-demo: added C++ samples in one batch for SAM, SAM2, SAM3, YOLO_world, YOLO_world_v2, D-FINE, Recognize-Anything, FearTracker, MP_SENet, and BLIP (mostly in both opencv and bmcv implementations), and cleaned up invalid download and script references for tpu-mlir and TPU-NNTC; also added four skill documents covering quantization calibration, accuracy alignment, performance profiling, and delivery checks.

Summit sidelights: the 10-19 main forum lightning talks scheduled Sophgo’s “Natively running 100-billion-parameter large models: new RISC-V intelligent computing server launch” and the Beijing Institute of Open Source Chip’s “XiangShan product launch”; specific specifications of both launches are subject to the vendors’ subsequent announcements.

IV. Special Chapter on Embodied Intelligence and Robotics

4.1 Ubitium Closes $14M Seed Round: Reconfigurable RISC-V Array Targets Physical AI

Date: 2026-10-13 (reported by Chinese media on 10-19)　Sources: Ubitium press release (10-13), Evertiq: Ubitium raises $14M (10-16), Zhidx: Ubitium raises $14M (10-19)

German Düsseldorf-based startup Ubitium announced the close of a $14 million new seed round, led by Ibex Investors with participation from OpenOcean, and follow-on investment from existing shareholders KBC Focus Fund, Runa Capital, and Inflection, bringing cumulative seed funding to $18 million. The company is building a reconfigurable RISC-V array (CGRA approach): a set of programmable processing units dynamically allocates three workload classes—signal processing, AI inference, and real-time control—according to software configuration, replacing the multi-chip stack of “DSP + NPU + CPU” with unified memory and a standard RISC-V toolchain, targeting physical AI scenarios in drones, robots, vehicles, and industrial equipment. The first validation chip, UB108, is built on Samsung 8nm with 256 processing units and has demonstrated all three compute classes running on the same array; the first commercial chip, UB410, is planned with 4096 processing units, with evaluation samples scheduled for delivery in 2027. This direction stands in contrast to the domestic “automotive-grade + embodied” dedicated SoC approach: one pursues specialization, the other reconfigurable generalization.

4.2 Summit 10-20 Agenda Finalized: Demo Talk Added; Automotive Electronics, Industrial & Robotics Sub-forums Held Today

Date: 2026-10-19~10-20　Sources: 6th RISC-V China Summit official agenda, Summit official website source repo commit log (10-19)

The summit website finalized the 10-20 agenda overnight on 10-19 (7 commits in the source repo, HEAD updated to 10-19 23:40): the agenda overview added a “Demo Talk” tab; the 10-20 core logic analyzer session saw speaker changes (Saifuldeen A. Mohammed joined, Sajosh became sole speaker); Hu Qingwei’s affiliation was changed to ByteDance; and Wang Cong and Huang Yanwei were confirmed for the same session. As scheduled, seven sub-forums are held on 10-20, among which the Automotive Electronics, Industrial & Robotics sub-forum, co-chaired by Xu Tao of StarFive and Yang Yong of WCH, is today’s first-hand window into RISC-V deployment in embodied intelligence and in-vehicle applications; 10-21 is Hong Kong Day. The summit website sitemap’s latest lastmod remains 10-16, with the only page-side change being the agenda page.

4.3 SpacemiT Robotics Perception Stack: Planar Reconstruction Falls Back to CPU Image Decoding When VDEC Is Unavailable

Date: 2026-10-19　Source: spacemit-robotics/perception PR #10 (10-19)

One push in the spacemit-robotics org during the window: perception #10 “planar pipeline falls back to CPU JPEG decoding when VDEC is unavailable”. This repo hosts the planar reconstruction pipeline for robot vision; after several consecutive weeks of adjusting feature-detection parameter scoping, ONNX Runtime linking, and model-download robustness, this issue adds a degradation path for when hardware video decoding is missing—for robot systems built on edge chips such as K3 as their compute base, this is a usability fix ensuring “it runs even without hardware decoding,” not a performance optimization. No other repos in the same org saw pushes during the window.

V. Summary and Trend Observations

  • Server specifications move from “document” to “product”: V100 lands five specifications—RVA23, server SoC, server platform, BRS, and security model—across the chip, firmware, and OS layers in one go, with all BRS tests passing and mainstream distributions directly installable. This means RISC-V servers are beginning to shed the embedded inertia of “one chip, one system” and move toward the x86-style general-purpose platform model—the most structural step this issue.
  • Open-source cores enter commercial server chips for the first time: 6 of V100’s 46 cores are XiangShan Kunminghu V2R2. Open-source high-performance cores are no longer merely academic and validation objects but are entering sellable data-center products as IP, giving the XiangShan “open source → product” path a verifiable sample.
  • Intelligent computing centers become a new competitive front: Zhufeng 200 explicitly targets Agent clusters, inference super-node Hosts, and hybrid inference; G5201 has validated the Kunlunxin M100 and supports RDMA networking; plus Sophgo’s teased RISC-V intelligent computing server—all three are pushing the “CPU + domestic accelerator card” combination toward inference clusters rather than point-to-point competition with general-purpose servers.
  • Base software simultaneously fills in determinability: Linux 7.3 makes RVA23 determinable at runtime via hwprobe and completes counter delegation, QoS identifiers, and KVM’s Svadu and shadow stack extensions; openRuyi backports RISC-V lpm/fib lookup optimizations into dpdk. The former solves “how do I know I’m RVA23,” the latter “once I know, can the performance be delivered.”
  • Capital remains polarized: Tenstorrent closed a $1.5 billion Series E at a $6.2 billion valuation and explicitly refused to sell, in stark contrast to the domestic Xinji Wuxian’s tens-of-millions-of-yuan Pre-A; but both direct funds toward “mass production and scenario deployment” rather than architecture validation. XuanTie’s 6 billion units shipped and E908A’s dual ASIL automotive certification offer another path—trading scale for ecosystem.
  • Limitations: V100’s 12nm/120W process and power figures come from overseas media reports; the official Chinese release does not list these two items. Zhufeng 200 has only disclosed scenarios and interfaces; specifications and performance are subject to its year-end launch. The summit lightning talks by Sophgo and the Beijing Institute of Open Source Chip are agenda arrangements; specific product specifications have not been confirmed by public materials. Ubitium’s funding was announced on 10-13; inclusion in this issue is based on Chinese media reports on 10-19. Changes detected in the member website inspection are all routine homepage updates by universities and institutions; no substantive product, funding, or architecture announcements were found.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Google News aggregation (14 queries in Chinese and English, via proxy) 95 items after deduplication within the window: V100 launch, XuanTie 6 billion units and E908A, Zhufeng 200, Xinji Wuxian Pre-A, Tenstorrent Series E, and Linux 7.3 are substantive news and all included; Chinese queries for “Espressif,” “Sophgo,” and “ESWIN” returned large numbers of listed-company announcements and market reports (cash management, equity incentives, Xi’an ESWIN lock-up expiry, etc.), which are unrelated to RISC-V and were excluded; “Ubitium” is secondary coverage of a 10-13 release, with the original date noted
GitHub organization check (24-hour window) Pushes within the window: espressif 33, openhwfoundation 6, spacemit-com 4, sipeed 4, openRuyi-Project 4, eswincomputing 2, sophgo 2, spacemit-robotics 1, revyos 2; XUANTIE-RV, Nuclei-Software, and radxa-linkr had no pushes within the window (most recent: 10-15, 10-14, and 10-15 respectively)
Key XiangShan repo check XiangShan (kunminghu-v3) 1 commit (bump XSCache); XSCache 1 commit (L2 SRAM split by set/bank and prefetch throttling); GEM5 (xs-dev) 1 commit (skip replay flags on store/AMO send failures); NEMU and difftest main branches had no new commits within the window (most recent 10-16)
openRuyi dual-source Official website news page latest is still the 2026.09 version (released 9-30), with no new version announcement within the window; GitHub main repo 15 commits (dpdk RISC-V backport, spdk 26.09, grouped Rust package updates, included and covered in 1.3), with additional pushes in the organization for lookout/kiwi-image/TakoPack
DAMO Academy XuanTie (XUANTIE-RV) 0 pushes in the organization within the window (most recent 10-15); all XuanTie developments in this issue come from the summit (6 billion units, E908A, automotive and embodied intelligence roadmap), noted in the main text as product and commercialization progress
ESWIN Computing and Nuclei (eswincomputing/Nuclei-Software) eswincomputing had 2 repo pushes (linux-stable, opensbi), but the latest main-branch commits date back to 2024, being mirror syncs with no substantive content; Nuclei-Software had no pushes within the window; ESWIN-related news consists entirely of announcements about Xi’an ESWIN (688783) restricted-share circulation and similar matters, unrelated to the RISC-V computing business, and was excluded
RISC-V International member website inspection (391 organizations) Took 180 seconds: 224 unchanged, 99 with page content changes, 68 failed to fetch; changes concentrated in routine homepage updates at universities and research institutions (carousels and announcements at MIT, NUS, imec, LBNL, FURG, etc.), with no substantive RISC-V product, funding, or architecture announcements detected
RVSC2026 official website and source repo monitoring Official website sitemap latest lastmod is 10-16, with no new pages; agenda page grew from 14,519 to 15,316 characters, adding a Demo Talk tab and adjusting 10-20 speakers; source repo had 7 commits within the window (HEAD 10-19 23:40) — included as 4.2
revyos / platform distributions The batch configuration commits on the revyos/linux 7.3.y branch dated 10-19 match the content of the 20-commit batch already covered in the 10-16 daily report (K3/K1/EIC7700/linuxboot/CI), judged to be re-pushes rather than new additions, and not re-included in this issue
riscv.org blog and openRuyi news page No new articles or version announcements within the window
Pending-inclusion queue No pending items in this issue (no files for the day in the queue directory)