Research window: 2026-10-16 05:00 ~ 2026-10-19 05:00 (Beijing time, 72 hours; covers Saturday and Sunday, continuing from the previous briefing’s cutoff).

Sources: Google News aggregation (30+ query sets in Chinese and English, via proxy), Hacker News, CNX Software, LinuxGizmos, OSChina, the riscv.org blog, the openRuyi official news page, website inspections of RISC-V International member companies (391 companies), monitoring of the 6th RISC-V China Summit official website and source repositories, and GitHub (push and commit searches across organizations and key repositories including XiangShan/NEMU/difftest/GEM5/XSCache, DAMO XuanTie XUANTIE-RV, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT, Sipeed, revyos, openRuyi-Project, Radxa Linkr, and OpenHW).

In This Issue

  • Today’s Highlights: The 6th RISC-V China Summit opens in Shenzhen, with today’s main forum agenda unveiled (10-18~19)
  • I. Open-Source Community and Software Ecosystem
    • XiangShan: Kunminghu V3 expands the ROB to 160 entries; GEM5 adds two-thread SpMT resource partitioning (10-16)
    • openRuyi: main repo merges 6 Rust ecosystem packages in a single commit, filling out bare-metal and driver development components (10-16)
    • meta-riscv: linux-mainline bumped to 7.2.11, riscv-common switched to prioritizing mainline kernels and U-Boot (10-16~19)
  • II. Product and Ecosystem Developments
    • Tenstorrent reportedly in sale talks with both Intel and Qualcomm, valuation possibly exceeding $5 billion (10-17)
    • AI agent completes full-flow design of a RISC-V cryptographic SoC: ~$2,000 in compute cost, 20 mW power consumption (10-16)
  • III. Deep Dive on Domestic Teams
    • Ruisi Core Technology completes strategic financing: Renjun Capital and Shuimu Fund take stakes, continuing to double down on RISC-V server CPUs (10-16)
    • ESWIN Computing’s first week post-IPO: HK$33.8 billion market cap, human-machine interaction still accounts for 76% of revenue (10-17)
    • SpacemiT’s llama.cpp fork releases v0.2.3: merges K3 decode state optimization and syncs with upstream (10-16)
    • Sophgo zsbl: splits each cpusys into its own application subdirectory (10-16)
  • IV. Special Chapter: Embodied Intelligence and Robotics
    • AgiBot takes a strategic stake in Xinji Infinite: RISC-V humanoid robot compute moves toward a dedicated foundation (10-18)
    • Summit robotics track: 10-20 features automotive electronics, industrial, and robotics sub-forums; embodied intelligence penetration expected to rise to 28.2% (10-17~19)
  • V. Summary and Trend Observations

Today’s Focus: The 6th RISC-V China Summit Opens in Shenzhen, Today’s Main Forum Agenda Revealed

Date: 2026-10-18 (opening) / 2026-10-19 (main forum)　Sources: 6th RISC-V China Summit official agenda, NetEase: RISC-V Summit opens in Shenzhen on the 18th; main control chips grow from 1.1 billion to 37.7 billion in five years (10-18), 21st Century Business Herald: RISC-V bellwether — 2026 China Summit fully upgraded (10-13)

The 6th RISC-V China Summit opened on October 18 at the Shenzhen Convention and Exhibition Center (Futian), running for three days through October 20. Organizers expect more than 3,600 on-site professional attendees and over 450 exhibitors and research institutions. Four concurrent tracks ran on the first day (10-18): Member Day / Workshops / Community Exchange (Narcissus Hall), the GPGPU track (organized by Tsinghua University, featuring progress and hands-on sessions on the open-source Ventus GPGPU and an SPMP Workshop), the AI for RISC-V track (three parts, with Part 2 covering “RISC-V AI practice based on the RuyiAI system software stack: from RVV to AME”), and the XiangShan processor track (high-performance architecture evolution and industrial-grade verification, UCAgent agent practice, and a processor IP security verification platform).

Today (10-19) is the opening ceremony and main forum day: the opening ceremony runs 9:00–12:20 and the main forum 13:30–17:40, both in Plum Blossom Hall. The pre-announced schedule shows:

  • Remarks: Dai Lu, Chairman of the RISC-V International Foundation, and Tan Zhangxi, Summit Chair and Co-Director of the RISC-V International Open Source Laboratory.
  • Morning: Andrea Gallo (CEO, RISC-V International), “The Architecture of Intelligence: Delivering the Future of Computing from Data Center to Edge”; David Patterson (Professor Emeritus, Berkeley; Turing Award laureate), “RISC-V in the AI Era”; Rong Zhicheng, “From RISC-I to RISC-V — Forty Years, the ‘China Moment’ of RISC”; Meng Jianyi (DAMO), “Technological Innovation and Open Ecosystem of XuanTie IP”; Chen Zhijian (SpacemiT), “From Edge to Cloud: The Next Leg of RISC-V”.
  • Afternoon: Krste Asanović (Chief Architect, RISC-V International; Co-founder, SiFive), “RISC-V State of the Union”; Aniket Saha (Tenstorrent), “AI Acceleration: From Data Center to Edge”; Zhou Meng (China Electronics Standardization Association) on the scaling inflection point and standardization; He Ning (ESWIN), “RISC-V + AI Driving Digital Infrastructure Reconstruction”; Jia Xinxia (Lanxin Computing), “LX500: Unlocking a New Path for AI Inference”. The lightning talk session includes ZTE Microelectronics, SiFive, Synopsys, Chaorui Technology, Sophgo, MIPS, Beijing OpenXiang Institute, Cadence, and others.
  • Points to watch: The official agenda page still marks 10-19 as “detailed agenda coming soon,” so the speakers and order above are subject to the on-site schedule; the seven sub-forums on 10-20 (AI, data center and high-performance computing, software ecosystem, embedded IoT and smart hardware, chip design and verification, industry-academia collaboration and innovation/entrepreneurship, automotive electronics industry and robotics) and the Hong Kong Day on 10-21 are subsequent windows to watch.

I. Open-Source Community and Software Ecosystem

1.1 XiangShan: Kunminghu V3 Expands ROB to 160 Entries; GEM5 Adds Two-Thread SpMT Resource Partitioning

Date: 2026-10-16　Source: XiangShan PR #6730 (10-16), GEM5 xs-dev #1231 (10-16), NEMU PR #1246 (10-16), NEMU PR #1252 (10-16)

The main XiangShan repository (kunminghu-v3) merged #6730: expanding the reorder buffer (ROB) capacity to 160 entries, a parameter-level performance adjustment to the out-of-order execution window that directly increases the number of instructions that can be in flight simultaneously. On the simulation side, GEM5 (xs-dev branch) merged #1231: adding middle-end resource partitioning for two-thread SpMT, targeting isolation and quotas when multiple threads share front-end/rename resources. On the verification side, two PRs landed in the same window: NEMU #1246 adds a Kunminghu V2 (kmhv2) configuration and aligns common fixes between V2 and V3, so the reference model covers both microarchitecture generations; #1252 reduces the overhead of DiffTest memory CRC checks. No new commits landed on the difftest or XSCache main branches during this window.

1.2 openRuyi: Six Rust Ecosystem Packages Merged into Main Repo in One Batch, Completing Bare-Metal and Driver Development Components

Date: 2026-10-16　Source: openRuyi main repo commit log (10-16)

Maintainer luojia65 submitted 6 SPECS packages to the openRuyi main repository in a single batch: rust-riscv 0.16, rust-riscv-macros 0.4, rust-riscv-types 0.1, rust-embedded-hal 1, rust-volatile-register 0.2, and rust-vcell 0.1. These packages cover the RISC-V bare-metal runtime, embedded HAL abstractions, and low-level register access, forming the foundational dependencies for Rust in RISC-V bare-metal and driver scenarios; for the distribution, this means Rust support extends from the compiler itself to runtime components entering the packaging system as a group. No new release announcements appeared on the official news page this period (latest remains 2026.09).

1.3 meta-riscv: linux-mainline Bumped to 7.2.11, riscv-common Switches to Preferring Mainline Kernel and U-Boot

Date: 2026-10-16~10-19　Source: riscv/meta-riscv commit log (10-16~10-19)

The Yocto layer meta-riscv saw 14 commits in this window: linux-mainline was bumped from 7.2.10 to 7.2.11; riscv-common was adjusted to prefer mainline Linux and U-Boot, reducing reliance on vendor BSP branches; documentation added boot and UART instructions for SpacemiT K3 Pico-ITX, K3 COM260, and LicheePi-4A, and set KERNEL_IMAGETYPE=Image for freedom-u540. The distribution build layer is converging toward mainline, in line with the recent platform consolidation moves by openRuyi and RevyOS.

II. Product and Ecosystem Developments

2.1 Tenstorrent Reportedly in Sale Talks with Both Intel and Qualcomm, Valuation Could Exceed $5 Billion

Date: 2026-10-17　Source: Startup Fortune: Intel and Qualcomm Both Court Jim Keller’s AI Chip Startup Tenstorrent (10-17)

According to Bloomberg (as relayed by Startup Fortune), RISC-V AI chip company Tenstorrent is separately negotiating a potential sale with Intel and Qualcomm and has engaged investment banks to evaluate the deal, with a valuation that could exceed $5 billion; following the report, Intel shares rose as much as 6.4% intraday. Intel, Qualcomm, and Tenstorrent all declined to comment. Tenstorrent, led by Jim Keller, is a representative company in RISC-V high-performance AI acceleration and IP; in June this year, reports emerged that Qualcomm was in talks to acquire it for $8–10 billion, which Keller denied at the time. The matter remains at the media-report stage and has not been confirmed by any party.

2.2 AI Agent Completes Full RISC-V Crypto SoC Design Flow: ~$2,000 Compute Cost, 20 mW Power

Date: 2026-10-16 (original report 10-15)　Source: Tencent News (Kuai Technology): Threshold Collapses! AI Designs a RISC-V Chip for 14,000 Yuan (10-16)

Semiconductor blogger @bubbleboi used Meta’s Muse AI agent to complete the full flow of a RISC-V crypto-specific SoC from logic design to place-and-route: consuming approximately 100 million tokens at a compute cost of about $2,000; using OpenROAD to complete place-and-route and generate a tape-out-ready GDSII layout. The design contains approximately 61,590 logic cells, runs at 100 MHz, consumes 20 mW, and has 4.5 ns timing margin, passing DRC checks and validation against 1.5 million Berkeley TestFloat vectors. The author is seeking multi-project wafer (MPW) shared tape-out opportunities. The result has not yet been silicon-verified and is a personal experiment, but it provides a reproducible data point on the cost curve of “AI participating in chip design.”

III. In-depth Look at Domestic Teams

3.1 Ruisi Core Completes Strategic Financing: Renjun Capital and Shuimu Fund Take Stakes, Further Betting on RISC-V Server CPUs

Date: 2026-10-16　Source: Sohu (Dahe Caicube): Ruisi Core Completes Strategic Financing (10-16)

Ruisi Core (Shenzhen) has completed a new round of strategic financing, with investors including Renjun Capital and Shuimu Fund; the amount was not disclosed. Founded by Tan Zhangxi, the company’s team comes from the original RISC-V project group at UC Berkeley and previously launched China’s first fully self-developed RISC-V server processor, “Lingyu”; it had earlier completed a Series B led by Shenzhen Heavy Investment state capital. This round’s funds will be used for R&D on RISC-V server-class high-performance processors and cloud-native CPUs. Tan Zhangxi also serves as co-director of the RISC-V International Open Source Laboratory (RIOS) and delivered remarks at today’s summit opening ceremony.

3.2 ESWIN Computing’s First Week After Listing: Market Cap HK$33.8 Billion, Human-Machine Interaction Still 76% of Revenue

Date: 2026-10-17　Source: Sina Finance (China Business Journal): ESWIN Computing Breaks Issue Price on Debut, RISC-V Still Awaits Large-Scale Commercialization (10-17)

ESWIN Computing (01256.HK), listed on the Hong Kong Stock Exchange on 10-09, has seen its first post-listing market assessment: it closed at HK$1.535 on the first day, down 0.97%, with a market cap of about HK$33.8 billion; revenue for 2023–2025 was RMB 1.752/2.025/2.431 billion, adjusted net profit was −1.705/−1.440/−1.161 billion, and gross margin ranged from 14% to 18%; human-machine interaction chips still account for 76% of revenue, with average selling price falling from RMB 20.9 to RMB 11.6. Based on 2025 revenue, it ranks fifth in China’s RISC-V main control chip market and third among domestic vendors, with a 1.2% share (the top five together hold 22.5%).

3.3 SpacemiT llama.cpp Fork Releases v0.2.3: Merges K3 Decode State Optimization and Syncs with Upstream

Date: 2026-10-16　Source: llama.cpp v0.2.3 Release (10-16), PR #48: perf/k3-decode-state (10-16)

The mtmd-backend branch of spacemit-com/llama.cpp released v0.2.3: it merges #48 (K3 decode-stage state reuse optimization) and #47 (sync with upstream version 20261014), and updates the version number. The branch maintains a cadence of roughly one release every 1–3 weeks (v0.2.2 was released on 10-13), continuously improving the usability and performance of K1/K3 on-device inference.

3.4 Sophgo zsbl: Splits Each cpusys into Separate Application Subdirectories

Date: 2026-10-16　Source: sophgo/zsbl commit history (10-16)

Sophgo’s zsbl (ZScale Boot Loader) saw one structural change in the window: each cpusys is split into a separate application subdirectory, making it easier to maintain boot code separately for different chip platforms. This is an engineering refactor on the boot firmware side with no functional changes; sophon-tools also had pushes during the same period.

IV. Special Chapter on Embodied Intelligence and Robotics

4.1 AgiBot Takes Strategic Stake in Xinji Infinite: RISC-V Humanoid Robot Compute Moves Toward a Dedicated Foundation

Date: 2026-10-18　Source: Sohu (Semiconductor Industry Panorama): AgiBot Strategically Invests in Xinji Infinite! Doubling Down on the Tsinghua-Linked RISC-V Embodied Intelligence Compute Track (10-18)

AgiBot has taken a strategic stake in Tsinghua-linked RISC-V AI chip company Xinji Infinite. Xinji Infinite is the only RISC-V AI chip enterprise that Tsinghua University has technologically transferred and holds equity in; its team has been engaged in RISC-V research since 2016, and in 2026 Tsinghua Huakong Technology Transfer took an equity stake valued with core RISC-V intellectual property. On the product side:

  • XC64AE (cerebellum chip): 12 RISC-V cores plus a self-developed NPU, balancing motion control and mid-range environmental perception; the first chip has taped out and returned, and a standardized development solution has been launched; V1000 (brain chip) is based on 2.5D Chiplet with a nominal 1000 TOPS; joint control chips are already in mass production, and the full second-generation XC64AE series is planned to tape out in 2027.
  • Automotive-grade XC32 series: the XC32MC body motor control MCU is already in volume production in vehicles, with cumulative orders exceeding 5 million units; XC32LS complies with ASIL-D, has taped out and lit up, and is planned for mass production in 2027; XC32DC central domain control is expected to reach design win and mass production in 2028.
  • Significance: Beyond Tesla’s in-house FSD and NVIDIA’s Jetson general-purpose platform, Xinji Infinite has chosen a third path of “fully self-developed RISC-V + trimmable instruction extensions + Chiplet”; AgiBot brings complete-machine scenarios and measured data, accelerating the chip’s transition from samples to mass-production validation.

4.2 Summit Robotics Sessions: 10-20 Sub-forums on Automotive Electronics, Industry and Robotics; Embodied Intelligence Penetration Expected to Rise to 28.2%

Date: 2026-10-17~10-19　Source: 6th RISC-V Summit China Official Agenda, Securities Times: RISC-V Major Summit to Be Held, Industry Space Expected to Exceed RMB 200 Billion (10-17)

The summit will hold an “Automotive Electronics, Industry and Robotics” sub-forum on 10-20 (co-chairs: Xu Tao of StarFive and Yang Yong of WCH), and the main forum also schedules a sharing by Zero Dynamic Robot on RISC-V architecture applications in embodied intelligence. On the market side, Frost & Sullivan data shows: RISC-V’s penetration in China’s embodied intelligence chips is expected to rise from 10.7% in 2025 to 28.2% in 2030, and in smart terminals from 6.9% to 26.7%; China’s RISC-V main control chip market is expected to grow from about RMB 37.7 billion in 2025 to about RMB 219.4 billion in 2030.

V. Summary and Trend Observations

  • The summit has entered the “agenda fulfillment” stage: the pre-summit warm-up of agendas, exhibitors and speakers over the past two weeks is over; the 10-19 main forum and the seven sub-forums on 10-20 are first-hand material for testing the “ecosystem maturity” narrative; the two main threads of AI and data centers (DAMO AME, ESWIN RISC-V + AI, BlueCore LX500) are concentrated in the main forum’s afternoon session.
  • Capital sentiment is clearly diverging: the primary market continues to add positions (AgiBot’s stake in Xinji Infinite, Ruisi Core’s strategic investment), while the secondary market gives a “rationally cool” valuation (ESWIN broke its issue price on its first trading day, and A-share RISC-V concept stocks have averaged a pullback year to date). The mismatch between long-term industry space (RMB 219.4 billion by 2030) and near-term profit realization remains the main valuation theme.
  • Three software stack progress lines: on the microarchitecture side, XiangShan improves performance and verification coverage through ROB expansion and dual-version NEMU configuration; on the distribution side, openRuyi adds Rust runtime components and meta-riscv converges toward the mainline kernel/U-Boot; on the on-device inference side, SpacemiT’s llama.cpp maintains a 1–3 week release cadence.
  • Embodied intelligence has become a differentiated battleground for RISC-V: from Xinji Infinite’s dedicated SoC + Chiplet to the summit’s robotics sub-forum and the 28.2% penetration forecast, RISC-V’s narrative in robotics compute has shifted from “usable” to “dedicated foundation + scenario data loop.”
  • Limitations: The main forum speakers and order are based on pre-summit published materials; the official website still marks 10-19 as “detailed agenda coming soon,” so the on-site schedule prevails; the Tenstorrent sale is a media report and has not been confirmed by the three parties; the AI-designed RISC-V SoC is a personal experiment and has not yet taped out, with data based on the author’s public description; changes found in the member website inspection are mostly marketing page refreshes, with no substantive product launches detected.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Google News aggregation (30+ Chinese and English queries, via proxy) Few valid items within the window: RISC-V Summit and market data, post-IPO analysis of ESWIN, Ruisilicon strategic investment, AI-designed SoC, AgiBot’s stake in Xinji Wuxian, etc. were captured; many “Milk-V”, “Andes”, and “Sophgo” queries returned noise such as milk, the Andes mountains, and stock quotes, which were removed by semantic filtering; on the English side, Tenstorrent was the only substantive industry story
GitHub organization check (72-hour window) Pushes within the window: espressif 39, sipeed 6, spacemit-com 5, openhwfoundation 3, sophgo 2, spacemit-robotics 2, openRuyi-Project 2, revyos 1; XUANTIE-RV, eswincomputing, Nuclei-Software, and radxa-linkr had no pushes within the window (most recent: 10-15, 10-14, 10-14, 10-15 respectively)
Key XiangShan repository check XiangShan (kunminghu-v3): 1 commit (ROB enlarged to 160); GEM5 (xs-dev): 1 commit (two-thread SpMT middle-end resource partitioning); NEMU: 2 commits (kmhv2 configs, CRC checking overhead); no new commits on difftest or XSCache main branches within the window
openRuyi dual-source Official news page still shows the 2026.09 version (no new release announcements); GitHub main repo: 6 Rust ecosystem SPECS commits (captured, see 1.2); homepage repo: 2 commits (new storage guide document, homepage link fix)
DAMO XuanTie (XUANTIE-RV) 0 pushes within the window (most recent 10-15); XuanTie-related information this issue appears only in the summit main forum agenda (Meng Jianyi’s talk) and is not listed as a separate item
ESWIN Computing and Nuclei (eswincomputing / Nuclei-Software) Neither organization had pushes within the window; ESWIN coverage is post-IPO market analysis (captured, see 3.2)
RISC-V International member website sweep (391 sites) Took 184 seconds: 231 unchanged, 92 with page content changes, 68 failed to fetch; changes were mainly university site and vendor marketing page refreshes (homepage carousel updates at Google, NVIDIA, Huawei, Infineon, etc.); no substantive RISC-V product, funding, or architecture announcements detected
RVSC2026 official site and source repo monitoring sitemap added 1 page (sponsor promotional piece for Chaorui Technology, 10-16); agenda page: tutorial titles adjusted on 10-18 and speaker tweaks on 10-20; source repo: 8 commits within the window (including Hong Kong Day agenda sync and multiple speaker replacements on 10-20) — merged into today’s highlights
riscv.org blog and openRuyi news page No new articles/release announcements within the window
Pending-inclusion queue No pending items this issue (no files for the day in the queue directory)