Research window: 2026-10-13 05:00 ~ 2026-10-14 05:00 (Beijing time, 24 hours; continuing from the cutoff of the previous daily issue).

Sources: Google News aggregation (40+ query sets in Chinese and English, via proxy), Hacker News, Phoronix, riscv.org blog, openRuyi official news page, RISC-V International member company website sweep (391 companies), and GitHub (pushes and commit searches across organizations and key repositories including XiangShan, NEMU, difftest, GEM5, XSCache, DAMO XuanTie XUANTIE-RV, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT, Sipeed, revyos, openRuyi-Project, Radxa Linkr, OpenHW, etc.).

Index

  • Today’s Highlights: Lanxin Computing completes nearly RMB 2 billion Series B funding round, RISC-V+AI server chip races toward mass production (10-12~10-13)
  • I. Open Source Community and Software Ecosystem
    • Asterinas 0.19.0: introduces initial X.Org/DRM support and adds AArch64 target (10-13)
    • openRuyi: firmware line releases “Ruyi Firmware 20261013”, full UEFI support for K3 Pico-ITX (10-13)
    • riscv.org blog: ISA Explorer student practice — ISA configuration builder and extension sandbox (10-13)
  • II. Product and Ecosystem Developments
    • Ubitium: $14 million seed funding, reconfigurable RISC-V “universal processor” targeting physical AI (10-13)
    • Industry events: 6th RISC-V China Summit scheduled for October 18-20 in Shenzhen (10-13)
  • III. Deep Dive on Domestic Teams
    • SpacemiT: llama.cpp fork releases v0.2.2, fixes Qwen3.5 output issues on K1 (10-13)
    • SpacemiT ecosystem: K3 fully domestic mini COM-E module launched; Agent software line establishes repositories in bulk (10-12~10-13)
    • XiangShan: store queue fix merged into main branch; simulation verification chain iterates intensively (10-13)
    • Espressif: security self-test library ESP-BIST releases v1.1.0, toolchain adds S31 support (10-13)
    • Sipeed: logic analyzer software SLogic releases v2.2.0 (10-13)
  • IV. Embodied Intelligence and Robotics Special Section
    • Yanxin Technology: integrating “symbols + behavior + connectivity” into RISC-V chips, building a plug-and-play robot brain (10-13)
    • Window observation: three threads on the embodied intelligence side (10-13)
  • V. Summary and Trend Observations

Today’s Highlight: Blue Core Computing Completes Nearly RMB 2 Billion Series B Financing, RISC-V + AI Server Chip Sprinting Toward Mass Production

Date: 2026-10-12 (Chinese media first report) / 2026-10-13 (English media follow-up)　Sources: [Phoenix Net · Investment World: Exclusive Blue Core Computing Completes Nearly RMB 2 Billion Series B Financing (10-12)](https://feng.ifeng.com/c/8x9l3WCyw5z), East Money (Cailian Press): Blue Core Computing Completes Nearly RMB 2 Billion Series B Financing (10-12), Sohu (Dahe Caicube): Blue Core Computing Completes Nearly RMB 2 Billion Series B Financing (10-12), DIGITIMES: China’s Blue Core Computing secures nearly US$300 million (10-13)

Shenzhen-based RISC-V chip company Blue Core Computing (Shenzhen) Technology Co., Ltd. has completed a Series B round totaling nearly RMB 2 billion (approximately US$299 million): existing shareholders including Shenzhen Capital Group, Huakong Fund, and Longqiu Capital continued to increase their investments, while state-owned capital, industrial capital, and leading venture firms such as Suguotou, Suchuangtou, GigaDevice, Tongchuang Weiye, CCB International, Yueke Financial, and Jiukun Venture joined the round. The funds will be used for mass production of RISC-V CPU chips, iteration of AI heterogeneous processors, and expansion of general-purpose computing solutions for telecom operators, financial institutions, and cloud service providers. Key points:

  • Product: The core product LX500 is the world’s first server CPU natively integrating RISC-V general-purpose computing and AI intelligent computing on a single chip—a 48-core heterogeneous design (32 performance cores + 16 efficiency cores), with an on-die 75 TOPS (INT8) AI engine, supporting RVV 1.0 vector extensions and the RVA23 standard, and natively compatible with PCIe 5.0 and CXL 2.0 memory expansion.
  • Deployment: Taped out and powered on in February 2026; in July, the Lenovo Wentian WR5219 G5 server equipped with the LX500 rolled off the production line at the Hefei Lianbao factory; it has been adapted to China Mobile’s BC-LINUX operating system and has completed inference validation for large models such as Kimi K2.6 and Qwen3.6-35B.
  • Team: Founder and CEO Lu Shan is the former head of server chip R&D at ByteDance (previously at Intel and Qualcomm), and CTO Jia Xinxia has 21 years of chip design experience.

At the intersection of Agentic AI computing demand and the RISC-V serverization narrative, this is one of the largest financings in China’s RISC-V sector in 2026, and it also marks the transition of domestic RISC-V server chips from “powering on” to “large-scale deployment.”

I. Open-Source Community and Software Ecosystem

1.1 Asterinas 0.19.0: Introduces Initial X.Org/DRM Support and Adds AArch64 Target

Date: 2026-10-13　Source: Phoronix: Asterinas 0.19.0 Brings Up X.Org & Other Improvements To This Rust-Written OS (10-13)

Asterinas, the memory-safe kernel written in Rust, has released 0.19.0: it introduces an initial DRM subsystem for the first time, bringing up the X.Org graphics stack on top of the modesetting driver and Mesa LLVMpipe, replacing the previous traditional framebuffer experience; it adds AArch64 architecture support, alongside the existing x86_64, RISC-V, and LoongArch64 targets; it also advances secure containers, a Rust-native device model, self-hosting, and AI code review modes. The project markets itself on Linux software compatibility and memory safety, and serves as a sample for observing the diversification of system software on the RISC-V platform.

1.2 openRuyi: Firmware Line Releases “Ruyi Firmware 20261013”, Full UEFI Support for K3 Pico-ITX

Date: 2026-10-13　Source: ruyifirmware Release 20261013 (10-13), edk2-ruyi commit log (10-13), openRuyi commit log (10-13)

The openRuyi project’s firmware line (ruyifirmware/edk2-ruyi) merged SpacemiT K3 Pico-ITX platform support in a concentrated window: GOP graphics output and EDID modes, PCI option ROM, RTL8127 wired NIC driver, boot selection and console hotkey policy, Fastboot update verification, and more; it also released “Ruyi Firmware 20261013”, offering two firmware variants—with and without x64 emulation (x64emu) (AMD Radeon RX 6400 has been verified under x64emu). The main repository concurrently updated SPECS for Go ecosystem packages (OpenTelemetry collector, etc.); kiwi-image added a GitHub Action build script for riscv64 images. The openRuyi official news page shows no new version release (the latest remains the 2026.09 version).

1.3 riscv.org Blog: ISA Explorer Mentee Practice—ISA Configuration Builder and Extension Sandbox

Date: 2026-10-13　Source: RISC-V International: My RISC-V Mentorship: The Problems Nobody Assigned Me (10-13)

riscv.org published a practice summary by LFX mentorship program mentee Rohit Sharma (JECRC University, India): in the RISC-V ISA Explorer project, beyond completing the established milestones, he independently designed and launched two tools—the ISA Configuration Builder (select core configurations on demand, automatically resolve dependencies, generate toolchain-usable configuration strings, and validate conflicts) and the Extension Sandbox (instantly check for conflicts with existing encodings when designing new instructions); the synchronization pipeline was rewritten into three-pass routing, enabling 1,867 instructions to be automatically categorized into 83 ISA subsets. The tools are used to reduce the error cost of custom core configuration and custom extensions, and serve as an example of community education and toolchain development.

II. Product and Ecosystem Updates

2.1 Ubitium: $14M Seed Round for a Reconfigurable RISC-V “Universal Processor” Targeting Physical AI

Date: 2026-10-13　Source: Ubitium press release: UBITIUM RAISES $14 MILLION TO BUILD THE FIRST UNIVERSAL PROCESSOR FOR PHYSICAL AI (10-13), EE Times: Ubitium Tapes Out First ‘Universal’ RISC-V Chip (background)

German semiconductor startup Ubitium (a RISC-V International member) based in Düsseldorf announced a $14 million new seed round: led by Ibex Investors, with participation from OpenOcean, KBC Focus Fund, Runa Capital, Inflection and others, bringing total funding to $18 million. The company advocates replacing the patchwork stack of “DSP + NPU + CPU” with a single reconfigurable RISC-V processing array — the array allocates resources at runtime across three workload classes: signal processing, AI inference, and real-time control. Its first chip, UB108 (256 processing units, Samsung 8nm), has taped out and validated all three workload classes on the same array; the first commercial chip, UB410 (4,096 processing units), is slated to ship evaluation units in 2027, with initial customers focused on “perception-layer” applications such as radar and audio.

2.2 Industry Events: 6th RISC-V China Summit Set for October 18-20 in Shenzhen

Date: 2026-10-13　Source: 21st Century Business Herald: RISC-V Bellwether: 2026 China Summit Fully Upgraded, Debating Ecosystem Maturity (10-13), RISC-V China Summit 2026 official site

21st Century Business Herald published a summit preview: the 6th RISC-V China Summit is scheduled for October 18-20 at the Shenzhen Convention and Exhibition Center (Futian), with an expected 3,000+ in-person professional attendees and more than 150 exhibitors and research institutions; Turing Award winner David Patterson, RISC-V International CEO Andrea Gallo and others will attend, with companies including DAMO XuanTie, ESWIN, SpacemiT, Lanxin Computing, and Tenstorrent making a concentrated appearance. The article frames 2026 as the watershed year for RISC-V “moving from technical validation to large-scale commercialization,” and cites the industry figure that “RISC-V already holds roughly 25% of the global processor market.”

III. Deep Dive on Domestic Teams

3.1 SpacemiT: llama.cpp fork releases v0.2.2, fixes Qwen3.5 output issue on K1

Date: 2026-10-13　Source: llama.cpp Release v0.2.2 (10-13), llama.cpp PR #44: Fix ggml-spacemit op kernels garbling Qwen3.5-2B output on K1 (10-13)

Continuing from the previous issue (introduction of the standalone ggml-spacemit backend and v0.2.1), the SpacemiT llama.cpp fork shipped v0.2.2 within the window: it merges the operator kernel fix for garbled Qwen3.5-2B output on K1 (#44) and fully documents how to enable the new backend — both the environment variable GGML_SPACEMIT_BACKEND and the argument –device SPACEMIT0 must be set for it to take effect (setting the environment variable alone does not work); multimodal models go through the –media-backend smt path, and benchmarking uses llama-bench –dev SPACEMIT0. The fork maintains a release cadence of roughly 1–3 weeks, with on-device inference usability continuing to converge.

3.2 SpacemiT Ecosystem: K3 fully domestic mini COM-E module launched; Agent software line sees concentrated repo creation

Date: 2026-10-12 / 2026-10-13　Source: CSDN: Zhongda Technology launches SMSM_K3_A SpacemiT K3 fully domestic mini COM-E module (10-12), GitHub: new repositories in the spacemit-com organization (10-13), model-zoo-vision commit history (10-13)

Two ecosystem developments: First, Zhongda Technology launched the SMSM_K3_A fully domestic mini COM-E (Type 10) module based on the SpacemiT K3 — 16-core homogeneous fusion architecture, 60 TOPS AI compute, 32GB LPDDR5 memory, 16MB NOR + 128GB UFS storage, with 100% domestically sourced components; it supports Bianbu / Buildroot / Kylin V10, is industrial-grade from -40 to 70°C, and has typical power consumption of 13W; on the AI side it offers llama.cpp (GGUF/GGML, capable of running Qwen3-30B and others) plus YOLO, VLM, and ASR/TTS support, targeting scenarios such as AI edge gateways, industrial servers, and embodied robots. Second, on GitHub, SpacemiT created a batch of new repositories in a concentrated push on the evening of 10-13 (bibit series, bianbu-agent series, agent-power-manager, bianbu-agenic, bianbu-skill, etc., all currently empty), pointing to a layout in the direction of on-device AI Agent system software; on the software side, model-zoo-vision added the CosPlace visual place recognition model, mpp merged multiple vdec/venc/RTSP fixes, and docs-buildroot updated the K1/K3 screen adaptation documentation.

3.3 XiangShan: store queue fix merged into main branch; simulation verification chain iterates intensively

Date: 2026-10-13　Source: XiangShan PR #6693: fix forward older store data (10-13), NEMU commit history (10-13), difftest commit history (10-13), GEM5 commit history (10-13)

The XiangShan mainline (kunminghu-v3) merged the store queue forwarding fix for older store data (#6693); verification and simulation infrastructure advanced on multiple fronts: difftest added an MCSim timing backend (alongside DRAMSim3), delta encoding for mcsr/mcfg, an FPGA-oriented CRC-64 store queue hash check, and PLDM flow fixes; NEMU accelerated AME matrix hash computation, introduced CRC-64 store queue hash checking and a fix for duplicate store log recovery; GEM5 added Zimop instruction support (including RV64 regression) and TRACERTL/NEMU trace format support. The Kunminghu platform’s progress on correctness verification infrastructure was notably significant this window.

3.4 Espressif: safety self-test library ESP-BIST releases v1.1.0, toolchain adds S31 support

Date: 2026-10-13　Source: esp-bist Release v1.1.0 (10-13), esptool commit history (10-13), esp-video-components commit history (10-13)

Espressif’s built-in self-test (BIST) library esp-bist released v1.1.0 — the library performs integrity self-tests on hardware including CPU registers, CSRs, interrupt handling, volatile/non-volatile storage, stacks, and clock sources, targeting safety-critical scenarios such as IEC 60730 Class B, with a supported list covering ESP32-C3/C5/C6/C61 and H2/H4/P4 (all RISC-V cores); esptool merged the ADC weight eFuse fields for ESP32-S31 and ESP32-H2 chip variant identification; esp-video-components fixed the OV5647 sensor’s non-continuous clock mode. The Espressif organization pushed to 46 repositories within the window, with intensive maintenance cadence on the device side (including the RISC-V chip line).

3.5 Sipeed: logic analyzer software SLogic releases v2.2.0

Date: 2026-10-13　Source: SLogic Release release-2.2.0 (10-13), SLogic commit history (10-13), sipeed_wiki commit history (10-13)

Sipeed’s logic analyzer software SLogic released v2.2.0 following v2.1.0: it focuses on the capture length issue on arm64 (macOS) and on ngscopeclient deep-memory reshaping no longer hanging; it also fixes the uninitialized sampling depth variable for ALL-LOGIC on arm64; sipeed_wiki updated the NanoKVM multi-screen mirroring documentation, fixed documentation links, and switched the site-top banner to the SLogic32U3 Kickstarter crowdfunding entry point.

IV. Special Chapter on Embodied Intelligence and Robotics

4.1 Yanxin Technology: embedding “symbols + behavior + connection” into RISC-V chips to build a plug-and-play robot brain

Date: 2026-10-13　Source: 36Kr: Large models can write poetry but cannot walk out of the factory fence — Yanxin Technology fuses the three routes of “symbols + behavior + connection” into a RISC-V chip (10-13, Google News link), English version (same article on 36Kr Europe)

36Kr reported on Beijing startup Yanxin Technology (founded January 2025): addressing the scenario-generalization pain point that large models “cannot walk out of the factory fence,” it fuses the three technical routes of symbolism, behaviorism, and connectionism into a single “general-purpose embodied intelligence brain” system, pre-packaged and hardened into a RISC-V chip, offering robot manufacturers a plug-and-play “industry embodied intelligence brain,” and advocating support for continuous learning after factory shipment, human-robot interaction teaching, and pure on-device deployment. Note that the company is still in an early validation stage — public information shows registered capital of 1 million yuan and it is still in the financing roadshow period, and the report also notes that specific technical implementation details, performance metrics, and mass-production progress are all undisclosed. It can be seen as yet another example of the RISC-V × embodied intelligence crossover track continuing to attract early-stage startups.

4.2 Window observation: three threads on the embodied intelligence side

This window presents a profile of “warming at both ends, combined delivery” on the embodied intelligence and robotics side: First, a new international player enters with a differentiated architecture — Ubitium unifies perception, inference, and real-time control with a reconfigurable RISC-V array, securing $14 million in seed funding (see 2.1); second, an early-stage domestic startup is betting the “robot brain” on RISC-V chip-level packaging (Yanxin Technology, see 4.1); third, on the established vendor side, SpacemiT K3 continues to deliver a complete “chip—module—software stack” chain to robotics and edge scenarios (K3 COM-E module and the llama.cpp/model library software line, see 3.2), while its robotics-dedicated organization spacemit-robotics had no new pushes within the window. Together, the three threads point to this: competition in RISC-V for embodied intelligence is shifting from “single-point chips” to combined delivery of “chip + brain software + scenario packaging.”

V. Summary and Trend Observations

  • Capital and products resonating on two fronts: Lanxin Computing’s nearly 2 billion yuan Series B and Ubitium’s $14 million seed round landed in the same period, making RISC-V chips in the high-performance/physical AI direction a track where global capital is concentrating its bets; domestic RISC-V server chips have entered the “mass-production validation” stage (LX500 + Lenovo complete-machine mass production + carrier operating system adaptation).
  • Industry calendar approaching: The 6th RISC-V China Summit will be held in Shenzhen on October 18-20, with DAMO XuanTie, ESWIN, Lanxin, SpacemiT, and others appearing in force; combined with Ubuntu 26.10 (released October 15) offering an official RISC-V desktop image for the first time, next week is an observation window.
  • High-density output on the domestic engineering side: SpacemiT’s llama.cpp v0.2.2 and concentrated repo creation for the Agent software line, plus the launch of the K3 fully domestic COM-E module; XiangShan’s verification chain (MCSim timing backend, delta encoding, CRC-64 store check) advancing systematically; Espressif’s safety self-test library v1.1.0 covering its entire RISC-V SoC product line.
  • Open-source system software flowing quietly but deeply: Asterinas 0.19 (initial DRM/X.Org support, AArch64 target) and the openRuyi firmware line (K3 Pico-ITX support release) show RISC-V platform software continuing to strengthen at both the desktop and firmware ends.
  • Limitations note: Information on Yanxin Technology comes from a single media report and the company is still at an early stage; Lanxin’s funding scale is based on Chinese media and DIGITIMES figures (nearly 2 billion yuan / approximately $299 million); this issue’s member website inspection had 67 failed crawls (mostly domestic sites), so developments at the relevant sites may be missing.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Google News aggregation (40+ query sets in Chinese and English, via proxy) Included within window: Ubitium funding, Blue Core Computing funding, Yanxin Technology, summit preview, Asterinas, etc.; Excluded: ESP32-S31 media echo (old news, already reported in detail on 09-05/09-25), Guoxin Technology investor interaction (low substance), Kapta Space / Power Integrations / Jon Peddie report (not RISC-V related); queries for vendors such as SiFive / StarFive / Andes / Milk-V yielded no new reports within the window; ESWIN Computing post-IPO commentary is continuity content
GitHub organization check (24-hour window) Pushes within window: espressif 46, spacemit-com 22, openRuyi-Project 13, sipeed 5, openhwfoundation 3, Nuclei-Software 3 (development branch sync, no new mainline commits detected); XUANTIE-RV, eswincomputing, sophgo, spacemit-robotics, revyos, radxa-linkr all 0 (most recent pushes all on 10-12 or earlier)
Key XiangShan repository check XiangShan main branch merged #6693 (StoreQueue fix); NEMU / difftest / GEM5 multiple merges (CRC-64 storage verification, MCSim timing backend, delta encoding, Zimop); XSCache no new main branch commits within window
Organizations of interest such as DAMO XuanTie XUANTIE-RV 0 pushes within window (most recent on 10-12); ESWIN Computing organization 0
openRuyi dual-source Official news page latest still the 2026.09 version (no new release); 13 repository pushes within window on GitHub (ruyifirmware release 20261013, edk2-ruyi K3 Pico-ITX support, etc., already included)
RISC-V International member official site sweep (391 sites) 102 sites showed content changes (mostly routine/marketing updates by universities and vendors; among them the Ubitium official site update corresponds to this issue’s funding news); 67 sites failed to fetch (mostly domestic sites, non-blocking)
riscv.org blog and LWN One new post on the riscv.org blog (ISA Explorer student practice, already included); no RISC-V feature items on LWN within window
Pending queue (WeChat official accounts) No queue files this issue