Research window: 2026-10-10 09:20 ~ 2026-10-12 05:00 (Beijing time, approx. 44 hours; this issue is the Monday morning briefing, with the window starting from the cutoff of the previous daily (10-10 National Day makeup report), covering Saturday morning through early Monday, including all of Sunday).

Sources: Google News aggregation (30+ query sets in Chinese and English, via proxy), Phoronix, CNX Software, Hacker News, Wccftech, 36Kr, WeChat official accounts, LPC26 conference system (talk pages and materials), openRuyi official news page, riscv.org blog, RISC-V International member company website sweep (391 companies), and GitHub (XiangShan/NEMU/difftest/GEM5, DAMO XuanTie XUANTIE-RV, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT (including robotics org), Sipeed, revyos, openRuyi-Project, Radxa Linkr and other orgs and key repos, push and commit searches, including pending-inclusion queue entries).

Issue Index

  • Today’s Highlights: LPC26 Recap — RVA23u64 kernel profile bits advance, 8 patches merged into riscv/for-next (10-11)
  • I. Open Source Community and Software Ecosystem
    • Phoronix/LPC26: Kernel auto-vectorization yields positive results, LZ4 up to ~15% improvement (10-11)
    • RevyOS: Kernel synced to 6.17.11 config, enabling Rust/PowerVR/NTSYNC and other features (10-11)
    • openRuyi: SPECS updated with Go 1.27.2 and OpenSSL 3.6.5, docker-cli packaged independently (10-10)
  • II. Product and Ecosystem Updates
    • M5Stack ToughC5: Waterproof ESP32-C5 industrial IoT controller released (10-10)
    • Wireless-Tag WT32P4C5-43S: ESP32-P4 + C5 dual-chip 4.3-inch touchscreen dev board (10-11)
    • Industry Watch: Qualcomm v. Arm trial sees clash over RISC-V data center maturity (10-11)
    • Industry Analysis: x86/Arm/RISC-V “meet head-on” at the industrial edge (10-10)
  • III. Deep Dives on Domestic Teams
    • XiangShan: Compressed ROB (crob) architectural feature merged, MMU and execution unit fixes (10-10/11)
    • XiangShan simulation chain: difftest adds parallel memory hash verification, NEMU/GEM5 feature branches advance (10-10/11)
    • Espressif: esp-vision adds nano track tracking and IPA statistics, esp-sr updates precompiled libraries (10-10/11)
    • Sophgo: zsbl releases v3.2.1, LLM-TPU adapts bge-reranker-v2-m3 and MinerU2.5-Pro (10-10)
    • Sipeed: SLogic releases v2.1.0, fixes Windows RAW_IO throughput and adds regression self-test (10-10)
    • SpacemiT: spine-triton-tutorial completes smt_rvisa terminology unification (10-10)
  • IV. Embodied Intelligence and Robotics Special Section
    • SpacemiT Robotics: IMU library adds BMI270 kernel IIO reading, motor library completes M8010-A native UART (10-11)
  • V. Summary and Trend Observations

Today’s Highlight: LPC26 Returns — RVA23u64 Kernel Profile Bits Advance, 8 Patches Merged into riscv/for-next

Date: 2026-10-11　Source: WeChat Official Account “Docular嘚吧嘚”: LPC26 Trip Report (10-11), LPC26 Presentation Slides, Author’s Homepage: Docular

Xu Guodong (Docular, currently at Qualcomm), the primary driver of the RVA23 kernel effort, published his trip report from Linux Plumbers Conference 2026 (LPC26, Prague): his Linux kernel rva23u64 profile bits series is advancing to v9 (in flight), and on October 9, the first 8 of the 11 patches in v8 were merged into riscv/for-next by RISC-V kernel maintainer Paul Walmsley (awaiting the next merge window for mainline), with the remaining 3 core patches to be submitted with v9 after incorporating feedback from LPC.

  • Problem being solved: RVA23 profile 1.0 (ratified 2024-10, 39 mandatory + 15 optional extensions) requires the kernel and userspace to answer “is this hardware RVA23?” at low cost — currently only bit-by-bit queries are possible, glibc and GCC each compute their own answer, and Ubuntu-side detection tools can only report “probably RVA23.” The proposed solution: the kernel computes an “RVA23 compliant” bit at boot and places it in the vDSO, so userspace can read it in one shot via the hwprobe UAPI.
  • Conclusions on the four Asks at LPC26: ① The v8 bit format was accepted by maintainers; v9 will add RVA22 / RVA20 tiered bits (to facilitate glibc’s stepwise fallback) and document the legacy behavior of not inheriting IMA bits; ② glibc will switch to profile-based builds + glibc-hwcaps automatic library selection (hwcaps sourced from kernel bits; ifunc reserved for microarchitecture-level selection), with GCC maintainer Jeff Law advancing in the same direction at the GNU Tools Cauldron RISC-V BoF; ③ The userspace interface for dynamically disabling the V extension will be deprecated — the very next day at LPC, Samuel Holland (SiFive) sent out a 3-patch series (cover letter: RISE and LPC26 have reached consensus, create more trouble than benefits); ④ Future extensions with register state (e.g., matrix) will not introduce similar switches.
  • Spillover effects: This series directly or indirectly drove no fewer than 5 mainline series — two old patch sets shelved for two years (extension name case unification, Zicclsm) were absorbed, ByteDance’s Qingwei Hu contributed Zic64b support, and additionally a “do not report disabled extensions” (6-patch series), cpufeature BUNDLE-to-SUPERSET streamlining, and the V-off deprecation series were sent out around the same time.
  • Note: This year’s LPC RISC-V MC featured 10 talks total, with Qualcomm contributing 3; the slides for this talk are now public (see reference links).

I. Open-Source Community and Software Ecosystem

1.1 Phoronix/LPC26: Kernel auto-vectorization yields positive results, LZ4 up to ~15% improvement

Date: 2026-10-11　Source: Phoronix: Auto Vectorizing The RISC-V Linux Kernel Shows Promising Results (10-11), LPC26 talk page: Optimizing the kernel with vector, Hacker News discussion

RISC-V kernel builds do not yet enable the V (vector) extension. Andy Chiu presented “Optimizing the kernel with vector” at LPC26 (October 5-7, Prague), describing an approach to optimize the kernel via compiler auto-vectorization: experiments targeting kernel scenarios such as crypto, RAID, XOR, and user copy show — LZ4 up to ~15% improvement, Btrfs ~8.4%, XFS ~5%, Nginx scenario ~2%; the cost is increased time and memory overhead from vector context management, and existing constraints on using vector units in kernel mode remain. Phoronix called the direction “promising results,” and the talk materials have been made public with the conference.

1.2 RevyOS: Kernel synced to 6.17.11 config, enabling Rust/PowerVR/NTSYNC and other features

Date: 2026-10-11　Source: revyos/linux commit log (10-11)

RevyOS (a multi-platform RISC-V Debian distribution) kernel repository saw 50 commits during the window: kernel configs were batch-synced to the 6.17.11 baseline, adding configs for platforms including K1/K3, DP1000, SG2042/SG2044, and TH1520, and enabling Rust, PowerVR DRM, NTSYNC, the K3 display controller and UFS, SPACEMIT PM domains, and the FUSB301 Type-C controller; device trees enable GPU and USB3 ports for the K3 Pico ITX and USB for the Milk-V Meles; CI adds cross/native builds. Display, USB, storage, and GPU support for platforms such as K3 is being densely filled in on the distribution kernel side.

1.3 openRuyi: SPECS updated with Go 1.27.2 and OpenSSL 3.6.5, docker-cli packaged separately

Date: 2026-10-10　Source: openRuyi commit log (10-10), lookout commit log (10-11), openRuyi official news page (checked 10-12)

The openRuyi repository saw 5 SPECS updates during the window: Go upgraded to 1.27.2, OpenSSL upgraded to 3.6.5, and a new standalone docker-cli package added (moby’s Provides migrated to docker-cli); the PR template links were fixed. The organization’s version inspection tool lookout saw 10 commits during the window, advancing capabilities such as automatic discovery of Go components from trusted-source tags, precise Go version tracking, and NVD security identity verification. Official news page check: the latest release remains version 2026.09, with no new version announcement.

II. Product and Ecosystem Updates

2.1 M5Stack ToughC5: Waterproof ESP32-C5 Industrial IoT Controller Launched

Date: 2026-10-10　Source: CNX Software: M5Stack ToughC5 weatherproof ESP32-C5 IoT controller (10-10)

M5Stack has launched the waterproof industrial IoT controller ToughC5 (an upgraded version of the 2021 M5Stack TOUGH): based on the ESP32-C5 (single-core RISC-V @240MHz + low-power RISC-V core), dual-band Wi-Fi 6, BLE 5, 802.15.4 (Zigbee 3.0/Thread 1.3), 8MB Octal PSRAM, 16MB flash, 2.0-inch 320×240 touchscreen (up to 853 nits), RS485 and 4x HY2.0-4P expansion, RX8130CE RTC (independent coin cell), 6-24V power supply; the waterproof enclosure has a built-in USB-C and 4-pin expansion port, with M12 cable routing. Targeting industrial field control, outdoor edge acquisition, and smart buildings, priced at $49.9.

2.2 Wireless-Tag WT32P4C5-43S: ESP32-P4 + C5 Dual-Chip 4.3-Inch Touchscreen Dev Board

Date: 2026-10-11　Source: CNX Software: Wireless-Tag WT32P4C5-43S (10-11)

Wireless-Tag WT32P4C5-43S touchscreen dev board: ESP32-P4 (dual-core RISC-V @400MHz + low-power core, 16/32MB PSRAM) paired with an ESP32-C5 wireless module, integrating a 4.3-inch 800×480 capacitive touchscreen (18-bit RGB interface), 15-pin MIPI CSI camera interface, microSD, dual USB-C (including debug/JTAG), 14-pin GPIO expansion. Targeting industrial automation, smart control panels, and edge AI vision terminals, starting at $32; the official offering includes two firmware repositories for the ESP32-P4 main firmware and the C5 coprocessor, plus schematics and STEP models, supporting ESP-IDF/Arduino/LVGL.

2.3 Industry Watch: Qualcomm v. Arm Trial Sees Sparring Over RISC-V Data Center Maturity

Date: 2026-10-11　Source: Wccftech: Even Court Judges Are Now Declaring That RISC-V Is Basically Worthless (10-11)

In the Qualcomm v. Arm licensing dispute trial (U.S. federal court in Delaware), RISC-V unexpectedly became a courtroom topic: Arm expert witness Timothy Simcoe described RISC-V and x86 as constituting “long-term competitive pressure”; presiding judge Noreika pressed on RISC-V’s current availability, and the witness acknowledged that its enterprise data center deployments remain at an early stage, with related designs mainly coming from Chinese companies (such as Alibaba’s XuanTie), after which the judge did not probe further. The report circulated with a sensationalist headline, sparking community discussion; the focus of the discussion was the enterprise data center scenario, which does not directly contradict RISC-V’s existing progress in embedded and edge deployments.

2.4 Industry Analysis: x86/Arm/RISC-V “Meet Head-On” at the Industrial Edge

Date: 2026-10-10　Source: 36Kr: “x86, Arm, RISC-V Meet Head-On at the Industrial Edge” (10-10)

The edge AI explosion has brought the three architectures into head-on competition in industrial scenarios: Semiconductor Industry Panorama (published with authorization from 36Kr) lays out — x86 relies on ecosystem (Intel Open Edge Platform, AMD Ryzen AI Embedded X100 up to 80 TOPS, already deployed in inspection robots); Arm relies on energy efficiency and heterogeneity (Rockchip RK3572 integrates a RISC-V core, RK182X coprocessor embeds multiple RISC-V cores, already adopted in hundreds of customer projects); RISC-V relies on openness and customizability (XuanTie C950, Nuclei NA900 pass ASIL-D, ESWIN R500A passes ASIL-B certification). The article judges that by 2030, RISC-V’s share of industrial edge chip shipments may rise from under 7% to over 24%, with the key to competition lying in toolchains, RTOS, and certification systems; it also previews a forum at the Shanghai Industrial Fair Guoxin Exhibition starting 10-12 titled “Can RISC-V Crack the Hard Nut of the Industrial Edge.”

III. Deep Dive into Domestic Teams

3.1 XiangShan: Compressed ROB (crob) Architectural Feature Merged, MMU and Execution Unit Patches

Date: 2026-10-10/11　Source: XiangShan commit log (10-10/11), PR #6695: MMU ignores PTE G bit, PR #6689: Narrow shift bias

Ten merges landed in the main XiangShan repo during the window: the compressed ROB (crob) architectural feature landed—implementing the compressed ROB and integrating CSR state tracking, with supporting refactors of the compressed state and deadline paths, carrying event locations for ArchEvent, maintaining ordered store checks via entry offsets, and fixing scommit bit width while expanding entry count; additionally fixed the MMU (ignoring PTE G bit when V=0, #6695), execution unit narrow shift bias selection by output format (#6689), and CI performance reporting (#6702, #6705).

3.2 XiangShan Simulation Chain: difftest Adds Parallel Store Hash Verification, NEMU/GEM5 Feature Branches Advance

Date: 2026-10-10/11　Source: difftest store-hash branch commits (10-10), NEMU branch commits (10-11), GEM5 branch commits (10-10)

Multiple repos in the simulation chain were active during the window (primarily on feature branches): difftest added lane-parallel CRC-64 store hash verification (store-hash branch) and portable builds for PLDM; NEMU branches explored a new checkpoint mode (CHECKPOINT_HERE) and new vector floating-point reduction logic; GEM5 advanced golden memory write-order preservation, SMT LR replay, and PerfCCT diagnostic tracing. On the main branch side, only one commit landed for the Chinese repository reporting tool.

3.3 Espressif: esp-vision Adds nano track Tracking and IPA Statistics, esp-sr Updates Prebuilt Libraries

Date: 2026-10-10/11　Source: esp-vision commit log (10-11), esp-sr commit log (10-10), esp-idf commit log (10-10)

Espressif continued maintenance across multiple repos: esp-vision added nano track object tracking support and a sensor IPA statistics interface (10-11); esp-sr updated prebuilt libraries (10-10); esp-idf merged BLE command IRAM footprint reduction, an ESP32 TWAI random receive data misalignment errata fix, PSRAM rate DFS, and H4 ECO2 crystal dependency fixes (10-10). Twenty-five repos were pushed within the Espressif organization during the window, reflecting a dense maintenance cadence on the edge side (including the RISC-V chip line).

3.4 Sophgo: zsbl Releases v3.2.1, LLM-TPU Adapts bge-reranker-v2-m3 and MinerU2.5-Pro

Date: 2026-10-10　Source: zsbl commit log: v3.2.1 (10-10), LLM-TPU PR #179 (10-10), tpu-mlir commit log (10-10)

Sophgo maintained multiple repos: zero-stage bootloader zsbl released v3.2.1 (including console entry adjustment after SG2042 loading); LLM-TPU merged PR #179, adding compatibility adaptation for the bge-reranker-v2-m3 reranker and the MinerU2.5-Pro document parsing model; tpu-mlir fixed documentation build OOM and cleaned up the qwen_asr package; libsophon, sophon_media, edk2-non-osi, and others were pushed in sync (libsophon side was branch-level pushes, with no commits on the main branch during the window).

3.5 Sipeed: SLogic Releases v2.1.0, Fixes Windows RAW_IO Throughput and Adds Regression Self-Test

Date: 2026-10-10　Source: SLogic commit log: v2.1.0 (10-10)

Sipeed’s logic analyzer software SLogic released v2.1.0: fixed the RAW_IO throughput issue on Windows, added SLogic32U3 regression self-test, completed the CHANGELOG, and corrected the combo box dropdown width in slogicview under macOS dark theme; the previously added sigrok-cli forwarding plugin was included alongside.

3.6 SpacemiT: spine-triton-tutorial Completes smt_rvisa Terminology Unification

Date: 2026-10-10　Source: spine-triton-tutorial commit log (10-10)

SpacemiT’s spine-triton-tutorial fully renamed spine_raw to smt_rvisa throughout the documentation and completed a full-text edit, aligning tutorial naming with the main repository.

IV. Embodied Intelligence and Robotics Special Chapter

4.1 SpacemiT Robotics: IMU Library Adds BMI270 Kernel IIO Reading, Motor Library Refines M8010-A Native UART

Date: 2026-10-11　Source: peripherals-imu feat/bmi270-iio branch (10-11), peripherals-motor feat/m8010a-native-uart branch (10-11)

Two feature branches in the spacemit-robotics peripheral libraries advanced during the window: peripherals-imu added BMI270 IMU kernel IIO reading support (previously had BMI270 SPI event-driven and IWT603 UART drivers); peripherals-motor tightened native UART transaction boundaries for the M8010-A motor (previously added M8010-A RS485 shared library driver). The robotics peripheral stack continues converging toward kernel-space and event-driven approaches.

V. Summary and Trend Observations

  • Two kernel low-level tracks advance in parallel: After LPC26, 8 RVA23u64 profile bits have entered riscv/for-next (glibc will build and distribute by profile, and the userspace interface for dynamically disabling the V extension will be deprecated); kernel auto-vectorization experiments show roughly 15% gains on LZ4, and the long-standing taboo of “using vectors in kernel space” is being re-evaluated.
  • Distribution configuration upgrades: RevyOS kernel synced to 6.17.11 and enabled Rust, PowerVR, NTSYNC, and other features for K3/TH1520/SG2042 and other platforms; openRuyi updated Go/OpenSSL and split docker-cli, with enhanced lookout inspection capabilities.
  • Edge competition narrative takes shape: A 36Kr long-form article and Qualcomm v. Arm courtroom discussion point to the same judgment—RISC-V already has “qualifying status” in embedded/edge, while data centers still need time; the 26th China International Industry Fair Guoxin Exhibition begins today (10-12) in Shanghai.
  • Edge-side and domestic team deployments: Espressif (esp-vision tracking and IPA statistics), Sophgo (zsbl v3.2.1, LLM-TPU model adaptation), Sipeed (SLogic v2.1.0), and SpacemiT (robotics peripheral libraries, documentation terminology unification) all had substantive commits.
  • To watch: Real-world feedback on the Ubuntu 26.10 (released 10-15) RISC-V desktop image; the direction of the RVA23 series v9 submissions and kernel vectorization discussions; follow-up performance validation of XiangShan’s compressed ROB.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Google News aggregation (30+ query sets in Chinese and English, via proxy) Hits within the window and included: LPC26 kernel vectorization, the industrial edge long-form piece, courtroom trial coverage; Milk-V queries were mostly homonym noise, and follow-up coverage of ESWIN’s listing was all continuation of yesterday’s content with no substantive additions; English queries for vendors such as SiFive / Andes / StarFive / SOPHGO yielded no new coverage within the window
GitHub organization check (48-hour window) Pushes within the window: espressif 25, sophgo 7, Nuclei-Software 3 (no content commits detected within the window on the respective development branches, inferred to be branch/tag maintenance), sipeed 3, spacemit-com 2, spacemit-robotics 2, openRuyi-Project 2, revyos 1; XUANTIE-RV, eswincomputing, openhwgroup, radxa-linkr all 0
Key XiangShan repository check XiangShan main branch had 10 merges (crob, etc., already included); difftest / NEMU / GEM5 main branches had no new commits within the window, with new content concentrated on feature branches (summary already included)
Organizations of interest such as DAMO XuanTie XUANTIE-RV had 0 pushes within the window (most recent was 10-07); ESWIN Computing organization had 0 within the window
openRuyi dual-source Official news page latest is still the 2026.09 edition; GitHub repository had 5 SPECS commits + 10 lookout commits (already included)
RISC-V International Foundation member website sweep (391 sites) 49 sites showed content changes, all routine university/institutional and marketing updates, with no substantive RISC-V developments included; 65 sites failed to scrape (mostly domestic sites, non-blocking)
riscv.org blog and news No new posts within the window (latest was 10-07)
Pending queue (WeChat Official Accounts) Queue item R1 (LPC26 RVA23 kernel profile bits) has been included in today’s highlights