Research window: Past 24 hours (2026-09-29 05:00 ~ 2026-09-30 05:00, Beijing time).

Sources: Google News aggregation (multiple Chinese and English query sets, via proxy), digitimes, Notebookcheck, Jumpstart Magazine, ifeng, Electronics For You, Business Wire, openRuyi official news page, RISC-V International Foundation blog and member company website sweep (391 companies), plus GitHub (XiangShan/NEMU/GEM5/difftest, DAMO XuanTie XUANTIE-RV, Sophgo, Espressif, SpacemiT, Sipeed, revyos, openRuyi-Project, Radxa Linkr and other organizations and key repositories for push and commit searches; including ecosystem project tracking for rv32emu, felix86, etc.).

Index

  • Today’s Highlights: RevyOS adds kernel support for Zhihe Computing A210 (Melon Pi), batch of patches in place (09-29)
  • I. Open Source Community & Software Ecosystem
    • XiangShan: Four backend fix PRs opened, feature branches advancing intensively (09-29)
    • XiangShan simulation chain: difftest lays down CROB comparison line, NEMU submits CSR shadow fix (09-29)
    • rv32emu: Buildroot ext4 root filesystem generation pipeline merged (09-29)
    • openRuyi dual-source: linux-lts bumped to 6.18.54, K3 firmware released 20260929 (09-29)
    • Ecosystem shorts: Lua/OCaml bare-metal verification practice on Sail RISC-V model (09-29)
  • II. Product & Ecosystem Developments
    • GF’s MIPS: Completes ARC integration anchoring RISC-V Physical AI, partners with Xcelsa to accelerate custom silicon (09-29)
    • Nuvacore: Unveils “Core First” development model, ISA choice remains open (09-29)
    • SignOff: Demonstrates full custom chip flow capability with RISC-V “Kaveri” soft IP (09-29)
  • III. Deep Dive on Domestic Teams
    • ESWIN: IPO follow-up coverage focuses on Wang Dongsheng, financial and business fundamentals analyzed in depth (09-29)
    • SpacemiT: K3 native Triton tutorial repository receives concentrated commits (09-29)
    • Espressif: esp-sr adds multilingual wake word models, multi-repo maintenance advances (09-29)
    • Sipeed: SLogic releases 2.0.0, slogic16u3-tools ships two versions in succession (09-29)
    • Sophgo: sophon-demo refines Qwen3.5 examples and Web UI (09-29)
  • IV. Embodied Intelligence & Robotics Special Section
    • SpacemiT Robotics: ros2_humanoid adds ASR action voice prompts (09-29)
  • V. Summary & Trend Observations

Today’s Highlights: RevyOS adds kernel support for Zhihe Computing A210 (Melon Pi), batch of patches in place

Date: 2026-09-29　Source: revyos/linux commit: MAINTAINERS adds Zhihe A210 support (09-29), commit: A210 thermal and watchdog device tree (09-29), commit: PWM reuses TH1520 driver to support A210 (09-29), commit: Melon Pi V2 audio routing (09-29)

On the morning of September 29, the RevyOS kernel repository (revyos/linux) pushed a batch of patches to the rv/a210-upstream-local branch (14 commits visible in the window), completing kernel support for the Zhihe Computing “Archimedes” A210 SoC and its Melon Pi V2 development board. The A210 is an eight-core RISC-V “unified training-inference” chip (12 TOPS@INT8) equipped with DAMO XuanTie C920 and C908 cores, targeting edge servers and embodied intelligence scenarios. This batch of patches covers: MAINTAINERS and defconfig entries; device tree (thermal and watchdog, PWM, ADC, Melon Pi V2 audio routing); driver-side changes including PWM reusing the TH1520 driver, IIO ADC single conversion, ASoC’s A210 I2S controller and Everest ES8156 stereo codec; plus one [NOT-FOR-UPSTREAM] deb-pkg DTB installation adjustment. Most are submitted in normalized form as dt-bindings, drivers, and device trees, continuing RevyOS’s rapid follow-up pace on new hardware.

I. Open-Source Community and Software Ecosystem

1.1 XiangShan: Four Backend Fix PRs Opened, Feature Branches Advance Densely

Date: 2026-09-29　Source: XiangShan PR #6649: Preserve FEX0 output slot for x0 conversion (09-29), XiangShan PR #6652: Prevent vector std from issuing outside the store queue physical window (09-29), XiangShan PR #6653: Fix inverted condition for out-of-bounds issue in StdExeUnit (09-29)

Within the window, the XiangShan main repository’s default branch (kunminghu-v3) saw no new merges, with development concentrated on feature branches: my-crob-difftest, victim-btb, frontend-bt, fix-flt, timing-fense, test-mbtb, tmp-xfb-20260929 and others all received pushes, and a new feat-mmu-h-tlb-compression branch was created. On the PR side, four backend fixes were opened the same day: #6649 (preserve FEX0 output slot for x0 conversion), #6651 (clean up unused F2vCfg configuration in FEX0), #6652 (prevent vector std from issuing outside the store queue physical window), #6653 (fix inverted condition for out-of-bounds issue in StdExeUnit)—all concentrated on the issue and ordering paths of the frontend and backend.

1.2 XiangShan Simulation Chain: difftest Lays Out CROB Comparison Line, NEMU Proposes CSR Shadow Fix

Date: 2026-09-29　Source: difftest branch: my-crob-difftest pushed (09-29), NEMU PR #1237: Invalidate CSR shadow copy on implicit state updates (09-29), GEM5 branch: apf-align pushed (09-29)

difftest, NEMU, and GEM5 all advanced at the branch level: difftest pushed two branches, my-crob-difftest and tmp-xfb-20260929 (echoing the same-named branches in the main repository, with the CROB comparison chain being laid out); NEMU opened PR #1237 (invalidate CSR shadow copy on implicit state updates) and created a new fix-csr-shadow branch; GEM5 pushed the apf-align branch, updated the lldp branch in sync, and also had a dependabot Actions version upgrade PR.

1.3 rv32emu: Buildroot ext4 Root Filesystem Generation Pipeline Merged

Date: 2026-09-29　Source: rv32emu merged #787: Generate ext4 root filesystem (09-29), rv32emu commit: Buildroot supports ext4 and ext4.gz output (09-29), rv32emu commit: Save ext4 root filesystem when building Linux image (09-29)

The Linux boot chain of the teaching-oriented RV32 emulator rv32emu continues to improve: within the window, PR #787 (ChinYikMing) was merged—Buildroot adds ext4 and ext4.gz root filesystem output, saves this rootfs when building the Linux image, and adds assertion checks to the image generation flow. Following the system emulation JIT batch covered in the previous issue, the “run Linux” image engineering chain has been further consolidated.

1.4 openRuyi Dual-Source Verification: linux-lts Upgraded to 6.18.54, K3 Firmware Released 20260929

Date: 2026-09-29　Source: openRuyi commit: linux-lts upgraded to 6.18.54 and patch set refreshed (09-29), openRuyi commit: rpm adds gnupg dependency (09-29), k3firmware release: Boot Firmware for SpacemiT K3 20260929 (09-29), openRuyi official website news page (09-29 verification)

  • Official website news page: The 2026.09 release has still not been published (most recent is 2026.08).
  • GitHub main repository: 2 SPECS commits within the window—the linux-lts kernel package was upgraded to 6.18.54 with the patch set refreshed, and the rpm package completed its gnupg dependency (in coordination with the software source’s GPG signing configuration).
  • Supporting firmware: openRuyi-Project’s k3firmware released Boot Firmware for SpacemiT K3 version 20260929 (this release includes CI packaging directory structure cleanup; the previous version was 20260825).

1.5 Ecosystem Shorts: Bare-Metal Verification Practice for Lua/OCaml on the Sail RISC-V Model

Date: 2026-09-29　Source: ship-your-lua repository (09-29 commit), ship-your-ocaml repository (09-29 commit)

Two new developments have emerged in the formal verification direction: first, the ship-your-lua project performs end-to-end verification of Lua 5.4.7 compiled to bare-metal RV64 on the Sail RISC-V model using Lean 4 and iris-lean (completing an ELF disassembly survey and semantic scaffolding, among other work); second, ship-your-ocaml verifies the OCaml bootstrap compiler—its verification records show differential testing passing 9 out of 9, with boot/ocamlc completing one compilation on the Sail model (approximately 81.9 million steps). Both are frontier practices in “verifiability of the language runtime stack” (the previous generation, ship-your-interpreter, already proved the refinement relation for a WHILE interpreter ELF).

II. Product and Ecosystem Developments

2.1 GF’s MIPS: Completes ARC Integration, Anchors on RISC-V Physical AI, Partners with Xcelsa to Accelerate Custom Silicon

Date: 2026-09-29　Source: digitimes “GF’s MIPS bets on RISC-V physical AI, expands into autos and data centers” (09-29, Google News aggregator link), Industry Events reposted summary (09-29), Business Wire “MIPS and Xcelsa Collaborate to Accelerate Verified, Workload-Optimized Custom Silicon” (09-29)

digitimes reported on 09-29: MIPS, under GlobalFoundries, says it has completed the integration of Synopsys’ ARC processor IP business, anchoring on RISC-V as its foundation for Physical AI and expanding from AIoT into automotive and data center applications; it claims the merger has made GF and MIPS the world’s second-largest processor IP supplier. On the same day, Business Wire reported: MIPS has entered a strategic partnership with Xcelsa Labs — leveraging Xcelsa’s Apex design optimization platform (formal equivalence assurance) to accelerate custom chip development based on MIPS IP, covering AI, automotive, industrial, robotics, and edge scenarios. Earlier in early September, MIPS had already launched three workload-native platforms: Acies, Actus, and Aegis.

2.2 Nuvacore: Unveils “Core First” Development Model, Keeps ISA Choice Open

Date: 2026-09-29　Source: Notebookcheck “Apple Silicon and Nuvia veterans reveal unusual CPU core that keeps its ISA options open” (09-29), Tom’s Hardware “Legendary Qualcomm, Apple, and Nuvia alumni form new CPU startup” (background)

CPU startup Nuvacore, founded by Gerard Williams III, John Bruno, and Ram Srinivasan (with Apple/Nuvia/Qualcomm backgrounds), has disclosed the “Core First” model for its first general-purpose core, WarpCore: build an ISA-decoupled microarchitecture foundation first, then select the instruction set based on the target system; its recruiting materials list RISC-V, Arm64, and x86 side by side, interpreted as keeping ISA options open — media noted that RISC-V offers the most direct path since it avoids Arm-style architecture licensing, while decode, privilege levels, memory ordering, and software compatibility remain the decisive constraints on the final ISA. The company has not yet disclosed its ISA choice, process node, or tapeout plans.

2.3 SignOff: Demonstrates Full Custom Silicon Flow Capabilities with RISC-V “Kaveri” Soft IP

Date: 2026-09-29　Source: Electronics For You “SignOff Builds Toward a Bigger Role in Custom Silicon” (09-28/29)

Indian design services firm SignOff Semiconductor is expanding from VLSI design services into turnkey custom silicon: it showcases customizable RTL and application-centric peripheral functions as soft IP on its in-house RISC-V “Kaveri” platform, positioning it as a “proof of capability” rather than a product line — targeting customers who want a single partner to handle everything from architecture to silicon implementation. The company says it has completed multiple application demonstrations on the platform and is combining foundry and OSAT ecosystem partnerships with EDA investment to take on end-to-end projects.

III. Deep Dive on Domestic Teams

3.1 ESWIN Computing: IPO Follow-up Coverage Focuses on Wang Dongsheng, Financial and Business Fundamentals Under Scrutiny

Date: 2026-09-29　Source: Jumpstart Magazine “The Man Who Built China’s Screen Giant Is Betting on RISC-V” (09-29), Phoenix Finance “In-Depth Analysis of ESWIN Computing’s Hong Kong IPO” (09-29)

Around ESWIN Computing’s (01256.HK) IPO (launched 09-28, listing planned for October 9), several in-depth analyses appeared within the window: a Jumpstart Magazine long-form piece focuses on founder Wang Dongsheng (founder of BOE, who began a “second venture” at age 62) and the use of proceeds—net proceeds of approximately HK$2.27 billion (at the midpoint pricing), of which 35% goes to chip products, 30% to the RISAA (RISC-V + AI) platform, 15% to potential M&A, 10% to marketing and the RISC-V ecosystem, and 10% to working capital; the Phoenix Finance article analyzes its “coexistence of high growth and high losses”: 2025 revenue of RMB 2.431 billion, net loss of RMB 1.516 billion; Q1 2026 revenue of RMB 494 million (up 18.4% YoY), net loss of RMB 375 million; by 2025 revenue, it is China’s largest domestic smart terminal human-machine interaction chip provider and China’s third-largest domestic RISC-V main control chip provider.

3.2 SpacemiT: Concentrated Commits to K3 Native Triton Tutorial Repository

Date: 2026-09-29　Source: spine-triton-tutorial commit: K3-native scope v2 rewrite (09-29), spine-triton-tutorial commit: initial tutorial (skill basics + 10 operator guides) (09-29)

SpacemiT’s newly created spine-triton-tutorial repository (created 09-29) completed 3 commits within the window: from the initial tutorial (skill basics + 10 operator guides) to the v2 rewrite completed the same day—rewriting ops/08 through 09 for the K3-native scope and adding an ops/10-cat operator chapter, plus a first demo. Triton operator development for K3 now has systematic, follow-along official materials.

3.3 Espressif: esp-sr Adds Multilingual Wake-Word Models, Multi-Repository Maintenance Advances

Date: 2026-09-29　Source: esp-sr commit: adds German/Japanese/French wn10 wake-word models (09-29), esp-hosted-linux commit: fixes beacon set ie regression (09-29), esp-bist merge: hd_ram and documentation v1.1 update (09-29)

Espressif advanced across multiple repositories within the window: esp-sr added German, Japanese, and French wn10 wake-word models and merged them into the multi_lang branch (multilingual voice front-end expansion); esp-hosted-linux fixed a beacon set ie regression and corrected some IEs APIs (stability maintenance for ESP32 as a Linux host Wi-Fi co-processor); esp-bist (built-in self-test) merged hd_ram and documentation v1.1 updates, and esp-vision fixed expression evaluation in Windows builds. The above constitutes the day’s mainline developments covering the ESP32-C/S series RISC-V product lines.

3.4 Sipeed: SLogic Releases 2.0.0, slogic16u3-tools Ships Two Versions Back-to-Back

Date: 2026-09-29　Source: SLogic release release-2.0.0 (09-29), SLogic commit: Windows CI build ngscopeclient (09-29), slogic16u3-tools release v0.1.6 (09-29)

Sipeed’s SLogic logic analyzer software stack released release-2.0.0 (the last batch of commits within the window includes building ngscopeclient on Windows, a macOS Vulkan alias packaging fix, and a libsigrok dev_close event thread fix); the companion slogic16u3-tools shipped v0.1.5 and v0.1.6 on the same day (eFuse write determination, openFPGALoader status bit parsing, multi-channel verification log alignment, and other refinements). Following the 09-28 issue’s “ngscope native driver phase one,” this toolchain has entered a versioned release cadence.

3.5 Sophgo: sophon-demo Refines Qwen3.5 Examples and Web UI

Date: 2026-09-29　Source: sophon-demo commit: Qwen3_5 Web UI example (Flask streaming chat) (09-29), sophon-demo commit: Qwen3_5 long-text robustness fix (09-29), bootloader-riscv commit: SG2044 adds OpenBMC firmware upgrade package (09-29)

Sophgo’s sophon-demo advanced its Qwen3.5 large model examples: adding a Web UI example (Flask streaming chat interface) and fixing repetition and crash issues caused by long text and abnormal input; bootloader-riscv added OpenBMC firmware upgrade packaging for SG2044 (64-core server platform); the edge_dev branches of osdrv and bootloader-arm64 continued daily pushes. The SG2044 and CV series software stacks remain active in parallel.

IV. Special Chapter on Embodied Intelligence and Robotics

4.1 SpacemiT Robotics: ros2_humanoid Adds ASR Action Voice Prompts

Date: 2026-09-29　Source: ros2_humanoid commit: ASR action voice prompts and robust playback (09-29)

SpacemiT Robotics’ ros2_humanoid repository added one commit within the window: adding voice prompts and a more robust playback mechanism for ASR actions—building on the Qwen3-ASR voice action control covered in the 09-28 issue, the feedback and fault tolerance of the voice interaction chain continue to be refined. On the rest of the robotics side: no other substantive developments from relevant domestic teams in this window (member website inspections revealed no robotics-direction updates).

V. Summary and Trend Observations

  • A virtuous cycle of new hardware and distro follow-up: Zhike Computing’s A210 receives a batch of RevyOS kernel support (including multiple standardized dt-bindings and driver commits); openRuyi releases K3 firmware 20260929 and rolls linux-lts forward to 6.18.54.
  • RISC-V’s commercial standing rises at the processor IP layer: GF and MIPS claim to become the world’s second-largest processor IP supplier after completing ARC integration, and complete the “workload-to-custom-silicon” chain through the Xcelsa collaboration; automotive and data centers are clear expansion directions.
  • “ISA openness” draws attention from top-tier teams again: Nuvacore’s Core First model defers ISA selection, and RISC-V becomes a direct beneficiary option due to licensing costs.
  • Domestic vendors’ toolchains enter a versioned and instructional phase: Sipeed’s SLogic 2.0.0 and slogic16u3-tools dual releases, SpacemiT’s K3 Triton tutorial taking shape, Espressif’s multilingual voice models—moving from “usable” to “learnable and releasable.”
  • The XiangShan family maintains high-frequency branch-level development: four backend fix PRs in the main repository focus on the issue and sequencing paths, difftest lays out CROB comparison lines, and the simulation chain and implementation chain advance in sync.
  • To watch: ESWIN pricing and listing (October 9), openRuyi 2026.09 release, the review trajectory of the four XiangShan PRs; DAMO XuanTie, Nuclei, Radxa Linkr, and others were silent within the window.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Hacker News No major RISC-V-related hits within the window
Google News aggregation (multiple Chinese and English queries, via proxy) English side yielded and included digitimes MIPS, Notebookcheck Nuvacore, Jumpstart ESWIN feature, SignOff, etc.; Chinese side yielded Phoenix News ESWIN IPO analysis (included in 3.1), the rest being stock market and industry roundup noise, filtered out by semantics
English media and vendor side embeddedcomputing republished SiFive BigSky and AMD ROCm demo coverage on 09-29 (original event 09-15, already included in the 09-16/09-17 issues, not repeated this issue); Electropages published EVAS funding analysis on 09-29 (09-18 event, already included in the 09-21 issue); SiFive/Andes/StarFive/Milk-V had no new articles within the window
GitHub organizations and key repositories Pushes within the window: espressif 35, sipeed 7, sophgo 4, openRuyi-Project 3, spacemit-com 2, spacemit-robotics 1, revyos 1 (A210 support batch); the XiangShan main repos and difftest, GEM5, NEMU all had branch-level pushes; XUANTIE-RV, eswincomputing, Nuclei-Software, openhwgroup, radxa-linkr had 0 within the window
RISC-V International official website and blog No new announcements; the ecosystem landscape repository was routinely refreshed by LFX tooling (data maintenance, not listed separately)
openRuyi dual sources No new version on the official website (2026.09 not released); 2 SPECS commits in the main repository, plus the accompanying K3 firmware release 20260929 (included)
Member company website sweep Swept 391 companies: 100 pages had updates, all marketing/rolling content with no substantive developments; 68 failed to fetch (including ISCAS, Beijing Institute of Open Source Chip, Andes, etc.), not affecting conclusions
CNX/LinuxGizmos/Phoronix RSS No new RISC-V-related hits within the window