Research window: Past 24 hours (2026-09-28 05:00 ~ 2026-09-29 05:00, Beijing time).

Sources: Business Wire, EE Times, IndexBox, Google News aggregation (multiple Chinese and English queries, via proxy), RTHK, Economic Reference Network, Hong Kong Commercial Daily, RISC-V International Foundation blog, LinuxGizmos and other RSS feeds (keyword filtering), as well as GitHub (push and commit searches across organizations and key repositories including XiangShan/NEMU/GEM5/difftest, DAMO XuanTie XUANTIE-RV, Sophgo, Espressif, SpacemiT, Sipeed, revyos, openRuyi-Project, Radxa Linkr; including website inspections of 391 member companies).

Index

  • Today’s Highlight: ESWIN Computing officially launches Hong Kong IPO, priced at HK$1.48–1.59, raising up to approximately HK$2.5 billion, listing planned for October 9 (09-28)
  • I. Open Source Community and Software Ecosystem
    • XiangShan: bosc IOMMU and DMAC/IOPMP integration lands, 4 merges to main repository (09-28)
    • XiangShan simulation chain: GEM5 prefetch experiments continue with BDP parameterized tuning, NEMU disables AME checks (09-28)
    • rv32emu: system emulation batch merged, approximately 20 commits for JIT and memory pool optimization (09-28)
    • felix86: fake online core count, two fixes for Wine int 0x2d (09-28)
    • openRuyi dual-source verification: five SPECS commits, no new release on official website (09-28)
    • Ecosystem briefs: RISC-V International Foundation publishes community profile feature (09-28)
  • II. Product and Ecosystem Developments
    • Efinix releases Sapphire RV64: 64-bit RISC-V FPGA soft-core SoC (09-28)
    • Xcena MX1 detailed by EE Times: CXL memory integration with over a thousand RISC-V cores (09-28)
  • III. Deep Dive on Domestic Teams
    • RevyOS: five kernel branches updated in batch, adds ESWIN EIC7700 support (09-29 early morning)
    • SpacemiT: vision model library adds RTMPose pose estimation (09-28)
    • Espressif: esp-idf maintenance branches and esp-hosted-linux continue advancing (09-28)
    • Sipeed: SLogic logic analyzer ngscope native driver phase one lands (09-28)
    • Sophgo: CV84x6 software adaptation continues (09-28)
  • IV. Embodied Intelligence and Robotics Special Section
    • SpacemiT Robotics: ros2_humanoid adds Qwen3-ASR voice action control (09-28)
  • V. Summary and Trend Observations

Today’s Highlight: ESWIN Computing Officially Launches Hong Kong IPO, Listing Planned for October 9

Date: 2026-09-28　Sources: RTHK “ESWIN Computing IPO raises up to approximately HK$2.5 billion, may become the first ‘RISC-V’ stock” (09-28), Economic Reference Network “ESWIN Computing launches Hong Kong IPO” (09-28), Hong Kong Commercial Daily “RISC-V chipmaker ESWIN Computing (01256) opens subscription today, plans global offering of approximately 1.57 billion shares” (09-28)

On September 28, Beijing ESWIN Computing (01256.HK) officially launched its Hong Kong global offering: approximately 1.57 billion H shares (of which approximately 10% is the Hong Kong public offering), offer price range of HK$1.48 to HK$1.59 per share, 2,000 shares per lot with an entry fee of approximately HK$3,212, and total fundraising of up to approximately HK$2.497 billion (nearly HK$2.5 billion, approximately US$320 million) at the top of the range. Subscription will close on October 6, with listing on the Main Board of the Hong Kong Stock Exchange expected on October 9; joint sponsors are CITIC Securities and China Securities International.

The company has introduced cornerstone investors including CITIC Asset Management Hong Kong, Japan’s Orix, Hefei Construction Investment, and GBAHIL (Greater Bay Area Homeland Investments), subscribing to a total of approximately HK$1.161 billion; proceeds will be mainly used for product development of human-machine interaction and multimedia processing chips, interconnect and computing chips, and the construction of software and hardware technology platforms, as well as potential strategic acquisitions. According to the prospectus, as of the end of March 2026, the company has launched over 150 software-hardware co-designed products, serving more than 220 customers globally, and has accumulated over 620 IP modules and more than 20 series of RISC-V cores. If the offering proceeds smoothly, it will become the first RISC-V-focused chip company listed in Hong Kong (Hong Kong has already listed RISC-V as one of seven key emerging industries in its 2026-27 budget); this publication will continue to track the pricing and listing milestones.

I. Open-Source Community and Software Ecosystem

1.1 XiangShan: bosc IOMMU and DMAC/IOPMP integration lands, 4 merges in main repo

Date: 2026-09-28　Source: XiangShan commit: integrate bosc IOMMU with DMAC, IOPMP (#6560) (09-28), XiangShan commit: ckpt_select passes random seed (#6637) (09-28), difftest PR #976: MinimalMatrixConfig checker compatibility fix (09-28)

The XiangShan main repository’s default branch (kunminghu-v3) merged 4 commits in the window, the core being the simulation integration of bosc IOMMU with DMAC and IOPMP (#6560): changes cover the OpenIOMMU submodule, simulation top level and device configuration, IOMMU test cases (Iommu.scala / SimMMIO / SimTop), etc., advancing system-level IOMMU integration another step (the difftest side had previously added OpenIOMMU simulation file tables, see #974). The rest are engineering-side: ckpt_select supports passing a random seed (#6637), CI ignores dependabot configuration (#6612), and dependabot is enabled for kunminghu-v2 (#6611). difftest created the fix-ame-minimal branch on 09-28 and opened PR #976 (MinimalMatrixConfig checker compatibility fix).

1.2 XiangShan simulation chain: GEM5 prefetch experiments continue with parameterized BDP control, NEMU disables AME checks

Date: 2026-09-28　Source: GEM5 commit: parameterized BDP incremental depth control (09-28), GEM5 commit: retain G12 predictive stream depth controller (09-28), NEMU commit: temporarily disable AME MS domain checks (#1236) (09-28)

The GEM5 prefetch branch feat-ywl-pfbuffer advanced 2 commits in the window: adding parameterized BDP (bandwidth-delay product) incremental depth control and retaining the G12 predictive stream depth controller—continuing the tuning wrap-up after last period’s 31 experiments. NEMU merged #1236: temporarily disabling the check logic for the AME (matrix extension) MS domain, a routine adjustment to the matrix extension simulation path (v2026.09.r18 was just released on 09-25).

1.3 rv32emu: system emulation batch merged, ~20 commits on JIT and memory pool optimization

Date: 2026-09-28　Source: rv32emu merge: bench branch PR #783 (09-28), rv32emu commit: system emulation selects tier-1 JIT (09-28), rv32emu commit: move T2C cache maintenance off the hot path (09-28)

The educational RV32 emulator rv32emu merged a bench branch batch in the window (PR #783, ~20 commits), concentrating on strengthening system emulation capabilities: system emulation scenarios switch to tier-1 JIT, T2C (translation cache) maintenance moves off the hot path, translated code is retired when the guest actively flushes, only the emulator thread uses the memory pool, and branch sampling analysis under a guest OS plus dual-host benchmark recording are added; the tooling side supports paging to view more prebuilt versions. Following last period’s inclusion of Linux image builds (#786), the project continues to double down on both “runs systems” and “runs fast.”

1.4 felix86: faking online core count, fixing Wine int 0x2d

Date: 2026-09-28　Source: felix86 commit: fake online CPU core count (#799) (09-28), felix86 commit: fix int 0x2d under Wine (#800) (09-28)

The binary translation project felix86, which runs x86 games on RISC-V Linux, merged 2 more commits in the window: faking the online CPU core count reported to applications (to work around hard-coded core-count assumptions in some programs), and fixing handling of int 0x2d (an FPU-emulation-related interrupt) in the Wine environment. Since mid-September the project has maintained a high-frequency compatibility-polishing cadence, accumulating over a dozen commits in a week.

1.5 openRuyi dual-source verification: five SPECS commits, no new release on the official site

Date: 2026-09-28　Source: openRuyi commit: add GPG public key to openruyi-repos (09-28), openRuyi commit: restore arptables and ebtables to iptables (09-28), openRuyi official news page (09-28 check)

  • Official news page: the 2026.09 release is still unpublished (most recent release is 2026.08).
  • GitHub main repository: 5 SPECS commits in the window—adding a GPG public key to the software source configuration (openruyi-repos and its format adjustments), adding a gnupg recommended dependency to openruyi-minimal, restoring iptables’ arptables/ebtables components, and adjusting pre-commit hook dependencies—continuous polishing of the distribution packaging layer (this repository had 0 commits last period).

1.6 Ecosystem briefs: RISC-V International publishes community profile feature

Date: 2026-09-28　Source: RISC-V International “Community Motion: What Are RISC-V Advocates Doing?” (09-28)

The RISC-V International blog published a community profile feature, “Community Motion,” introducing four advocates: Guodong Xu (RVA23 from standard to deployment practice), Jingwei Wang (software ecosystem building), Tobias Scheipel (teaching and community operations), and Tan Siret Akinci (Turkish community). It continues to output organizational narratives along the dimensions of international standards, education, and regional ecosystems.

II. Product and Ecosystem Updates

2.1 Efinix Releases Sapphire RV64: 64-Bit RISC-V FPGA Soft-Core SoC

Date: 2026-09-28　Source: Business Wire “Efinix Brings 64-Bit RISC-V Performance to Embedded FPGA Designs With New Sapphire RV64 SoC” (09-28), Efinix Sapphire RV64 User Guide (official documentation)

FPGA vendor Efinix has released the Sapphire RV64 SoC: extending the Sapphire soft-core family from 32-bit to 64-bit RISC-V—a seven-stage pipeline supporting optional A/F/D/C and Zba/Zbb/Zbs/Zicbom extensions; on-chip 4 to 512KB RAM, multi-way L1 instruction/data caches, optional L2 cache (64 to 512KB, 8-way), branch predictor, and hardware/software prefetching; paired with DDR/LPDDR4 memory controllers, configurable with 1 to 4 64-bit cores at 20 to 400MHz. The product targets edge AI and embedded Linux scenarios “where applications have outgrown the addressing, cache, and I/O limits of 32-bit cores,” and can be used across all Titanium/Topaz FPGAs and Trion (T20 and above) devices, with graphical configuration via the Efinity IP Manager. Official documentation states the core is similar to the open-source VexiiRiscv and has been optimized for the company’s own devices.

2.2 Xcena MX1 Detailed by EE Times: CXL Memory Integrating Over a Thousand RISC-V Cores

Date: 2026-09-28　Source: EE Times “Xcena Cuts Data Movement to Address Memory Bottlenecks” (09-28), IndexBox “Xcena MX1: CXL Near-Memory Processing with 2TB DDR5 and 1,000+ RISC-V Cores” (09-28)

EE Times and IndexBox published articles on 09-28 detailing South Korean semiconductor company Xcena’s MX1 computational CXL memory device (announced at Hot Chips 2026 this summer): a single card integrates up to 2TB DDR5 (4 channels, CXL 3.2 / PCIe 6.0), exposes SSDs as byte-addressable memory via InfiniteMemory, and integrates a near-memory compute unit comprising over 1,000 in-house 1.4GHz RISC-V cores (tech media reports 3,072 cores, with 24 subsystems sharing 128MB L3) plus an approximately 3 TFLOPS FP32/FP16 vector engine; official figures cite up to 4.7x throughput and 18.7x energy efficiency on data analytics workloads compared with a host CPU accessed via CXL. Developers program in C/C++/Rust via an LLVM toolchain, with mass production planned for end-2026 and revenue beginning in 2027. The large-scale deployment of RISC-V cores in “memory wall” scenarios is the highlight of these reports.

III. Deep Dive on Domestic Teams

3.1 RevyOS: Batch Updates Across Five Kernel Branches, Adds ESWIN EIC7700 Support

Date: Early morning 2026-09-29　Sources: revyos/linux commit: Enable ARCH_ESWIN/DWMAC_EIC7700/PINCTRL_EIC7700 (early 09-29), revyos/linux commit: K1/K3 platform configuration (early 09-29), revyos/linux commit: Enable drm powervr (early 09-29)

The RevyOS kernel repository (revyos/linux) pushed roughly 20 configuration updates in batch to each of five branches (revyos/6.18.y and 7.0.y through 7.3.y) at the end of the window. The core change is new support for the ESWIN EIC7700 platform (ARCH_ESWIN, DWMAC_EIC7700 Ethernet, PINCTRL_EIC7700), along with completed configuration for the SpacemiT K1/K3 series (K3 display controller, K3 UFS, K1 USB2 on Banana F3, etc.). It also enables PowerVR GPU DRM and TH1520 GPU power sequencing, RESET/PHY-related drivers, and linuxboot configuration, with cross/native builds added on the CI side. This is a cross-kernel-version configuration baseline sync, filling in new hardware support for both the 6.18 and 7.x kernel lines.

3.2 SpacemiT: Vision Model Zoo Adds RTMPose Pose Estimation

Date: 2026-09-28　Sources: model-zoo-vision commit: Add RTMPose pose estimation (#96) (09-28), spacemit-com/ai-sdk repository (vision submodule sync)

SpacemiT’s model-zoo-vision added the RTMPose human pose estimation model (#96), continuing the repository’s recent line of RVV pre-processing and post-processing acceleration for SuperPoint, segmentation, OCR, face/CLIP and other models on the K1/K3 platforms; ai-sdk synced its vision submodule. See Chapter IV for its robotics-side developments.

3.3 Espressif: esp-idf Maintenance Branches and esp-hosted-linux Continue

Date: 2026-09-28　Sources: esp-idf commit: Handle Read Remote failure after NimBLE ACL connection (release/v5.4) (09-28), esp-hosted-linux commit: Sync firmware version header to 1.0.6.0.8 (09-28), esp-hosted-linux commit: Switch OTA command to 30-second timeout (09-28)

Espressif’s activity in the window was mainly maintenance merges: the esp-idf release/v5.4 maintenance branch merged handling for the NimBLE “Read Remote failure after ACL connection establishment” case and strengthened checks for unsupported features; esp-hosted-linux added 3 more commits after 09-25 — syncing the host-side firmware version header to 1.0.6.0.8, switching the OTA command to a 30-second timeout, and skipping the TX-aggr alignment check over SPI. This investment covers the full chip lineup including the ESP32-C/S series RISC-V product lines.

3.4 Sipeed: SLogic Logic Analyzer’s ngscope Native Driver Phase One Lands

Date: 2026-09-28　Sources: SLogic commit: ngscope native SLogic driver phase one (09-28), SLogic commit: Group-level analog/digital channel switching (09-28), slogic16u3-tools commit: Assign a dedicated DFU PID for SLogic32U3 (09-28)

Sipeed’s SLogic logic analyzer software stack advanced 7 commits in the window: the ngscope client landed the “native SLogic driver (phase one)”, no longer depending on sigrok-bridge, and now supports runtime capture width selection, group-level analog/digital channel switching, and automatic reordering display, with build artifacts renamed uniformly under scopehal-apps; on the tooling side, a dedicated DFU PID (0x30F2, distinct from 16U3’s 0x30F1) was assigned to the SLogic32U3 and the eFuse writing flow was streamlined. The open-source test and measurement toolchain for the RISC-V ecosystem continues to fill out.

3.5 Sophgo: CV84x6 Software Enablement Continues

Date: 2026-09-28　Sources: sophon-demo commit: Correct SE13-64 (CV84X6) host CPU specs (09-28), sophgo/build repository (edge_dev branch continues pushing), sophgo/osdrv repository (edge_dev branch continues pushing)

Following the previous issue’s large-scale rollout of the CV84x6 (84x6) platform across 16 repositories, Sophgo pushed to 3 more repositories in the window: the build and osdrv edge_dev branches continued updating (09-28), and sophon-demo documentation corrected the SE13-64 (CV84X6 platform) host CPU specs to an 8-core Cortex-A55@2.0GHz. The new platform’s software stack is still in its iteration phase, with hardware spec details being progressively corrected.

IV. Embodied Intelligence and Robotics Special Chapter

4.1 SpacemiT Robotics: ros2_humanoid Adds Qwen3-ASR Voice Action Control

Date: 2026-09-28　Source: ros2_humanoid commit: Add Qwen3-ASR voice action control backend (09-28)

SpacemiT Robotics’ ros2_humanoid repository added a Qwen3-ASR backend, using speech recognition to drive humanoid robot action control — connecting with the RGB-D SLAM and Nav2 support covered in the 09-23 issue, as well as the earlier ZMQ policy switching and voice stand-up control lines. Its humanoid robot software stack is advancing along the overlay of “voice/multimodal interaction plus ROS2 navigation.”

Other robotics-side news: no other substantive developments from relevant domestic teams in the window (member company website inspections showed no robotics-direction updates).

V. Summary and Trend Observations

  • Capitalization enters the issuance landing phase: ESWIN Computing officially opened its IPO subscription on 09-28 (priced at HK$1.48–1.59, raising up to approximately HK$2.5 billion, with listing planned for October 9). The pricing and subscription enthusiasm for the Hong Kong stock market’s “first RISC-V stock” will form a public reference for sector valuations.
  • Distributions are simultaneously pushing new hardware support into kernels: RevyOS updated configurations in batch across five kernel branches — 6.18 and 7.x — overnight: ESWIN EIC7700, K1/K3 display and storage, PowerVR GPU. The rhythm of “distributions quickly following up once boards and SoCs are ready” is accelerating; openRuyi also remains active at the SPECS layer.
  • XiangShan’s IOMMU and prefetch advance on two fronts: the main repository merged bosc IOMMU and DMAC/IOPMP simulation integration, while on the GEM5 side BDP stream depth tuning moves toward parametric finalization — Kunminghu v3’s system integration and performance experiments continue to deepen along both lines.
  • RISC-V expands toward “non-MCU compute positions”: Efinix pushed its FPGA soft core to 64-bit, and Xcena uses over a thousand RISC-V cores for CXL near-memory computing — two product developments appearing the same day, one hardware and one software, point to the same trend: RISC-V cores are moving from control-type scenarios toward data-plane and memory-side compute.
  • Verification, translation, and toolchains continue to thicken: rv32emu system emulation JIT batches, felix86 compatibility layer polishing, Sipeed’s logic analyzer, and the openRuyi packaging layer — infrastructure-type projects maintain a high-frequency, small-step cadence.
  • To watch: DAMO XuanTie, ESWIN Computing (GitHub), Nuclei and others were silent in the window; next issue will focus on ESWIN’s pricing and subscription progress, XiangShan IOMMU/prefetch merge developments, and whether openRuyi 2026.09 is released.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Hacker News No major RISC-V-related hits within the window
Google News aggregation (multiple Chinese and English queries, via proxy) English side yielded Efinix RV64, Xcena, ESWIN IPO, etc.; Chinese side showed dense coverage of the ESWIN IPO (RTHK / Economic Information Daily / Hong Kong Commercial Daily / Stockstar / Sina Finance, etc.), with old articles and gambling/stock-market-style headlines removed by semantic filtering
English media (Business Wire / EE Times / IndexBox, etc.) Efinix Sapphire RV64 and Xcena MX1 hit and included; no new articles from SiFive / Andes / RISC-V Summit within the window
GitHub organizations and key repositories (API with Atom fallback) Pushes within the window: espressif 27, spacemit-com 4, spacemit-robotics 1, sipeed 5, revyos 2 (including batch commits across five branches of revyos/linux), openRuyi-Project 5, sophgo 3; XiangShan family 4 (XiangShan main repo 4 commits, GEM5 branch 2 commits, NEMU 1 commit, difftest branch and PR); XUANTIE-RV, eswincomputing, Nuclei-Software, openhwgroup, radxa-linkr 0 within the window
RISC-V International official website and blog Blog published a community profile feature (included); no new announcements on the official website
openRuyi dual-source No new release on the official website (2026.09 not released); 5 SPECS commits in the main repository (included)
Member company website sweep Swept 391 companies: 93 had page updates, all marketing/rolling content with no substantive developments; 67 failed to scrape (including ISCAS, Nuclei, Andes, Ingenic, etc.), which does not affect the conclusions
CNX / LinuxGizmos / Phoronix RSS No new RISC-V-related hits within the window