Research window: Past 3 days (2026-09-25 05:00 ~ 2026-09-28 05:00, Beijing time; includes weekend period, last report was 09-25).

Sources: Hacker News, Google News aggregation (multiple Chinese and English queries, via proxy), South China Morning Post, The Standard, ChipNews, LinuxGizmos, CNX Software, kit-e.ru/mforum.ru, ZOL, Beijing Daily, RISC-V International official website (including member company website inspection of 391 companies), openRuyi official news page, and GitHub (XiangShan/NEMU/GEM5/difftest/XSCache, DAMO XuanTie XUANTIE-RV, Sophgo, Espressif, SpacemiT, Sipeed, revyos, Radxa Linkr, openRuyi-Project and other organizations and key repositories’ push and commit searches).

Index

  • Today’s Highlights: ESWIN Computing launches Hong Kong IPO, seeking ~US$300 million, expected to list on October 8 (09-25)
  • I. Open Source Community and Software Ecosystem
    • XiangShan: feat-pdb prefetch data buffer improvement gating merged, XSCache “Oceanus” L2 receives 4 more fixes (09-27)
    • XiangShan simulation chain: GEM5 prefetch modeling sees 31 experiments over the weekend, NEMU releases v2026.09.r18 (09-27)
    • felix86: 8 commits in the window, SHA extension and VMCALL landed (09-27)
    • Open source ecosystem briefs: rv32emu improves Linux image build, openRuyi has no new additions in the dual-source window (09-27)
  • II. Product and Ecosystem Updates
    • ESP-Mosaico: Espressif ESP32-S31 modular development kit gets detailed media coverage (09-27)
    • LILYGO T-Dongle-C5: ESP32-C5 dual-band Wi-Fi 6 USB dongle receives comprehensive coverage (09-27)
    • Russian K1921VG10Ya: dual-core RISC-V MCU repackaged in 13×13mm BGA (09-25)
  • III. Deep Dive on Domestic Teams
    • Sophgo: 16 repositories pushed in bulk, 84x6 (CV84x6) new platform and 88a2 platform support landed (09-26)
    • DAMO XuanTie: DAMO-RV-ATS test suite adds vector fixed-point and memory access tests (09-27)
    • Espressif: esp-idf sees 7 merges in the window, esp-hosted-linux repository continues to advance (09-25)
  • IV. Embodied Intelligence and Robotics Special Chapter
    • Ruixin Gaoguang D35: officially mass-production launched at the Global Digital Trade Expo, with concentrated signings with enterprises across multiple sectors (09-25)
  • V. Summary and Trend Observations

Today’s Highlights: ESWIN Computing launches Hong Kong IPO, seeking ~US$300 million, expected to list on October 8

Date: 2026-09-25　Sources: South China Morning Post “Chinese RISC-V chipmaker Eswin seeks US$300m in Hong Kong IPO ahead of October debut” (09-25), The Standard “ESWIN Computing Technology eyes US$300m HK IPO” (09-23), ChipNews “Eswin edges toward the first RISC-V listing in Hong Kong” (09-25)

According to a South China Morning Post report on 09-25, Beijing ESWIN Computing will begin taking orders from institutional and public investors starting this Monday (09-28, the date of this report), targeting approximately US$300 million (about HK$2.34 billion), and is expected to list on the Hong Kong Stock Exchange on October 8; the joint sponsors are CITIC Securities (Hong Kong) and China Securities International. The company had previously passed the HKEX listing hearing (covered in our 09-21 issue), and the final stretch of procedures before the opening has officially begun.

On the financial front, its prospectus shows 2025 revenue of RMB 2.431 billion (up about 20% year-on-year), with a full-year net loss of RMB 1.5 billion — a curve of “high revenue growth, narrowing losses” that will face the pricing test of international investors, and is also a key sample for observing the viability of the RISC-V chip business model.

If the offering proceeds smoothly, ESWIN Computing will become the first chip company listed in Hong Kong with RISC-V as its main business, filling the gap in listed targets in this track and providing a public market reference for the “valuation anchor of RISC-V ecosystem companies.” The offering size, pricing, and subscription enthusiasm may still adjust with market conditions, and the final announcement shall prevail; we will track the listing results in early October.

I. Open-Source Community and Software Ecosystem

1.1 XiangShan: feat-pdb Prefetch Data Buffer Promotion Gating Merged, XSCache “Oceanus” L2 Fixes 4 More Commits

Date: 2026-09-25 to 09-27　Source: XiangShan commit: Gated prefetch data buffer promotion (09-27), XSCache commit: EvictBack field assignment completion (09-27), XSCache commit: Wait for CompAck during data-separated response phase (09-26), XSCache commit: L2VPipeSNP supports all writeback types and retries (09-26), XSCache commit: Retry state leak fix (09-26)

The XiangShan main repository’s default branch (kunminghu-v3) saw no new commits in this window (last merge was 09-24, covered in the previous issue), with development activity concentrated on feature branches: after feat-pdb introduced a coherent prefetch buffer on 09-21, this period added one commit for “prefetch data buffer promotion gating,” supplementing admission conditions for the promotion path by which data moves from the prefetch buffer into the cache.

The cache subsystem XSCache “Oceanus” (L2 development branch) fixed 4 more commits, all boundary corrections to the CHI coherence pipeline: EvictBack field assignment completion, waiting for CompAck only upon entering the data-separated response phase, L2VPipeSNP support for all writeback types and retries, and cleanup of leaked state on the retry path. This branch had 20 commits recorded in the 09-23 issue, and this period continues the wrap-up of fixes.

1.2 XiangShan Simulation Chain: GEM5 Prefetch Modeling Sees 31 Weekend Experiment Commits, NEMU Releases v2026.09.r18

Date: 2026-09-26 to 09-27　Source: GEM5 commit: Select predictive stream depth controller (09-27), GEM5 commit: BDP upshift hysteresis enhancement (09-27), GEM5 commit: H2P useful admission rate statistics (09-27), GEM5 commit: H2P buffer metadata lifecycle tightening (09-26), GEM5 commit: Vector register rename panic fix (#1185), NEMU Release v2026.09.r18 (09-25)

GEM5’s two development branches advanced a total of 31 experiment commits over the weekend: feat-ywl-pfbuffer with 20 in a single day, building a family of BDP (bandwidth-delay product) stream depth adaptive controllers—from selecting a predictive stream depth controller, to extending, tightening, and damping trend prediction, and on to upshift hysteresis and phase-change adaptive filtering; apf-align with 11, centered on H2P prefetch buffer admission and lifecycle modeling: entries retained at commit and released at resolve, allocating candidates gated by TAGE weak confidence, plus idle-cycle statistics, useful admission rate, and a weak-confidence A/B switch. The default branch (xs-dev) concurrently fixed a vector register rename panic (#1185).

NEMU released v2026.09.r18 on 09-25: packaging the previously merged share-ctrl CUTE AMU callback refinement (#1225, that commit was covered in the previous issue of this newsletter), and routinely providing prebuilt artifacts for the xs/xs-dual and ref/ref-debug combinations; the September rolling release cadence holds through the 18th version.

1.3 felix86: 8 Commits in the Window, SHA Extension and VMCALL Land

Date: 2026-09-25 to 09-27　Source: felix86 commit: Implement SHA extension (#795) (09-27), felix86 commit: Implement VMCALL (#797) (09-27), felix86 commit: Add Wayland thunks (#796) (09-27), felix86 commit: Fault on non-executable pages (#792) (09-25), felix86 commit: Unaligned lock inc/dec dword (#798) (09-27)

felix86, the binary translation project for running x86/x86-64 games on RISC-V Linux, merged 8 more commits in this window (#792–#798 plus one instruction latency table update), continuing the dense pace since mid-September: new SHA extension and VMCALL instruction implementations, expanded Wayland thunks, self-modifying code (SMC) support enabled for helper read-modify-write functions, faulting on non-executable page access, unaligned lock inc/dec dword handling, and code deduplication. The previous issue (09-25) covered four commits, #788–#791, bringing the total to over a dozen within a week.

1.4 Open-Source Ecosystem Shorts: rv32emu Refines Linux Image Build, openRuyi Sees No New Additions Across Both Sources

Date: 2026-09-27　Source: rv32emu commit: ext4 rootfs disk and CI prebuild (#786) (09-27), openRuyi official news page (checked 09-27), openRuyi main repository (checked 09-27)

  • Linux support in the teaching-oriented RV32 emulator rv32emu continues to improve: make build-linux-image now directly generates an ext4 rootfs disk (#786), and CI now prebuilds and stores it in the rv32emu-prebuilt repository, simplifying the Linux guest boot process.
  • openRuyi dual-source check: no new announcements on the official news page (the 2026.09 release is still unpublished; the most recent release is 2026.08); no new commits in the GitHub main repository within the window (only CI-type repositories within the organization showed activity, not counted).

II. Product and Ecosystem Updates

2.1 ESP-Mosaico: Espressif ESP32-S31 Modular Development Kit Gets In-Depth Media Coverage

Date: 2026-09-27　Source: LinuxGizmos, “ESP-Mosaico centers dual-core RISC-V ESP32-S31 around a 2.16-inch square AMOLED” (09-27), Espressif official release (08-19), ESP-Mosaico official documentation

LinuxGizmos published an in-depth article on Espressif’s ESP-Mosaico — a scalable intelligent interaction development kit for AI Coding (code agents) (officially released 08-19; this issue adds foreign media details): powered by the ESP32-S31NRV16 (dual-core 32-bit RISC-V @320MHz, 16MB on-chip PSRAM), equipped with a 2.16-inch 480×480 square AMOLED touchscreen, audio codec and amplifier, six-axis IMU, dual magnetometers, SPI NAND and haptic feedback, with two 2×10P module interfaces on the left and right supporting magnetic snap-together expansion. On the software side, it offers two paths — Chat Coding / Vibe Coding (with the built-in ESP-Claw on-device Agent) — alongside BSP and esp-mosaico example projects. Echoing the ESP32-S31 Linux porting progress covered in the previous issue, Espressif is advancing the S31 from chip to a “kit + framework” productization stage.

2.2 LILYGO T-Dongle-C5: ESP32-C5 Dual-Band Wi-Fi 6 USB Dongle Gets Comprehensive Coverage

Date: 2026-09-27　Source: CNX Software, “LILYGO T-Dongle-C5 – An ESP32-C5 USB dongle with microSD card slot, optional 0.96-inch OLED” (09-27)

CNX Software published an overview of the now fully available LILYGO T-Dongle-C5 (successor to the ESP32-S3-based T-Dongle-S3): powered by the ESP32-C5HR8 (single-core RISC-V @240MHz plus a 40MHz low-power core), supporting dual-band Wi-Fi 6, BLE 5.0 and 802.15.4 (Zigbee/Thread), 16MB flash / 8MB PSRAM, USB-A plug-in form factor, with optional 0.96-inch IPS display, microSD card slot and Qwiic expansion; priced from $13.02 in the official store. Community ports such as ESP32 Marauder penetration testing firmware have already appeared, indicating rising ecosystem activity. The ESP32-C5 belongs to Espressif’s RISC-V product line (the previous S3 generation was Xtensa), making this iteration significant in both experience and form factor.

2.3 Russia’s K1921VG10Ya: Dual-Core RISC-V MCU Repackaged in 13×13mm BGA

Date: 2026-09-25　Source: kit-e.ru, “Микроконтроллер К1921ВГ10Я в корпусе BGA” (09-25), mforum.ru: K1921VG1T repackaging report (09-24)

Russia’s GS Nanotech and НИИЭТ (Research Institute of Electronic Technology) have completed pilot-batch packaging of a small-package version (K1921VG10Ya) of the dual-core RISC-V microcontroller K1921VG1T: switching from LQFP-208 (28×28mm) to BGA216 (13×13mm), reducing PCB footprint by up to roughly one-fifth, with chip specifications unchanged — dual-core RISC-V @204MHz, lockstep support, 4MB Flash, 1MB SRAM, integrated gigabit Ethernet PHY and hardware encryption (AES and the Russian standards “Кузнечик/Магма”), targeting industrial automation and embedded applications. The report states pilot yields are good, and both companies now have volume packaging capability. Packaging form factors for international RISC-V MCUs continue to diversify.

III. Deep Dive into Domestic Teams

3.1 Sophgo: 16 repositories pushed in a concentrated burst, 84x6 (CV84x6) new platform and 88a2 platform support land

Date: 2026-09-26 to 09-27　Source: sophgo/build commit: add 84x6 and 88a2 configs (09-26), sophgo/osdrv commit: add 84x6 support (09-26), sophgo/osdrv commit: 2D engine update (09-27), sophgo/bootloader-arm64 commit: 84x6 support (09-26), sophgo/sophon_media commit: 84x6 support (09-26), sophgo/libsophav commit: libsophav update (09-26)

The Sophgo GitHub organization saw concentrated pushes across 16 repositories during the window (mainly on the edge_dev development branch), centered on rolling out the software stack for the new platform codenamed 84x6 (CV84x6): the build repository added a full set of board-level configurations—an FPGA target (edge_84x6_fpga), a Palladium hardware emulation target (edge_84x6_palladium_c906, including the RISC-V-side device tree soph_base_riscv.dtsi, cv84x6_palladium_c906.dts, and hart1–4 memory mapping scripts), and an EVB production board target (edge_84x6_wevb_emmc, including the se13v1 series device tree and BGA board-level initialization); osdrv added 84x6 driver support (interdrv sequences, ISP/monitoring HAL, spacc, uapi definitions) and updated the 2D engine; bootloader-arm64, sophon_media, and libsophav (adding the vglite library) were adapted in sync. The same batch also added buildroot/fastboot and emulation configurations for the 88a2 platform (BM1688/CV186AH family).

The coexistence of three target types—FPGA, Palladium emulation, and EVB boards—indicates the new platform is in the software adaptation and validation stage (release timing subject to official disclosure). Combined with Sophgo’s routine pushes in the previous issue and the OrangePi O1 single-board news, its engineering cadence of “new chip—SDK first” is clear. Sophgo is an important member of the RISC-V ecosystem (SoCs such as the BM1688 integrate RISC-V coprocessors).

3.2 DAMO XuanTie: DAMO-RV-ATS test suite adds vector fixed-point and memory access tests

Date: 2026-09-25 to 09-27　Source: DAMO-RV-ATS commit: vector fixed-point instruction tests (#4) (09-25), DAMO-RV-ATS commit: vector memory access tests (#5) (09-27), DAMO-RV-ATS commit: README resource links (#3) (09-25)

DAMO XuanTie’s open-source RISC-V instruction compatibility verification framework DAMO-RV-ATS merged 3 PRs during the window: adding vector fixed-point instruction tests (averaging add/subtract variants vaadd/vaaddu/vasub/vasubu, etc., with a shared fixed-point test library) and a vector memory access test suite (a new memory access directory covering dozens of cases including vle-series loads, fault-only-first, segment memory access, strided and indexed addressing), plus bilingual READMEs and architecture-related resources. The suite targets 200 instruction cases across RVV 1.0, Zvbb, and Zvbc (per the README), for compatibility regression and automated randomized testing. This newsletter’s 09-15 issue mentioned this repository in XuanTie’s “specifications and testing” investment line; this is a substantive expansion of vector coverage, continuing its progressive pattern of “extension definition—test reinforcement.”

3.3 Espressif: 7 merges in esp-idf during the window, esp-hosted-linux repository continues to advance

Date: 2026-09-25　Source: esp-idf commit: mbedTLS fragmented handshake overflow fix (09-25), esp-idf commit: NimBLE over-limit binding LFU eviction (09-25), esp-idf commit: WPS registrar heap leak fix (09-25), esp-idf commit: lwIP NAPT IPv6 out-of-bounds fix (09-25), esp-hosted-linux commit: Linux 6.12+ build compatibility (09-25), esp-hosted-linux repository

esp-idf merged 7 items during the window, mainly focused on security and stability: fixing a buffer overflow in mbedTLS dynamic buffer fragmented handshake scenarios, an IPv6 out-of-bounds access in lwIP NAPT, and a per-call heap leak in the WPS registrar under softAP; NimBLE added an LFU (least frequently used) device eviction strategy when the number of bindings exceeds the limit; there were also HTTP server errno handling and CI expectation adjustments. On the engineering side, the esp-hosted-linux repository, newly opened on 09-02, advanced 3 commits within three days: Linux 6.12+ build compatibility and warning cleanup, integration and recovery path hardening, and tightened MR governance. These investments cover the entire chip lineup including the ESP32-C/S series RISC-V product lines.

IV. Embodied Intelligence and Robotics Special Chapter

4.1 Ruixin Gaoguang D35: official mass-production launch at the Digital Trade Expo, concentrated signings with companies across multiple sectors

Date: 2026-09-25　Source: Sohu · ZOL “World’s first RISC-V dataflow physical AI chip Gaoguang D35 officially enters mass production, debut at Digital Trade Expo draws attention” (09-26), Beijing Daily “Fifth Digital Trade Expo opens today, fully self-developed physical AI chip makes full-scenario debut in Hangzhou” (09-23)

On September 25, Suzhou Ruixin held the official mass-production launch of the Gaoguang D35 on the “debut first show” stage of the Fifth Global Digital Trade Expo: the chip is positioned on a dual self-developed path of “dataflow + RISC-V” (vendor claim: the world’s first RISC-V architecture dataflow physical AI chip), and on-site it signed ecosystem cooperation framework agreements with companies across multiple sectors including smart parks, smart transportation, healthcare, embodied intelligence, and digital technology, to jointly develop industry solutions. Chip highlights (vendor claims): fully self-developed high-performance RISC-V CPU core (IP has passed Intel’s global procurement system certification), up to 128GB high-speed video memory per chip, flexible Chiplet configuration, and a software stack supporting a CUDA-compatible compiler, Triton, and vLLM/SGLang, among others. This newsletter’s 09-21 to 09-24 issues continuously tracked its Digital Trade Expo exhibition and Qiyuan Robotics computing cooperation developments; this issue marks the milestone of mass-production launch and ecosystem signings.

Other robotics-side items: repositories such as SpacemiT’s spacemit-robotics saw no pushes during the window; inspections of member company websites found no substantive embodied intelligence-related updates.

V. Summary and Trend Observations

  • Capitalization sprint enters its final stretch: ESWIN Computing opens its IPO subscription from 09-28, targeting a listing on October 8—the “first RISC-V stock” moves from hearing narrative into issuance execution; pricing and subscription enthusiasm will provide a public-market reference for sector valuations, and are also a direct test of its “high revenue growth, narrowing losses” trajectory.
  • Software stacks lead the way for new domestic hardware platforms: Sophgo’s CV84x6 rolls out across 16 repositories (including FPGA/Palladium emulation and RISC-V C906-side configurations), while Espressif’s S31 advances on two fronts from the kit (ESP-Mosaico) to the Linux host side (esp-hosted-linux, buildroot)—”building the software stack ahead of the new platform” is now a shared cadence among domestic vendors.
  • XiangShan-family cache and prefetch work is the weekend development focus: 31 GEM5 experiments over two days (BDP stream depth control, H2P admission and lifecycle) combined with XiangShan feat-pdb gating and XSCache Oceanus fixes—the cache/prefetch subsystem remains the performance battleground for Kunminghu v3.
  • Ecosystem foundations thicken: DAMO XuanTie’s DAMO-RV-ATS expands vector fixed-point and memory access tests, felix86 polishes its compatibility layer with over a dozen commits in a week, and rv32emu improves Linux image builds—investment continues on both the “verification” and “compatibility” ends.
  • To watch: openRuyi 2026.09 release still not out; Nuclei, SpacemiT, Sophgo, revyos, Radxa Linkr, ESWIN Computing and others saw no pushes on the GitHub side during the window; member website inspections show no substantive developments. Next issue focus: ESWIN pricing and the October 8 listing, Sophgo 84x6 official disclosure, the openRuyi monthly release, and XiangShan prefetch line merge developments.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Hacker News RISC-V-related hits within the window were popularity discussions of repos such as felix86; no major news
Google News aggregation (multiple Chinese and English queries) English side hit Eswin IPO (SCMP), ESP-Mosaico (LinuxGizmos), Russian-media MCU, etc.; Chinese side hit Global Digital Trade Expo / Ruixin signing and robotics-related pieces (some April old articles excluded); gambling and stock-market-style headlines excluded wholesale by semantics
English media (SCMP / The Standard / ChipNews / LinuxGizmos / CNX / kit-e.ru) Hit and included: Eswin prospectus, ESP-Mosaico, T-Dongle-C5, K1921VG10Ya package
GitHub organizations and key repositories Pushes within the window: XUANTIE-RV 1 (damo-rv-ats), sophgo 16, espressif 30, XiangShan family 4 (XiangShan feat-pdb / GEM5 three branches / NEMU r18 / XSCache 4 commits; difftest main branch had no commits within the window); eswincomputing, Nuclei-Software, spacemit-com, spacemit-robotics, sipeed, revyos, openhwgroup, radxa-linkr all 0
RISC-V International official website and blog No new announcements within the window
openRuyi dual sources No new announcements on the official news page (2026.09 release still not published); no new commits in the main repository within the window
Member company website sweep Swept 391 companies: 40 pages had updates, all marketing / rolling content with no substantive developments; 69 failed to fetch (including some domestic sites), which does not affect the conclusion
CNX / LinuxGizmos / Phoronix RSS Hit ESP-Mosaico, T-Dongle-C5, etc. (already included); Phoronix hit Redox OS monthly progress (not directly related to RISC-V, not included)