RISC-V Daily Intelligence Report (2026-09-08)
Research Window: Past 24 hours (2026-09-07 08:18 ~ 2026-09-08 08:18, Beijing Time) Sources: HN, Google News aggregation, ServeTheHome, CNX Software, LinuxGizmos, Phoronix, GitHub API (org repo pushed and commit search), domestic tech media, etc. (see appendix source verification table for details)
Issue Index
- I. Open Source Community and Software Ecosystem
- Canonical details enterprise-grade open source RISC-V software readiness: Ubuntu riscv64 package pass rate 55.1% (09-07)
- XiangShan: New vector backend vfma pipeline refactoring and wide instruction support batch landed (09-07)
- CVA6: Fix scope expanded to RV32/64 instruction legality, virtualization and memory protection continue to be refined (09-07~08)
- II. Product and Ecosystem Updates
- YuzukiHD open-sources YuzukiNeko: Allwinner F101 (DAMO XuanTie C907) Pico-sized Linux board (09-08)
- III. Domestic Team Updates and Deep Dives
- DAMO XuanTie XUANTIE-RV: priv-ATS adds Hypervisor tests, XTheadCmo spec tightens dcache operation scope (09-07)
- Comprehensive window observation: Sophgo/SpacemiT/Sipeed routine iterations, news side domestic teams overall quiet (09-07/08)
- IV. Embodied Intelligence and Robotics Special Chapter
- Window observation: No new updates, 09-09 Shenzhen IICIE Embodied Intelligence Industry Conference opens tomorrow (09-07/08)
- V. Summary and Trend Observations
- Appendix: Quiet Day Source Verification Table and Complete Source List
I. Open-Source Community and Software Ecosystem
1.1 Canonical Details Enterprise Open-Source RISC-V Software Readiness: Ubuntu riscv64 Package Pass Rate at 55.1% (09-07)
Date: 2026-09-07 (published by ServeTheHome on Monday, in-window at 09-08 01:00 Beijing time) Source: ServeTheHome
ServeTheHome follows up with a transcript of a Hot Chips 2026 talk: Canonical Silicon Valley Director of Partnerships Gordan Markus systematically explained Ubuntu’s multi-architecture build mechanism and the path to enterprise-grade RISC-V readiness, and provided quantitative gap data — in the Ubuntu 26.10 test snapshot, 3,443 riscv64 packages were accepted for testing and 1,898 passed, a pass rate of about 55.1%, far below amd64’s roughly 92%. Canonical attributes part of the gap to emulated build and test targets (execution times stretched from hours to days), and has introduced native RISC-V build machines, with partners providing server-class RVA23 platform support. On the open-source collaboration side: Canonical participates in RISC-V International’s RISE project (commercial software readiness for mobile, consumer electronics, data center, and automotive), and its Ubuntu 24.04 native RISC-V runners power build and board farms hosted on Scaleway Elastic Metal, using hardware from Alibaba and SpacemiT, having accumulated 116 organizations, 24,000 tasks, and 700,000 build minutes. Canonical’s core judgment is that RVA23-style profiles make software targets predictable, and that large-scale upstream collaboration can bridge the historical “software readiness gap” that slows open-source adoption of new ISAs; as server-class RVA23 hardware arrives over the next two years, the software stack will have a fixed convergence target. This is the most data-valuable item in the window on the enterprise RISC-V software ecosystem.
1.2 XiangShan: New Vector Backend vfma Path Refactor and Wide Instruction Support Batch Landed (09-07)
Date: 2026-09-07 (16:19–17:33 Beijing time batch) Source: GitHub openxiangshan/XiangShan commits
The vector backend refactor of the XiangShan open-source high-performance core (Kunminghu) continues: the 09-07 afternoon batch merged feat(vfma) “support vfma in new vector backend”, feat(vector, vfmac) refactoring pipeline registers and supporting widen instructions, and fix(vector) initializing vfma pipe metadata, marking the new vector backend execution path’s extension from whole-register moves (yesterday’s batch) to floating-point multiply-add (vfma/vfmac) and widening operations; the same batch also includes bypass readiness and non-register source fixes, LoadQueueReplay unaligned head delayed wakeup handling, ROD encoding alignment fix (#6509), and addition of VFREC7_V/VFRSQRT7_V to the FFlagsWen table. Combined with the vialu/mgu connections and vector wide/narrow instruction support of the past few days, it can be judged that the XiangShan vector execution subsystem refactor is advancing in the order of “instruction functionality completion — path dataflow fixes — floating-point matrix operation integration”, with engineering maturity continuing to improve; no version release in this window.
1.3 CVA6: Fix Scope Expands to RV32/64 Instruction Legality, Virtualization and Memory Protection Continue to Be Refined (09-07~08)
Date: 2026-09-07 20:18 ~ 09-08 05:36 (Beijing time, 9 commits) Source: GitHub openhwgroup/cva6 commits
OpenHW Group’s application-class open-source core CVA6 continued to merge fixes in batches within the window, with coverage further expanding from yesterday: a new dimension of instruction semantic legality was added — zip/unzip are legal only in RV32 and should decode as illegal in RV64 (#3527), rejection of illegal use of RV64-only FCVT on RV32 (#3540), and legalization of the reserved value 2’b10 for mstatus.MPP when RVH=1; the virtualization and memory protection paths continue yesterday’s themes — ptw fix that the HLVX rule does not apply to G-stage checks of VS-stage PTE reads, and PMPADDR63 out-of-bounds access fix (#3485); additionally, a misaligned branch regression test when the C extension is disabled (#3424), a false 4 KiB alias regression test (#3453), and a debug loop shared-pointer out-of-bounds fix. With more than 15 commits combined over two consecutive days, the refinement of virtualization two-stage address translation and the PMP security path has entered a high-frequency period, which can serve as an observation signal for the quality-maintenance cadence of RISC-V open-source application cores.
II. Product and Ecosystem Developments
2.1 YuzukiHD Open-Sources YuzukiNeko: Allwinner F101 (DAMO XuanTie C907) Pico-Sized Linux Board (09-08)
Date: 2026-09-08 Source: CNX Software, YuzukiHD/YuzukiNeko GitHub
Open-source hardware team YuzukiHD released a new board, the YuzukiNeko: a Raspberry Pi Pico-sized (about 51 x 21 mm) Linux single-board computer, powered by Allwinner’s new SoC, the Allwinner F101 “smart control and display processor”. The F101 uses a single-core DAMO XuanTie C907 RISC-V core (1.008 GHz, 32 KB I-cache + 16 KB D-cache), in a QFN-68 package, with SiP-integrated 8 MB (F101S2) or 16 MB (F101S3) PSRAM (252 MHz), an integrated display engine (RGB888 720p, single-link LVDS 1366x768, 4-lane MIPI DSI 1280x800), large-size JPEG/PNG decoding, USB 2.0 DRD, and 512-bit eFuse. Onboard are 128 Mbit SPI NOR + microSD, USB-C (data/power/flashing), dual 20-pin GPIO expansion headers, and a FEL button. On the software side, YuzukiHD has open-sourced on GitHub the schematic, EasyEDA project, Gerber, 3D STEP, and BOM, and provides a sun252i_f101 branch based on mainline Linux 7.2, a Buildroot external tree, and Zephyr RTOS support (Linux and Zephyr dual systems). A Whycan forum post says the F101 SoC unit price is about 18 RMB (about 2.7 USD), and the community expects the full board to sell for under 10 USD. The board is not yet on sale. Significance: following the D1 series (C906), the DAMO XuanTie C907 has once again gained large-scale low-cost adoption by a domestic SoC, and the ultra-low-cost “Linux/Zephyr dual-system” RISC-V micro-board ecosystem is expected to expand further.
III. Domestic Team Updates and Deep Dive
3.1 DAMO XuanTie XUANTIE-RV: priv-ATS Adds Hypervisor Tests, XTheadCmo Spec Tightens dcache Operation Scope (09-07)
Date: 2026-09-07 (14:29–22:55 Beijing Time) Source: XUANTIE-RV/damo-rv-priv-ats commits, XUANTIE-RV/thead-extension-spec commits
DAMO XuanTie’s public repositories resumed iteration after Monday’s silence, with 4 commits across two repositories in the window: the privileged architecture repository damo-rv-priv-ats merged “add Hypervisor_Za* tests” (#27) at 09-07 22:55, adding tests for atomic-class instructions (Za* series) in hypervisor mode; the extension spec repository thead-extension-spec merged PR #77 (XTheadCmo extension) at 14:29–14:48: tightening the scope of clean set/way operations and the th.dcache.isw instruction to L1 D-cache, clarifying that this cache management operation extension applies only to L1 semantics. Both updates are of the nature of spec refinement and test reinforcement, following the routine rhythm of “extension definition—test verification,” with no new product-level signals. Note also: overseas media on 09-07 still carried reprints from outlets such as Geeky Gadgets of “C950 runs Qwen 3.8 without GPU” (headline tagged Reportedly), which upon verification is a late echo of the 08-18 Day 0 adaptation announcement (already covered in detail in this report’s 08-19/20 editions), not a new event, and is not listed as a separate item.
3.2 Comprehensive Window Observation: Sophgo/SpacemiT/Sipeed Routine Iterations, Domestic Teams Overall Silent on the News Side (09-07/08)
Date: 2026-09-07/08 Source: sophgo/zsbl, spacemit-com/docs-chip, sipeed/NanoKVM-Pro, spacemit-com/linux, spacemit-com/onnxruntime and other commits APIs
Domestic teams on the GitHub side generally resumed routine iterations on Tuesday, all being regular development with no release-level updates: Sophgo’s zsbl zero-stage boot tool merged xmodem commands, console speed setting commands, console display dot repositioning, and a libc strncpy zero-padding fix at 09-07 16:13–19:47, constituting boot debugging toolchain polish; SpacemiT’s docs-chip updated the K3 UART register base address description and revision history at 17:17–17:50, and fixed internal anchors in P3 documentation (pure documentation maintenance), while the linux and onnxruntime repositories showed pushed signals but no new commits on the default branch within the window (suspected to be non-default branch/tag pushes, not further investigated); Sipeed’s NanoKVM-Pro merged a virtual keyboard crash fix (#148), a Flask-SocketIO upgrade to 5.6.1, and custom update source/manual update functionality (#145) at 18:07–19:29, as the KVM-over-IP product software continues to evolve. News-side verification: Chinese queries for “XuanTie/DAMO/Sophgo/SpacemiT/Nuclei/XiangShan” mostly returned semantic noise (Xiaomi’s “XRING” chip being a different brand, Sophgo matching “computing-power coordination” green computing finance articles, Nuclei matching Cantonese chip/Huawei and other generic “chip” content) or out-of-window old news (SpacemiT only having the AGIC conclusion on 09-03 already reported); the “Nuclei” topic’s 09-04 Electronic Engineering Album article “Robot Duck sells out, Rockchip hits limit-up” is an already-reported echo. Conclusion: no new increment on the news side for domestic teams, with substantive updates still primarily GitHub commits.
IV. Embodied Intelligence and Robotics Special Chapter
4.1 Window Observation: No New Updates, Shenzhen IICIE Embodied Intelligence Industry Conference Opens Tomorrow on 09-09 (09-07/08)
Date: 2026-09-07/08
This window saw no new product releases or major events in the RISC-V embodied intelligence/robotics direction. Supplementary queries for “embodied intelligence RISC-V when:7d” returned only out-of-window previews and general industry content (09-02 Electronic Engineering Album Shenzhen three-exhibition linkage preview, 09-05 Fudan MBA Zhangjiang Robot Valley visit, etc.), with no substantive new items. Observation points remain unchanged: starting 09-09, the Shenzhen IICIE International Integrated Circuit Innovation Expo opens (Hall 14 RISC-V Industry Ecosystem Innovation Conference, Hall 15 2026 Embodied Intelligence Industry Conference), combined with the smart car x embodied robotics three-exhibition linkage (09-09–11), with DAMO XuanTie/Sophgo/SpacemiT and others exhibiting, entering the fulfillment observation window for domestic RISC-V x embodied developments starting tomorrow.
V. Summary and Trend Observations
This report window is a regular active day (not a quiet day): on the open-source community side, one enterprise-level readiness quantification report plus continuous commits from two open-source cores; on the product side, one hardware item on low-cost adoption of a XuanTie core; domestic teams resumed GitHub iterations while the news side was silent. Key points summarized as follows:
First, enterprise-level software readiness has entered a “quantifiable acceptance” phase. Canonical’s Hot Chips supplementary talk publicly disclosed a quantified gap of 55.1% riscv64 package pass rate versus 92% for amd64, explicitly attributing the cause to emulated build bottlenecks, with the solution being native build machines plus RVA23 profile convergence—the RISC-V server software narrative is shifting from “it runs” to “it’s acceptable,” and the existence of the RISE project and a 24,000-task-level build farm indicates upstream investment has reached scale.
Second, the main theme of open-source core refactoring continues. XiangShan’s new vector backend advanced from whole-register moves (09-06) to vfma/vfmac floating-point multiply-add and widen instructions (09-07), with a clear rhythm of functional completion in the execution path; CVA6 saw 15+ fixes for two consecutive days, with coverage expanding from virtualization/PMP to RV32/64 instruction legality, making multi-architecture semantic correctness polish a new highlight.
Third, the DAMO XuanTie ecosystem is expanding in both directions—”reaching up and sinking down.” On the reaching-up end, the August announcement of C950 running Qwen 3.8 without GPU is still forming late echoes in overseas media, indicating the narrative dissemination cycle has not ended; on the sinking-down end, the C907 has entered the 18 RMB-level Allwinner F101 SoC, combined with YuzukiHD’s open-source board and Linux/Zephyr dual-system support, as XuanTie core licensing continues to expand its coverage in the ultra-low-cost micro-board market.
Fourth, forward-looking window: the Shenzhen IICIE opens on 09-09, alongside the RISC-V Industry Ecosystem Innovation Conference and the Embodied Intelligence Industry Conference (Halls 14/15), combined with the three-exhibition linkage of smart cars and robotics themes; domestic RISC-V developments are expected to clearly pick up in the middle of this week, and tomorrow’s report will follow up with focus.
Limitations note: Under the GitHub unauthenticated API rate limit (60 req/h), org verification sampled recently active repositories sorted by pushed_at; spacemit-com non-default branch pushes and commits from low-activity repositories may be missed; commit content for XiangShan/CVA6 and various vendors was judged only by commit message titles, without verifying code details one by one; Canonical’s pass rate and build farm data are quoted from the ServeTheHome talk transcript, without independent cross-verification against official Ubuntu data.
Appendix: Source Verification Table and Full Source List
| Source / Query | Verification Result |
|---|---|
| fetch_news.py comprehensive collection (HN, gnews, CNX/LinuxGizmos/Phoronix RSS, GitHub topic search, 24h window) | 11 candidates, 2 substantive items included (Canonical report, YuzukiNeko board). Excluded: Geeky Gadgets C950/Qwen series 08-18 official announcement echo; TSMC foundry share, MCU market forecast, Buterin Ethereum proof cost (crypto topics, RISC-V only a long-term hypothetical, and redistribution of old March articles) all lack direct event relevance to RISC-V; grain project x2 is a same-named non-RISC-V OS; open-bposit (new repo, 4 stars) below inclusion threshold; renode star changes not an event |
| HN | WerWolv/riscv-emulator “RISC-V Emulator and Linux System from Scratch” (rv32ima emulator booting Linux) is a 2026-04 created, 15-star old project repost, educational content, included in appendix not listed separately |
| Google News Chinese team queries (XuanTie chip/DAMO RISC-V/XiangShan processor/SpacemiT/Sophgo/Nuclei when:7d) | XuanTie matched Xiaomi “Xuanjie” (different chip brand, semantic noise); DAMO matched ttplus gambling SEO; XiangShan 0 hits; SpacemiT only 09-03 AGIC wrap-up (outside window, already reported); Sophgo matched “compute-power coordination” financial article and IICIE preview (reported yesterday); Nuclei matched CanSemi listing/Huawei Mate XT and other generic “chip” noise and ttplus gambling |
| Google News English queries (RISC-V when:1d/2d, SiFive/Milk-V/StarFive/RISC-V Summit when:3d/7d) | RISC-V when:1d total 3 items (Canonical included, C950 echo excluded, Buterin excluded); SiFive/Milk-V/StarFive/RISC-V Summit all 0 hits |
| GitHub org pushed check (XUANTIE-RV/sophgo/spacemit-com/Nuclei-Software/sipeed/eswincomputing) | XUANTIE-RV (priv-ATS/thead-extension-spec, included 3.1), sophgo (zsbl, included 3.2), spacemit-com (docs-chip, included 3.2; linux/onnxruntime pushed but no in-window commits on default branch), sipeed (NanoKVM-Pro, included 3.2); Nuclei-Software silent after 09-04; eswincomputing long silent since 07-14 |
| GitHub commits check (XiangShan/CVA6/OpenSBI) | XiangShan 09-07 vector backend vfma batch included (1.2); CVA6 09-07 20:18~09-08 05:36 batch included (1.3); OpenSBI no commits in window (latest 09-05) |
Full Source List: Hacker News, Google News RSS aggregation, ServeTheHome, CNX Software, LinuxGizmos, Phoronix, GitHub API (orgs repos / commits), EE Times China and other domestic tech media, vendor official websites.
This report is automatically generated by the Hermes daily scheduled task. The report opens with a traditional index; body items are organized by open-source community and software ecosystem, product and ecosystem developments, domestic team developments and deep dives, and a dedicated embodied intelligence and robotics chapter.