Research window: Past 24 hours (2026-09-05 08:18 ~ 2026-09-06 08:18, Beijing Time) Sources: HN, Google News aggregation, Phoronix, CNX Software, LinuxGizmos, GitHub API (org repo pushed and commit search), domestic tech media reports, etc. (see appendix: quiet-day source verification table for details)

Issue Index

  • I. Open-Source Community and Software Ecosystem
    • Trend Retrospective: GCC 17 native -mcpu/-mtune=native support merged into RISC-V (09-03)
    • Trend Retrospective: PoCL 7.2 achieves official OpenCL 3.0 conformance, covering RISC-V (09-04)
    • Trend Retrospective: XiangShan Kunminghu main repo and XSAI vector/AI branches continue iterating (09-02~04)
    • Window Observation: OpenSBI routine development commits, no version release (09-03~05)
  • II. Product and Ecosystem Developments
    • Trend Retrospective: SiFive: first batch of RVA23 server chips to land within the year, standards system detailed (09-03/04)
    • Trend Retrospective: BigSky CUDA-on-RISC-V media echo continues (09-03/04)
    • Trend Retrospective: XenoSpectrum: the gap between China’s 74% x86 server market and policy bets (09-04)
    • Window Observation: ESP32-S31 media echo deduplication note (09-05)
    • Forward-Looking Item: Shenzhen IICIE opens 09-09, with the RISC-V Industry Ecosystem Innovation Conference and Embodied Intelligence Industry Conference held concurrently (released 09-03)
  • III. Domestic Team Developments and Deep Dives
    • Trend Retrospective: Lingrui Zhixin P100: China’s first dynamic SMT4 server-class RISC-V core (09-02, echo continues through 09-05)
    • Trend Retrospective: Zhongke Haoxin completes Series B funding (09-03/04, Dealroom English echo 09-05)
    • Window Observation: Comprehensive weekend check of domestic teams’ GitHub: overall quiet (09-05/06)
  • IV. Embodied Intelligence and Robotics Special Chapter
    • Trend Retrospective: Humanoid robot computing moves toward a “centralized + distributed” hybrid architecture (09-03)
    • Window Observation: No major new developments; RISC-V embodied narrative carried by the funding side (09-05/06)
  • V. Summary and Trend Observations
  • Appendix: Quiet-Day Source Verification Table and Complete Source List

Statement of No Major News Today

Within this research window (2026-09-05 08:18 ~ 2026-09-06 08:18 Beijing Time, covering Saturday afternoon to Sunday morning), no major RISC-V news meeting inclusion criteria was found: the comprehensive collection by fetch_news.py yielded only 1 candidate, which upon verification was a media echo of old ESP32-S31 news (already reported in detail yesterday) and was excluded; multiple sets of Chinese team queries and English vendor queries, as well as checks of domestic teams’ GitHub organization activity, showed no new substantive developments within the window. Following the quiet-day handling approach, this report is presented as “three-day trend retrospective + window observation + source verification table.”

I. Open-Source Community and Software Ecosystem

1.1 Trend Retrospective: GCC 17 Native -mcpu/-mtune=native Support Merged for RISC-V (09-03)

Date: 2026-09-03　Source: Phoronix

A significant milestone on the RISC-V toolchain side: GCC 17 now supports -mtune=native/-mcpu=native on RISC-V targets, allowing the compiler to automatically detect host processor features and generate more optimized code, giving the RISC-V platform a native compilation experience on par with x86/AArch64. This item was covered in detail in the 09-04 report; here it is only a trend retrospective over the past three days and will not be expanded upon again.

1.2 Trend Retrospective: PoCL 7.2 Achieves Official OpenCL 3.0 Conformance, Covering RISC-V (09-04)

Date: 2026-09-04　Source: Phoronix

The portable computing language project PoCL 7.2 has become a Khronos-certified official OpenCL 3.0 conformant implementation, covering RISC-V (RV64GC and RVA22) and x86_64 — the first time an open parallel computing standard has received official conformance endorsement on general-purpose RISC-V processors. This was covered in detail in the 09-05 report; the trend retrospective is omitted here.

1.3 Trend Retrospective: XiangShan Kunminghu Main Repository and XSAI Vector/AI Branches Continue Iterating (09-02~04)

Date: 2026-09-02~04　Source: GitHub openxiangshan/XiangShan commits, openxiangshan/XSAI

Over the past three days, the XiangShan open-source high-performance core has maintained a high pace of iteration: on 09-02, the main repository saw 10+ commits in a single day, with intensive fixes for vector instruction exception handling; on 09-03/04, vector and floating-point unit refactoring advanced, and the XSAI AI branch continued syncing with upstream. The engineering progress of the open-source core along both the vector extension and AI feature lines is the most stable active signal in the open-source community over the past three days.

1.4 Window Observation: OpenSBI Routine Development Commits, No Version Release (09-03~05)

Date: 2026-09-03~05　Source: GitHub riscv-software-src/opensbi commits

During the window, riscv-software-src/opensbi had routine development commits: sbi_pmu counter/event error codes aligned with the SBI v3.0 specification, raw event matching fixes, scounteren time emulation, FP state save fixes, and sbi_domain code renaming, among others — all part of the daily maintenance rhythm, with no version release (the latest official version remains v1.9 from 2026-07-01). This can be seen as an observation signal of the firmware layer continuously converging toward the SBI v3.0 specification.

II. Product and Ecosystem Updates

2.1 Trend Retrospective: SiFive: First Batch of RVA23 Server Chips to Land Within the Year (09-03/04)

Date: 2026-09-03/04　Source: ServeTheHome

ServeTheHome and SiFive’s official blog successively posted follow-up transcripts of the Hot Chips 2026 talk: SiFive stated that the first batch of RVA23 server chips will land this year, with standards work now translating into real hardware; the server platform specification (RVA23 + AIA interrupts + UEFI/ACPI + MCTP/Redfish management) is advancing in parallel. This was covered in detail in the 09-03/04 report; here it is a trend retrospective.

2.2 Trend Retrospective: BigSky CUDA-on-RISC-V Media Echo Continues (09-03/04)

Date: 2026-09-03/04　Source: igor’sLAB (German media, English edition)

Coverage of the SiFive BigSky RISC-V server (capable of running CUDA on NVIDIA GPUs) continues as a media echo: the industry positions it as a “porting validation platform,” with NVLink Fusion chips landing no earlier than 2027. This was included as a trend item in the 09-04 report and is omitted here.

2.3 Trend Retrospective: XenoSpectrum: The Gap Between China’s 74% x86 Server Market and Policy Bets (09-04)

Date: 2026-09-04　Source: XenoSpectrum (translated from the original Japanese)

A Japanese outlet analyzes China’s RISC-V server strategy from market data and policy logic: roughly 74% of the market is still held by x86, creating a gap with the perception that “RISC-V is already widespread”; Beijing is making a combined bet through Xinchuang catalogs, state-owned cloud, and procurement subsidies. The piece offers a demystifying perspective on “China RISC-V policy hype” coverage. It was covered in detail in the 09-05 report; the trend retrospective is omitted here.

2.4 Window Observation: ESP32-S31 Media Echo Deduplication Note (09-05)

Date: 2026-09-05　Source: inews.zoombangla.com (Google News aggregated repost)

The only candidate for fetch_news.py in this window was a 09-05 19:17 repost on the zoombangla site of “Espressif ESP32-S31 DevKit Brings Wi-Fi 6 and Thread to a 320MHz RISC-V Board” (same source and same title as the 09-04 Geeky Gadgets report). Upon verification: neither the CNX Software main feed nor Espressif’s official channels had any new ESP32-S31 developments within the window (CNX’s recent posts were only ESP32-S3/P4/C3-type project posts, among which S3/P4 use Xtensa cores and thus fall outside RISC-V coverage to begin with). The product details and hands-on review of the ESP32-S31 dual-core RISC-V 320MHz + Wi-Fi 6 were already covered in detail in section 3.2 of the 09-05 report; this item is a media echo, excluded under the deduplication criteria and not included as a new item.

2.5 Forward-Looking Item: IICIE Opens in Shenzhen on 09-09, with the RISC-V Industry Ecosystem Innovation Conference and the Embodied Intelligence Industry Conference Held Concurrently

Date: Published 2026-09-03 (exhibition opens 09-09, forward-looking outside this window)　Source: Sohu/Shande News, IICIE official conference list

The 2026 IICIE International Integrated Circuit Innovation Expo (IC Innovation Expo) will be held from 09-09 to 11 at the Shenzhen World Exhibition & Convention Center (Bao’an), concurrently and at the same venue as CIOE and elexcon Shenzhen Electronics. The chip design exhibitor lineup includes RISC-V-related companies such as DAMO XuanTie, Sophgo, SpacemiT, C*Core Technology, and Liuyue Microelectronics; among the accompanying conferences, a “2026 RISC-V Industry Ecosystem Innovation Conference” (free) will be held in Hall 14 on the afternoon of 09-09, while Hall 15 will concurrently host the “2026 Embodied Intelligence Industry Conference — From Compute to Execution, Building Embodied Intelligence Systems.” For readers following the intersection of the RISC-V ecosystem and embodied intelligence, this is the first window next week to observe domestic vendors’ product and ecosystem announcements; this report flags it in advance, with developments to be verified after the event.

III. Domestic Team Updates and Deep Dive

3.1 Trend Retrospective: Lingrui Zhixin P100: China’s First Dynamic SMT4 Server-Class RISC-V Core (09-02, Echoes Through 09-05)

Date: 2026-09-02 (reposts still echoing on 09-04/05)　Source: Guancha Interview, Sina Tech reposting Kuaikeji 09-04

The Lingrui Zhixin P100 core has continued to dominate domestic RISC-V server narratives: China’s first commercialized dynamic SMT4 (real-time switching of 1–4 threads per core under load) server-class RISC-V core, with a 20+ stage out-of-order pipeline, 8-decode/10-issue, and a P100-based test chip that taped out on a domestic advanced process line in mid-to-late August (roughly three months from April kickoff to tape-out). Biren Technology participated in its Pre-A round and jointly optimizes CPU+GPU compute scheduling; a 128-core server CPU is planned for tape-out in 2027. Technical details were covered in depth in the 09-03 report; the 09-04/05 reposts by Sina, Kuaikeji, etc. are echoes (including execution-progress phrasing such as “three-month tape-out”) and were deduplicated out of this window, retained only in the trend.

3.2 Trend Retrospective: Zhongke Haoxin Completes Series B Financing (09-03/04, Dealroom English Echo 09-05)

Date: 2026-09-03/04 (English echo 09-05)　Source: STAR Market Daily (reposted via East Money), PEdaily, Dealroom

Zhongke Haoxin (a technology transfer from the Chinese Academy of Sciences Institute of Automation, a specialized RISC-V DSP supplier) completed a Series B round led by Yuehu Capital, with proceeds directed toward AI edge chips and industry-customized solutions covering smart appliances, industrial control, new energy, and embodied intelligence. This was reported in detail in the 09-05 report; Dealroom’s English brief published at 00:45 UTC on 09-05 is an echo of the same event and was removed.

3.3 Window Observation: Comprehensive Weekend GitHub Check of Domestic Teams: Broadly Quiet (09-05/06)

Date: 2026-09-05/06　Source: org repos APIs (sort=pushed) for XUANTIE-RV, eswincomputing, sophgo, Nuclei-Software, spacemit-com, sipeed, revyos, riscv-software-src, etc.

A pushed check was run on the GitHub organizations of six core domestic teams: DAMO XuanTie (XUANTIE-RV, 72 repos), ESWIN Computing (eswincomputing), Sophgo (sophgo), Nuclei (Nuclei-Software), SpacemiT (spacemit-com), and Sipeed (sipeed). Within the window (from 09-05 08:18), all showed zero pushes — combined with 09-06 being Sunday, weekend quiet is as expected, with no new commits to mine. The only two exceptions: revyos (Sipeed’s distro org) made routine sync pushes on 09-05/06 to three upstream tracking repos — linux, u-boot, and opensbi (not independent development); and development commits to riscv-software-src/opensbi were already covered in 1.4. Conclusion: there were no substantive new developments on the domestic team side within the window, corroborating the news side.

IV. Embodied Intelligence and Robotics Special Chapter

4.1 Trend Retrospective: Humanoid Robot Compute Moving Toward a “Centralized + Distributed” Hybrid Architecture (09-03)

Date: 2026-09-03　Source: Semiconductor Engineering

Semiconductor Engineering analysis notes that humanoid robot compute is moving toward a “centralized + distributed” hybrid architecture, and that its safety complexity exceeds that of autonomous driving — the implication of this judgment for the RISC-V ecosystem being that the demand from distributed real-time control nodes and safety islands for an open, scalable instruction set is precisely the structural opportunity for RISC-V MCU/MPU in embodied scenarios. This was covered in detail in the 09-04 report; the trend retrospective is abbreviated.

4.2 Window Observation: No Major New Developments, RISC-V Embodied Narrative Carried by the Financing Side (09-05/06)

Date: 2026-09-05/06

There were no new product launches or major events in the embodied intelligence/robotics direction in this window. Over the past three days, the RISC-V narrative in this direction has mainly been carried by financing and product planning: Zhongke Haoxin’s Series B proceeds are explicitly directed toward industry-customized DSP solutions including embodied intelligence (09-03/04); the converged-computing domain-enhanced processor planned under Lingrui Zhixin’s P100 is also aimed at embodied intelligence and edge inference scenarios (09-02 report). The pace of new hardware products has paused for now, and the observation point can be shifted to next week’s industry exhibition window.

V. Summary and Trend Observations

This report window (Saturday afternoon to Sunday morning) is a typically quiet period: both the news side and the GitHub activity side were low, and the only candidate, upon verification, was an old-news echo of ESP32-S31, removed under the deduplication standard, leading to a determination of “no major news for the day.”

The main trend lines over the past three days (09-03 to 09-05) remain clear and can be summarized in four points. First, the open-source software stack has strong iterative momentum — GCC 17 native -mcpu/-mtune=native, PoCL 7.2 official OpenCL 3.0 conformance, continuous commits to the XiangShan main repo and XSAI, and OpenSBI converging toward the SBI v3.0 specification, with multi-layer progress across toolchains/firmware/open-source cores. Second, the narrative around server-class domestic RISC-V CPUs is heating up — the tape-out of Lingrui Zhixin’s P100 (dynamic SMT4) test chip, SiFive’s statement that its first batch of RVA23 server chips will land within the year, and XenoSpectrum’s demystifying analysis of the gap between the “74% x86” reality of China’s server market and policy bets all coexist. Third, capital continues to flow in — Zhongke Haoxin’s Series B and Lingrui Zhixin’s Pre-A (with Biren participating), with active financing across both the RISC-V DSP and server CPU tracks. Fourth, the embodied intelligence narrative is dominated by financing and architecture discussion, with new hardware products paused for now.

Follow-up observation points: on 09-09 (next Tuesday), the Shenzhen IICIE International Integrated Circuit Innovation Expo opens, with the “2026 RISC-V Industry Ecosystem Innovation Conference” and “2026 Embodied Intelligence Industry Conference” held concurrently, with DAMO XuanTie, Sophgo, SpacemiT, and others exhibiting (see the forward-looking item in 2.5), making it the first observation window for domestic RISC-V ecosystem developments next week; the RISC-V community has no major release announcements upcoming in the near term, and the pace is fairly routine.

Appendix: Slow-News-Day Source Verification Table and Full Source List

Source / Query Verification Result
fetch_news.py comprehensive collection (HN, gnews, CNX/LinuxGizmos/Phoronix RSS, GitHub topic search, 24h window) Only 1 candidate: ESP32-S31 zoombangla repost (09-05 19:17), already covered in detail yesterday, excluded
Google News Chinese team queries (XuanTie/XiangShan/SpacemiT/Sophgo/Nuclei/Espressif/ESWIN/DAMO when:7d) All noise or no relevant hits; Espressif only buyback/disclosure financial noise; DAMO no new RISC-V-related developments
Google News English vendor queries (SiFive when:3d, Andes/StarFive/Milk-V/SpacemiT/SOPHGO when:7d, RISC-V when:2d, RISC-V Summit when:7d) No new entries within window; hits are all echoes of 09-03/04 coverage (SiFive Hot Chips, PoCL 7.2, Haawking Dealroom, etc.)
GitHub org pushed check (XUANTIE-RV/eswincomputing/sophgo/Nuclei-Software/spacemit-com/sipeed/riscv-software-src/revyos) Zero pushes from the six domestic teams within window; revyos only routine upstream sync; riscv-software-src is routine OpenSBI development commits
Phoronix / CNX Software / LinuxGizmos RSS No new RISC-V hardware/software entries within window (CNX only has S3/P4/C3 project posts; S3/P4 are not RISC-V cores)
OpenSBI releases No new version (latest v1.9, 2026-07-01)
Lingrui Zhixin P100 follow-up reposts (Kuaikeji/Sina 09-04/05) Echoes of old news already covered in depth on 09-03, excluded
IICIE preview verification (Sohu/Shande Zixun + official semi-e.com conference list) Published 09-03, exhibition dates 09-09~11, includes “2026 RISC-V Industry Ecosystem Innovation Conference” and Embodied Intelligence Industry Conference, included as a 2.5 preview item

Source list: Hacker News, Google News RSS aggregation, Phoronix, ServeTheHome, CNX Software, LinuxGizmos, XenoSpectrum, Semiconductor Engineering, Guancha, Sina Tech/Kuaikeji, STAR Market Daily (East Money repost), PEdaily, Dealroom, Sohu (Shande Zixun), semi-e.com (IICIE official), GitHub API (orgs repos / commits), Espressif official site, various vendor official sites.

This report is automatically generated by the Hermes daily scheduled task. No major news within the research window; judged a slow news day, with the main text presented as a three-day trend retrospective + window observations.