RISC-V Daily Intelligence Report (2026-09-02)
Research window: Past 24 hours (2026-09-01 08:18 ~ 2026-09-02 08:18, Beijing Time) Sources: HN, Google News aggregation, CNX Software, ServeTheHome, Chips and Cheese, Evertiq, Bisinfotech, Electronic Design, GitHub API (org/repo commit search), etc. (see appendix for details)
In This Issue
- I. Open-Source Community and Software Ecosystem
- NVIDIA Publishes Explicit Requirements for Porting CUDA to RISC-V Host CPUs, SiFive Collaboration Demo Imminent (08-23 talk / 09-01 report)
- ab-riscv-interpreter 0.2: Rust Compile-Time Interpreter Passing RISC-V ACT Certification Tests (09-01)
- Raven-RiscV: RV32IMF Assembly Learning Simulator and IDE Draws Community Attention (09-02)
- II. Product and Ecosystem Updates
- Qualcomm Dragonwing Q-2390 / IQ-2390: ARM Main Core + RISC-V Real-Time Core Running Zephyr (09-01)
- GigaDevice Signs with Rutronik: GD32 (Including RISC-V-Based MCUs) Expands Distribution in EMEA and Southeast Asia (08-31 / 09-01)
- III. Domestic Team Updates and Deep Dives
- SpacemiT: K3 UEFI Firmware Fixed by External Developer, P3 Datasheet Online, AI Documentation Localized to English (09-01)
- Sophgo: sophon-tools Wraps Up CV84X6 memory_edit Fix (09-01)
- Sipeed: NanoKVM Optimizes H264 Video Stream Concurrency (09-01)
- IV. Embodied Intelligence and Robotics Special Section
- No Robotics-Specific News in Window; Notes on Trends and Opportunity Windows Over the Past 3 Days
- V. Summary and Trend Observations
- Appendix: Complete Source List
I. Open-Source Community and Software Ecosystem
1.1 NVIDIA Publishes Explicit Requirements for Porting CUDA to RISC-V Host CPUs, SiFive Collaboration Demo Imminent
Date: 2026-08-23 (Hot Chips 2026 tutorial talk) / 09-01 (in-depth coverage by ServeTheHome and Chips and Cheese) Source: ServeTheHome, Chips and Cheese (Chester Lam), Hot Chips 2026 agenda (NVIDIA official)
At the Sunday tutorial session of Hot Chips 2026 (Stanford, 08-23 to 08-25), Frans Sijstermans of NVIDIA gave a talk titled “RISC-V Profile and Platform for Interoperability With NVIDIA GPUs,” systematically disclosing the roadmap and requirements checklist for extending CUDA to RISC-V host CPUs. Key points:
- Current state of CUDA: A parallel computing platform since 2006, currently supporting only x86-64 and aarch64 on the host side; applications are split between CPU and GPU modules, and the host software stack is complex and heterogeneous.
- Hard requirements for RISC-V host CPUs: RVA23 profile; compliance with the RISC-V server SoC and server platform specifications (including baselines such as RAS and a dedicated security processor); ACPI (the UEFI Forum added RISC-V to ACPI 6.6 in 2025-05, and the RISC-V BRS boot and runtime services specification landed in 2025-08); PCIe hardware-level I/O coherence; PCIe peer-to-peer communication. NVIDIA emphasized that software binary compatibility is the core goal, avoiding the “lowest common denominator” problem (citing predicate support for vector extensions as an example).
- On the NVLink Fusion side: Custom CPUs (which can be RISC-V) connect to the NVIDIA AI platform via NVLink C2C (roughly 88 PCIe lanes, CHI coherence), with additional requirements for the DOCA and NCCL software stacks and deep collaboration with NVIDIA. SiFive was named as the RISC-V-side NVLink Fusion CPU partner, and plans to demonstrate a high-core-count server system running CUDA on-site at Hot Chips.
- Commentary: ServeTheHome argues that RISC-V is becoming a genuine third option in the server CPU market alongside x86 and Arm, but is still about two generations away from large-scale deployment; Chips and Cheese cautions that virtually all existing consumer-grade RISC-V hardware fails to meet the requirements (ACPI being the biggest shortfall), and that in the near term CUDA on RISC-V will only appear on enterprise-class server platforms. This is the most significant commercial endorsement signal for the RISC-V software ecosystem within the window.
1.2 ab-riscv-interpreter 0.2: A Rust Compile-Time Interpreter That Passes RISC-V ACT Certification Tests
Date: 2026-08-31 (blog post) / 09-01 (Hacker News hot thread) Source: Project Abundance blog, Hacker News, crates.io
Project Abundance released version 0.2 of ab-riscv-interpreter and ab-riscv-primitives. Features: fully modular and generic, panic-free, no_std with zero allocation, usable as a const fn for compile-time execution, implemented strictly to the RISC-V specification (targeting blockchain use), and passing the RISC-V Architectural Certification Tests (ACT). The decoder is split into its own crate for standalone use; instruction execution code is macro-generated (a single implementation expands to roughly 1,900 lines); CoreMark performance is about 1600 (compact match loop) / 2950 (indirect threading). The trade-off is a dependency on roughly 30 nightly Rust features (const generics, guaranteed tail calls, etc.). The author says the approach can be generalized to any RISC-V-like ISA (such as Parity’s PolkaVM). The blockchain/formal-verification-oriented RISC-V software stack gains yet another strict implementation option.
1.3 Raven-RiscV: An RV32IMF Assembly Learning Simulator and IDE Draws Community Attention
Date: 2026-09-02 (push within the window) Source: GitHub Gaok1/Raven-RiscV
Raven-RiscV, a RISC-V teaching simulator written in Rust, was updated within the window (09-02 00:01 UTC) and maintained community interest (111 stars): it supports RV32IMF, a step debugger, and cache and pipeline visualization, positioned as “a simulator + IDE for learning assembly.” The repository was created in 2025-03 and recently entered the trending range of RISC-V topic repositories as its features matured. Educational tools continue to fill out the RISC-V assembly introductory ecosystem, fitting well with coursework and competition scenarios.
II. Product and Ecosystem Updates
2.1 Qualcomm Dragonwing Q-2390 / IQ-2390: ARM Main Core + RISC-V Real-Time Core Running Zephyr
Date: 2026-09-01 Source: CNX Software, Qualcomm Newsroom
Qualcomm has launched the Dragonwing Q2 series of AIoT processors: the Q-2390 (commercial/consumer: retail, smart home, smart displays, enterprise edge devices) and the IQ-2390 (industrial: industrial automation, machine vision, building management, energy systems). The main compute cores are quad-core Cortex-A78/A55 (ARM), supporting Android, Yocto Linux, and Ubuntu; some models include a RISC-V real-time core, which supports the Zephyr RTOS. The SoM will be showcased at IFA 2026, with evaluation kits expected in Q1 2027. This is another instance of Qualcomm’s AIoT product line continuing the “ARM application core + RISC-V real-time/management co-core” combination, further cementing RISC-V’s role in edge devices; note, however, that the main compute is still handled by ARM.
2.2 GigaDevice Signs with Rutronik: GD32 (Including RISC-V-Based MCUs) Expands Distribution in EMEA and Southeast Asia
Date: 2026-08-31 (announcement) / 09-01 (Evertiq, Bisinfotech reports) Source: GigaDevice Newsroom, Evertiq, Bisinfotech
GigaDevice has entered a strategic franchise partnership with long-established German distributor Rutronik Elektronische Bauelemente, covering EMEA and Southeast Asia (including India). The partnership centers on the GD32 series of microcontrollers—the company explicitly states that this product family is based on a dual Arm Cortex-M and RISC-V architecture, spanning entry-level to high-performance real-time applications. Target markets: industrial, automotive, energy, communications, consumer electronics, and IoT. Rutronik reported revenue of approximately EUR 1 billion in fiscal 2025, serves over 40,000 customers, and has 80+ offices worldwide, making it an important addition to GigaDevice’s overseas channels. This marks another step in domestic RISC-V MCUs going global via European distribution networks.
III. Domestic Team Updates and Deep Dive
3.1 SpacemiT: K3 UEFI Firmware Fixed by External Developer, P3 Datasheet Online, AI Docs Translated to English
Date: 2026-09-01 Source: spacemit-com/edk2-platforms commits, spacemit-com/docs-chip commits, spacemit-com/docs-ai
Three SpacemiT (spacemit-com) repositories saw substantive updates during the window:
- edk2-platforms (UEFI firmware): Merged two K3 fix PRs from external contributor vhaudiquet — one addressing firmware networking issues and one addressing boot progress codes. This is among the first signals of external community developers directly participating in K3 UEFI firmware development, indicating that the K3 platform firmware ecosystem is beginning to open up to external contributions.
- docs-chip: Added the P3 chip datasheet (including a BUCK DVS reserved-bit correction), and continued advancing English translation of datasheet diagrams, filling in the English materials available to overseas developers.
- docs-ai: Synced English-language solution documentation.
Combined with yesterday’s RevyOS addition of new kernel configurations for K1/K3 (linuxboot, K3 DC/UFS), the SpacemiT K3 platform software stack — from firmware and documentation to distribution kernels — is advancing as a whole.
3.2 Sophgo: sophon-tools Wraps Up CV84X6 memory_edit Fix
Date: 2026-09-01 Source: sophgo/sophon-tools commits
Sophgo’s sophon-tools merged a fix (zetao.zhang): CV84X6 -p print limit inconsistent with validation (over-reporting by 2M) (#181), part of the wrap-up work for the v26.08.31 release batch. No release-level news.
3.3 Sipeed: NanoKVM Optimizes H264 Video Stream Concurrency
Date: 2026-09-01 Source: sipeed/NanoKVM commits
Sipeed’s NanoKVM (a RISC-V-based IP-KVM) merged two commits: isolating H264 subscribers and sharing H264 capture frames, improving video stream performance and memory usage under concurrent multi-client viewing. A minor maintenance item.
Domestic team verification conclusion: T-Head (XUANTIE-RV), ESWIN Computing (eswincomputing), and revyos had no pushes during the window; Espressif (espressif) saw routine progress on esp-idf, arduino-esp32, etc., with no release-level news; Nuclei’s nuclei-linux-sdk had repository pushes but no new commits on the main branch (likely branch/tag operations); gnews Chinese queries (XiangShan/T-Head/XuanTie, Nuclei/ESWIN, Espressif, SpacemiT, Sophgo, StarFive when:7d) all returned zero hits, so domestic team information continues to rely on GitHub verification.
IV. Embodied Intelligence and Robotics Special Section
4.1 No Robotics-Specific News in the Window; Recent 3-Day Trends and Opportunity Window
Date: 2026-09-02 Source: gnews embodied intelligence when:3d zero hits (see appendix for verification)
No embodied intelligence/robotics-specific news hits during the window (gnews Chinese and English queries both returned zero). For recent 3-day trends, refer to: MicroDuck’s open-source bipedal robot (reported 09-01, powered by Rockchip RK3566, an ARM platform) surpassing $2.5 million in first-day preorders, validating strong demand for “low-cost open-source robots + reinforcement learning software stacks”; for the RISC-V side, the opportunity window remains in September’s domestic robotics expo season and the ramp-up of robotics SKUs across various SoCs. This section remains in quiet observation for this issue.
V. Summary and Trend Observations
- CUDA’s official roadmap points to RISC-V host CPUs: At Hot Chips 2026, NVIDIA publicly disclosed its porting requirements list for the first time (RVA23, server SoC/platform specifications, ACPI, PCIe coherency, P2P), and named SiFive as its RISC-V partner for NVLink Fusion, with plans to demo a system running CUDA on-site. This is one of the strongest commercial endorsements of the RISC-V server ecosystem to date; however, hard thresholds such as ACPI mean qualifying hardware is still years away, and in the near term it will only appear in enterprise-class servers.
- RISC-V real-time cores continue to penetrate mainstream AIoT SoCs: Qualcomm’s Dragonwing Q2 series — “ARM application cores + RISC-V real-time core (Zephyr)” — further confirms that this combination has become a mainstream approach for edge AI chips.
- Domestic RISC-V MCUs step up overseas channels: GigaDevice’s GD32 (including RISC-V architecture) is leveraging the Rutronik channel to expand into EMEA and Southeast Asia, covering industrial/automotive/energy and other markets.
- Domestic teams are in a routine iteration phase: SpacemiT’s K3 UEFI firmware fixes from external contributors, the P3 datasheet going online, and AI documentation English translation are the most substantive progress in the window; Sophgo and Sipeed made maintenance commits; none of the seven verified organizations had release-level new products.
- Open-source toolchain depth continues to broaden: A Rust compile-time RISC-V interpreter passed ACT certification tests, and an RV32IMF teaching simulator gained stars, as the education and verification software ecosystem continues to fill in gaps.
- Limitations note: Google News Chinese sources returned zero hits for domestic teams, so the domestic section relies on GitHub commit verification; Qualcomm’s model-level RISC-V real-time core details are based on CNX’s reporting; the Hot Chips talk was held on 08-23, and this issue is a belated in-depth report (ServeTheHome published on 09-01).
Appendix: Complete Source List
| No. | Event | Source Links |
|---|---|---|
| 1 | NVIDIA CUDA for RISC-V | ServeTheHome, Chips and Cheese, NVIDIA Hot Chips Agenda |
| 2 | ab-riscv-interpreter 0.2 | Project Abundance, HN, crates.io |
| 3 | Raven-RiscV | GitHub |
| 4 | Qualcomm Dragonwing Q2 | CNX Software, Qualcomm |
| 5 | GigaDevice Rutronik | GigaDevice, Evertiq, Bisinfotech |
| 6 | SpacemiT three repositories | edk2-platforms, docs-chip, docs-ai |
| 7 | Sophgo sophon-tools | sophgo/sophon-tools |
| 8 | Sipeed NanoKVM | sipeed/NanoKVM |
| 9 | Candidate list | candidates.txt (fetch_news.py output + gnews supplementary check + GitHub API verification) |
Quiet Source Verification Table (This Issue’s Window)
| Source/Query | Verification Result |
|---|---|
| gnews XiangShan/T-Head/XuanTie when:7d | 0 hits |
| gnews Nuclei/Nuclei/ESWIN when:7d | 0 hits |
| gnews Espressif/Espressif when:7d | 0 hits (RISC-V related) |
| gnews embodied intelligence when:3d | 0 hits |
| gnews SpacemiT/SpacemiT when:7d | 0 hits |
| gnews SOPHGO/SOPHGO when:7d | 0 hits |
| gnews StarFive/StarFive when:7d | 0 hits |
| gnews Andes/Andes when:7d | Noise only (Chilean Inca ruins, soccer matches) |
| gnews Milk-V when:7d | Irrelevant only (Armbian 26.8, MSI WS300) |
| gnews RISC-V when:1d | Normal, all hits already covered/noise |
| Electronic Design ESP32-P4 | Product catalog page (Mouser listing), not news, excluded |
| GitHub XUANTIE-RV / eswincomputing / revyos | 0 pushes in window |
| GitHub espressif | Routine progress (esp-idf etc.), no release-level activity |