RISC-V Daily Intelligence Report (2026-08-28)
Research Window: Past 24 hours (2026-08-27 08:18 ~ 2026-08-28 08:18, Beijing Time) Sources: HN, Google News aggregation, CNX Software, RISC-V International official blog, GitHub API (org commit search), Business Wire, etc. (see appendix for details)
Index
- I. Open-Source Community and Software Ecosystem
- RISC-V International Publishes Batch of World RISC-V Days 2026 Global Event Recaps (08-28)
- II. Product and Ecosystem News
- USB-C Deskradar: An Open-Source ADS-B Flight Tracker Based on ESP32-C3 (RISC-V) (08-27)
- III. Domestic Team Updates and Deep Dives
- Sophgo: CV84X6 Official Specs Land, Toolchain Commits Merge Densely (08-27)
- XiangShan: 66 Commits, Microarchitecture Performance Optimization and Verification Analysis in Parallel (08-27)
- SpacemiT: K3 AVL Documentation and RL Benchmark Tooling Refinement (08-27)
- IV. Embodied Intelligence and Robotics Special Section
- MIPS Becomes RISC-V International Premier Member, Leading Physical AI Open Standards (08-27)
- V. Summary and Trend Observations
- Appendix: Complete Source List
I. Open-Source Community and Software Ecosystem
1.1 RISC-V International Publishes Batch of World RISC-V Days 2026 Global Event Recaps
Date: 2026-08-28 (Beijing Time, UTC 08-27 18:32) Source: riscv.org blog (Turin), Graz, Tel Aviv, Boston, etc.
RISC-V International published 10 World RISC-V Days 2026 event recap reports in a single batch within the window, covering 10 cities worldwide including Turin, Italy; Graz, Austria; Tel Aviv, Israel; Boston, USA; Gujarat, India; Nairobi, Kenya; Buenos Aires, Argentina; Bangladesh (Mymensingh, Dhaka); and Heraklion, Greece. Key points: The Turin stop (February 26, Politecnico di Torino, over 225 registered attendees) focused on benchmark comparisons, fully open-source chip development, and emerging technologies such as FLOW PPU; the Graz stop (February 24, Graz University of Technology, nearly 100 attendees) covered CHERI security, reconfigurable and scalable SoCs, hardware accelerators, CPU design and benchmarking, and discussed NXP’s RISC-V involvement and the future of RISC-V in Europe; the Boston stop (February 27, Red Hat) was held during a blizzard and included hands-on Fedora and AI sessions. This batch of recaps demonstrates that RISC-V community day events have become a regular fixture spanning six continents.
II. Product and Ecosystem News
2.1 USB-C Deskradar: An Open-Source ADS-B Flight Tracker Based on ESP32-C3 (RISC-V)
Date: 2026-08-27 Source: CNX Software
CNX Software reported on the open-source project USB-C Deskradar: a desktop ADS-B flight tracker based on the Espressif ESP32-C3FH4 (single-core 32-bit RISC-V, up to 160 MHz, 400KB SRAM, 4MB Flash), featuring a 1.28-inch 240×240 round TFT display that shows nearby flights (heading, speed, callsign, altitude, aircraft type) in real time via a sonar-style radar interface. Data comes from the adsb.fi or OpenSky Network open APIs, and it supports a Wi-Fi provisioning portal, airport runway overlays, and a 3D-printed enclosure (STL open-sourced). The project is open-sourced on GitHub (arvis91/deskradar, MatixYo/ESP32-Plane-Radar) and has been picked up by Chinese vendors on AliExpress as a cheap desktop gadget. This is a maker hardware and RISC-V MCU application case, reflecting RISC-V’s penetration into low-cost IoT terminals.
III. Domestic Team Updates and Deep Dives
3.1 Sophgo: CV84X6 Official Specs Land, Toolchain Densely Merged
Date: 2026-08-27 Source: sophgo/sophon-tools, sophgo/sophon-demo
The Sophgo sophon-tools window merged roughly 15 commits, with the core event being the landing of official CV84X6 specs (PR #152, bmssm 2.3.4 / sophliteos 2.2.3): compute specs 64T/32/2, display name set to CV84X6, and CPU spec clock frequency corrected from 2.5GHz to 2.6GHz per the official spec table (v2.2.4). Combined with yesterday’s daily report on large-scale CV84X2 adaptation (get_info v1.5 filling in 19 metrics, etc.), this confirms that the CV84X family has multiple models, with official specs gradually being solidified into the toolchain. Accompanying changes in the same period: CV84X2 adaptation tool version numbers completed, single-source-of-truth version numbering refactor (root release prohibited from passing version numbers), bmssm added Prometheus metric forwarding (disabled by default, token authentication, v2.2.2), reasonix automatically strips debug info before embedding and embeds deb packages by default, sophliteos agent WebSocket switched to same-origin addressing; sophon-demo added a ResNet example adapted for BM1684X2 (SE13-64 single board). Sophgo is paving the way for monitoring, operations, and example software stacks for the new CV84X series.
3.2 XiangShan: 66 Commits, Microarchitectural Performance Optimization and Verification Analysis in Parallel
Date: 2026-08-27 Source: OpenXiangShan org commit search
OpenXiangShan had roughly 66 commits in the window, with performance optimization and verification analysis proceeding on two parallel tracks. On the optimization side: added RVV string microbenchmarks (rvv-string-bench #85); IFU/ICache instruction alignment path optimization (#6220); MMU alignment of TLB flush latency caused by CSR changes (#6421); cpu-o3 avoids redundant ROB scans and FTQ copies (#1067); fcmp treats FLTQ/FLEQ as quiet comparisons (qNaN does not set NV); codegen generates block copies for single-dimensional array assignments (#125). On the verification analysis side: dcache bank conflict analysis scenarios and code landed, analysis No. 4636 wrapped up, difftest filled in KMHV3 for XSTileDiffTop/NoCDiffTop, csrc switched to generating C++ opcode encodings from Opcodes.scala, NEMU references and ready-to-run synchronized updates, and routine nix dependency upgrades. The “research analysis accumulation + microarchitectural polishing” pattern of activity continues, with no new architecture-level changes.
3.3 SpacemiT: K3 AVL Documentation and RL Benchmark Tooling Polish
Date: 2026-08-27 Source: spacemit-com/docs-chip, spacemit-com/model_zoo_rl, spacemit-com/ai-sdk
SpacemiT had 4 commits in the window: the docs-chip repo restructured its hardware resource documentation, added K3 AVL (Allowable Voltage Limits) documentation and standardized AVL terminology; model_zoo_rl fixed unrealistic timing in reinforcement learning benchmarks (#9); ai-sdk synchronized updates to the rl submodule. Combined with yesterday’s K3 BSP v1.0.7 OPP table efuse calibration optimization, the AVL documentation is part of the supporting work for K3 power and voltage management. Activity volume was low for the day, consisting of ongoing documentation and toolchain polish.
IV. Embodied Intelligence and Robotics Special Section
4.1 MIPS Becomes RISC-V International Premier Member, Leading Open Standards for Physical AI
Date: 2026-08-27 Source: Business Wire (republished by Yahoo Finance)
MIPS (now “MIPS, by GF” under GlobalFoundries) announced its promotion to RISC-V International Premier Member, with its SVP and CTO Yankin Tanurhan appointed Vice Chair of the RISC-V International Board of Directors. The company will play a leading role in open standards and semiconductor technologies for physical AI platforms spanning aerospace, AI, automotive, industrial, and intelligent edge; MIPS is currently active in multiple SIGs and working groups including Automotive, Functional Safety, Crypto, Vector, and Documentation, aligning RISC-V standards work with its differentiated microarchitecture and custom silicon solutions. RISC-V International CEO Andrea Gallo welcomed its continued contributions on high-throughput real-time platforms. This event directly binds “physical AI open standards” to the RISC-V governance layer and is the most important ecosystem signal in the embodied intelligence direction for this window.
No other new hardware/product events occurred in the embodied intelligence direction during this window (08-27 08:18 ~ 08-28 08:18): the media digestion period following the close of the 2026 World Robot Conference (August 19–24) continues, and yesterday’s daily report already covered Tiangong Omni’s double championship and the H1 humanoid robot shipment report; on August 27, MERICS published a China-themed analysis on “humanoid robots + decarbonization + platform economy” (policy perspective, not involving RISC-V, included only as industry background reference, not covered in the main text).
V. Summary and Trend Observations
- This window is a “organizational governance + domestic team delivery” type of market: the biggest international event is MIPS’s promotion to RISC-V International Premier Member and its appointment as Vice Chair of the Board, elevating the physical AI open standards agenda to the governance layer; on the community side, RISC-V International published a batch of 10-city World RISC-V Days recaps, confirming the globalization and normalization of community day events.
- Sophgo’s CV84X6 official specs landing (64T/32/2 compute, 2.6GHz CPU) connects with yesterday’s CV84X2 adaptation report, gradually clarifying the CV84X family product outline; accompanying operational engineering actions such as Prometheus metric forwarding, reasonix debug stripping, and single-source-of-truth versioning indicate that the new products have entered the final toolchain wrap-up stage before mass production.
- XiangShan remains highly active with 66 commits, with its direction shifting from verification analysis to a dual focus on “verification analysis + microarchitectural performance optimization” (TLB flush latency, IFU/ICache alignment, cpu-o3 redundant scans, RVV string benchmarks), showing clear signals of research converging toward engineering.
- SpacemiT had a documentation polish day (K3 AVL documentation), and combined with yesterday’s BSP v1.0.7 release, it is overall in a quiet phase within its monthly iteration rhythm.
- Limitations note: In this window, gnews Chinese team queries (T-Head/XiangShan/Nuclei/Sophgo/ESWIN) were all empty or noise (XiangShan hits were all Beijing Xiangshan Forum, unrelated to the XiangShan processor), so domestic team information is based on GitHub commits; one futu English headline mislabeled 301536 (SigmaStar) as “StarFive Technology,” which was verified against the East Money data page and excluded, not included.
Appendix: Complete Source List
| No. | Event | Source Links |
|---|---|---|
| 1 | World RISC-V Days 2026 Recap (10 cities) | riscv.org Turin, Graz, Tel Aviv, Boston, Gujarat, India, Nairobi, Buenos Aires, Mymensingh, Bangladesh, Dhaka, Bangladesh, Heraklion, Greece |
| 2 | ESP32-C3 Deskradar | cnx-software.com |
| 3 | MIPS becomes a RISC-V International Premier Member | Business Wire, Yahoo Finance |
| 4 | Sophgo CV84X6 official specs land | sophgo/sophon-tools PR #152, sophgo/sophon-demo |
| 5 | XiangShan 66 commits | OpenXiangShan org |
| 6 | SpacemiT K3 AVL documented | spacemit-com/docs-chip, model_zoo_rl |
Supplementary Query Verification Table (24h window, Beijing time 08-27 08:18 ~ 08-28 08:18)
| Source/Query | Verification Result |
|---|---|
| fetch_news.py 24h candidates (16 items) | Valid main threads: World RISC-V Days 10 recaps (riscv.org, logged as 1.1, aggregated into one item), MIPS Premier Member (Business Wire, logged as 4.1), ESP32-C3 Deskradar (CNX, logged as 2.1); NVIDIA NVHBM memory is x86/AI chip content (excluded); Libgcrypt 1.12.3 is an Intel x86 optimization (excluded); IndexBox chip verification generic article (excluded); xykj61/grain and 3 other new repos with 0-61 stars (excluded) |
| gnews “RISC-V” when:3d / when:1d | Within the when:3d window only MIPS (logged); when:1d no new items; the rest are old news from 8-24/25/26 (BigSky, GCC patches, Armbian, Adafruit, etc., reported yesterday) |
| gnews Chinese team queries (T-Head/XuanTie/XiangShan/Sophgo/SpacemiT/Nuclei/ESWIN when:7d) | T-Head/XuanTie, Sophgo, Nuclei, ESWIN queries all empty; the 13 XiangShan hits for XiangShan Forum/Xiangshan Park news are all same-name noise (Beijing Xiangshan Forum is a security conference, unrelated to the XiangShan processor, entire batch excluded); SpacemiT only hit old GCC/LLVM/Armbian news |
| gnews vendor English queries (SiFive/Milk-V/StarFive/SpacemiT/Andes) | SiFive only NVIDIA NVHBM (irrelevant); Milk-V no in-window hits; StarFive hit 301536.SZ semi-annual report (net profit +619.5% YoY, RMB 6 per 10 shares), but verification via East Money data page shows 301536 is actually SigmaStar, the futu English headline mislabeled it “StarFive Technology,” and RISC-V relevance evidence is insufficient (excluded); Andes hits are all Andes mountain range same-name noise and the 8-24 D23-SE certification old news |
| gnews robotics queries (RISC-V robot / humanoid robot RISC-V / embodied intelligence when:3d) | RISC-V robot only old news; humanoid robot RISC-V empty; embodied intelligence hit MERICS China policy analysis (08-27, no RISC-V involvement, background only) |
| GitHub org commit search (in-window) | OpenXiangShan 66 (logged as 3.2), sophgo 15 (logged as 3.1), spacemit-com 4 (logged as 3.3), espressif 57 (docs/CI noise, excluded), XUANTIE-RV / Nuclei-Software / eswincomputing 0 |
| gnews “RISC-V” bare query to verify proxy | Proxy normal (when:1d returns results, content duplicates the above) |