RISC-V Daily Intelligence Report (2026-08-18)

Research window: Past 24 hours (2026-08-17 08:20 ~ 2026-08-18 08:20 Beijing time) Sources: HN (Algolia API), Google News RSS aggregation (English + Chinese, via proxy), CNX/LinuxGizmos/Phoronix/riscv.org RSS, GitHub API (riscv official org/XiangShan/T-Head/SpacemiT/Sophgo/ESWIN/Nuclei/ESWIN), espressif.com official pages, etc. (see appendix for details)

I. Open-Source Community and Software Ecosystem Updates

1.1 RISC-V Official HAC Specification Undergoes Third Consecutive Day of Intensive Revisions (15+ Commits, Review Convergence Sprint Continues)

Date: 2026-08-17 18:00 ~ 2026-08-18 07:45 (Beijing Time)　Source: riscv/riscv-high-assurance-cryptography GitHub

The High Assurance Cryptography (HAC) specification repository merged 15+ additional commits within the window, continuing the ML-KEM/ML-DSA post-quantum mainline sprint from the previous two days: Resolved ace.size returning a PI's size in a suitable status (clarifying under which CR states ace.size returns the PI size), Clarify padding and key derivation behavior, Marked issue of ace.load/ace.store in wrong extension as a non-issue (cross-extension use of ace.load/store classified as a non-issue), three consecutive updates to ace-ISA-algorithms.adoc, revisions to ace-introduction/acronyms, and a docs-resources dependency upgrade (#146). Three consecutive days of intensive revisions (roughly 12 commits/day over the prior two days) indicate that this extension specification targeting FIPS 140-3-grade high-assurance cryptographic implementations remains in its review convergence phase, aligned with this week’s security/cryptography mainline (Spectre paper, SPMP maintenance): RISC-V official is systematically shoring up its security and cryptographic infrastructure.

1.2 XiangShan Main Branch Merges 8 Commits in a Single Day: MissQueue Fix, Tage Random Allocation, Banked Regfile Refactor

Date: 2026-08-17 10:38 ~ 14:59 (Beijing Time)　Source: OpenXiangShan/XiangShan GitHub

The XiangShan main branch merged 8 commits within the window (the main branch had previously been stalled at the 08-14 satp flush fix #6014; yesterday’s report judged “no main-branch-level new feature merges,” which was overturned today):

MissQueue fix (#6308): secondary_ready should gate req_valid — the secondary ready signal must gate request valid; a memory access queue correctness fix;
IFU fix (#6354): correct checkerRedirect taken — front-end instruction fetch redirect path correction;
Tage new feature (#6349): random allocate — the Tage branch predictor introduces a random allocation policy, a new feature at the predictor behavior level;
Register file refactor (#6357): banked regfile switches to using the low index bits as bankIndex, a layout optimization for multi-bank physical register files;
Ftq cleanup (#6358): removes dropTarinCounter counting logic;
transforms fix (#6361): parse module names before CHIRRTL serialization;
configs (#6359): MinimalConfig front-end mbtb/sc updates; CI labeler upgrade (#6333).

With 8 commits in a single day spanning fixes, features, and refactors, the XiangShan main branch development pace has returned to an active tier.

1.3 riscv-unified-db Merges Three Instruction Semantics Fixes: zalrsc Sign Extension, sstateen Fixed Length, c.sdsp Index

Date: 2026-08-18 05:22 ~ 05:36 (Beijing Time)　Source: riscv/riscv-unified-db GitHub

The RISC-V official Unified Database (unified-db, UDB project) merged three instruction semantics-level fixes within the window:

fix(zalrsc): sign-extend the lr.w result on RV64 (#2460) — the Zalrsc extension’s lr.w result on RV64 requires sign extension;
fix(csr): sstateen0-3 take the stateen family's fixed length of 64 (#2395) — sstateen0-3 CSRs take the fixed 64-bit length;
fix(isa): c.sdsp must use its full 5-bit register index (#2419) — the compressed instruction c.sdsp must use its full 5-bit register index.

UDB is the single machine-readable source of instruction semantics for RISC-V official specs/software toolchains (consumed by riscv-arch-test, Sail, etc.); such low-level semantics fixes directly affect the correctness of testing and simulation tools, constituting “specification infrastructure”-level maintenance.

1.4 meta-riscv: SpacemiT K1 Mainline Kernel Bumped to 7.2, u-boot Source URL Fixed

Date: 2026-08-18 02:10 / 05:33 (Beijing Time)　Source: riscv/meta-riscv GitHub

The Yocto RISC-V layer meta-riscv updated K1-related recipes within the window: linux-mainline-k1: use 7.2 kernel version (the Linux mainline kernel recipe for SpacemiT K1 upgraded to version 7.2) and u-boot: fix k1 SRC_URI (fixing the K1 u-boot source URL). K1 is SpacemiT’s mass-produced high-performance RISC-V SoC (8-core, already adopted in multiple development boards); its mainline kernel tracking upgrade within the Yocto ecosystem reflects that K1’s Linux mainline support continues to roll forward (see 3.2 SpacemiT deep dive).

1.5 riscv-smmtt Merges PR #303 + riscv-arch-test Test Gating Update

Date: 2026-08-17 18:35 (Beijing Time)　Source: riscv/riscv-smmtt GitHub / riscv-arch-test

The Smmtt (MMU page table walk interrupt/MPTINVAL-related specification) repository merged PR #303 (mptinval-after-iofence, ordering semantics between page table invalidation operations and IOFENCE). riscv-arch-test concurrently has a Gate mcause hardware error with Sm1.13.0 (#2134) test gating update, with the remainder being routine renovate dependency upgrades. Other active repositories in the riscv org (riscv-glossary, docs-spec-template, riscv-cheri, learn, etc.) saw routine documentation/dependency maintenance.

1.6 Open-Source Project Watch

AGaMEMnon (39★, 5 consecutive pushes from 08-17 23:11 to 08-18 08:18 Beijing Time): an open-source SDK and FPGA toolchain for the AGM AG32 RISC-V MCU (with embedded AGRV2K FPGA fabric); within the window it implemented Rule 1 (byte disjointness) and Rule 2 (routing invariance) sub-rules, completed end-to-end build+sim verification of serv_blinky, and passed T1 re-verification on 10/10 pads — this domestic RISC-V MCU’s open-source toolchain is entering the rule-compliance and verification convergence phase (second consecutive day of coverage).
HN 24h Zero Hits: The Algolia riscv query returned no story entries over the past 24 hours; the open-source community news side is quiet.

II. Product and Ecosystem Updates

2.1 Mouser Begins Selling Espressif ESP32-P4X-EYE Vision Development Kit (Today’s Only New Product on the News Side)

Date: 2026-08-17 (reported 18:49 Beijing time / 04:18 the following day)　Source: Electronic Design (gnews link) / Electropages (gnews link)

Mouser has begun shipping the Espressif ESP32-P4X-EYE vision development kit, targeting AI, edge computing, HMI, and camera applications. Verified via the official espressif.com page: the ESP32-P4 uses a dual-core RISC-V CPU (up to 400 MHz), supports a single-precision FPU and AI instruction extensions, and comes with an advanced memory subsystem and high-speed peripherals—this is Espressif’s first high-performance general-purpose SoC series to break entirely away from Xtensa. The ESP32-P4X-EYE kit integrates camera and display interfaces, making it an entry-level vision/edge AI hardware platform for the ESP32-P4 ecosystem. Significance: Espressif’s hardware availability for RISC-V on-device AI (perception/vision direction) is further materializing, and its “high-performance RISC-V + AI extensions” product line beyond the ESP32-C series is beginning to expand through channels.

2.2 Ecosystem Background Supplement: India’s C2S Program Has Supported 254 Chip Tapeouts Cumulatively (Follow-up)

Date: 2026-08-17　Source: DD India (gnews link)

Yesterday we reported that MeitY’s semiconductor design talent training had exceeded 68,000 people; in this window, DD India/EE Times India follow-up reporting supplements the statistical scope: the C2S (Chip to Startup) program has cumulatively driven 254 chip designs to complete tapeout. This figure is more comprehensive than yesterday’s “30+ tapeouts under DLI” scope (C2S and DLI are different programs). Reports related to VIHAAN (VEGA RISC-V core) (INSIGHTS IAS/SDXCentral) are all reprints of yesterday’s top story, with no new facts, and are not reported again.

III. Domestic Team Updates and Deep Dive

3.1 Espressif: llvm-project toolchain sync + esp-claw “Chat Coding” AI agent framework iteration

Date: 2026-08-18 08:22 (llvm-project push)　Source: espressif/llvm-project / espressif/esp-claw

llvm-project (Xtensa+RISC-V toolchain fork) pushed at 00:22 UTC on 08-18 (routine upstream sync); esp-nvd-mirror (NVD CVE mirror) auto-synced at 00:05; esp-idf (08-17 17:50 UTC) and esp-sr (speech recognition, 1489★, 09:18) were branch-level pushes.
esp-claw (2014★, created 2026-04-17): Espressif’s “Chat Coding” AI agent framework (a conversational coding agent framework for IoT devices). Within the window, fix(cli): block transient cdc reads (CLI fix for transient CDC reads) was merged. The espressif.com “AI Solutions” section has already listed the Chat Coding AI Agent Framework as a first-tier product line, and esp-claw-skills-lab (skills lab) also had a push the same day. Espressif’s positioning around “RISC-V chips + AI agent development paradigm” is worth continued tracking—the ESP32-P4’s AI instruction extensions and AI development framework are forming a closed loop.

3.2 SpacemiT spacemit-com: humanoid RL runtime branch maintenance + K1 mainline kernel 7.2

Date: 2026-08-17 18:01 / 20:12 (Beijing time)　Source: spacemit-com/model_zoo_rl / spacemit-com/model-zoo-vision / riscv/meta-riscv

model_zoo_rl (K3 humanoid robot reinforcement learning runtime/SDK, created 04-28, includes humanoid-sdk initialization, robot-test CI, per-policy kp/kd, etc.): within the window, the fix/eigen-cmake-target branch was pushed (fixing Eigen’s CMake target integration); the most recent merge on the default branch main was the 07-23 declarative model I/O and typed tensor support (#7). K3’s RL inference stack (combined with the previously reported SPERT NPU inference) continues to be maintained.
model-zoo-vision: branch-level push; the most recent merge on the default branch was the 08-14 YOLOP/YOLOPv2 road-scene models (#73), continuing the expansion pace of the vision model library.
K1 mainline kernel: meta-riscv upgraded the linux-mainline-k1 recipe to kernel version 7.2 (see 1.4)—SpacemiT’s K1 continues to roll forward in Linux mainline/Yocto ecosystem support, further evidence of the dual-track “product + open-source ecosystem” push.

3.3 Sophgo: sophon-tools batch merges (SSO auth fixes, gateway failover chain)

Date: 2026-08-17 22:42 ~ 2026-08-18 07:51 (Beijing time)　Source: sophgo/sophon-tools

Within the window, sophon-tools merged 9 commits in batch via AI agent branches (agent/sophon-tools-agent/*): SSO authentication system fixes (MYS-378: removing sessionless pass-through, register JWT validation, unified auth for local sensitive routes), built-in gateway failover chain (MYS-405: CF Worker → Alibaba Cloud FC gateway → pure BM25 fallback), two-stage upgrade (MYS-381), AI agent authentication (MYS-379), etc. This is an AI-agent-ification and multi-cloud disaster-recovery overhaul of Sophgo’s developer toolchain, constituting internal infrastructure iteration; tpu-mlir was a branch-level push (the most recent merge on the default branch predates the window).

3.4 T-Head / Nuclei / ESWIN / Sipeed: silent within the window

T-Head XUANTIE-RV: the most recent push for opensbi/zero_stage_boot remains 08-15 (reported in the previous two days), with no new additions in the window.
Nuclei Nuclei-Software: no new push (most recent lauterbach-startup 08-11).
ESWIN eswincomputing: no new push (most recent 07-14), silent on the public repository side.
Sipeed: sipeed_wiki had an update on 08-17 10:27 (Beijing time) (routine wiki maintenance), with no code repository activity.

3.5 Snapshot of domestic team organization activity (GitHub API, within the window)

IV. Special Chapter on Key Directions: Embodied Intelligence and Robotics

4.1 SpacemiT K3 humanoid RL runtime (model_zoo_rl) branch-level maintenance

There were no major new releases in the embodied intelligence direction this window; the most noteworthy remains SpacemiT’s K3 humanoid robot reinforcement learning stack: within the window, model_zoo_rl pushed the fix/eigen-cmake-target branch (build integration fix), and the default branch merged declarative model I/O and typed tensor support on 07-23—the RL inference stack (including the previously reported SPERT NPU full-graph inference, robot-test CI, per-policy kp/kd configuration) continues to evolve, though at a “maintenance” rather than “new feature” pace.

4.2 Edge vision hardware availability: ESP32-P4X-EYE on sale

From the embodied intelligence “perception layer” perspective, the Espressif ESP32-P4X-EYE vision development kit (dual-core RISC-V 400MHz + AI instruction extensions + camera/display interfaces) going on sale provides a new low-cost RISC-V hardware option for edge vision perception (SLAM preprocessing, object detection front-end, HMI interaction). Together with SpacemiT SPERT (edge NPU inference) and Sophgo’s vision example library (YOLO series), it constitutes continued reinforcement of the perception layer within the domestic RISC-V “perception—decision—motion control” three-layer localization path.

4.3 Review of trends over the past three days

Looking back at 08-15 ~ 08-17: the Dishui Lake Forum established the “real-time core + application core” dual-core heterogeneous motion control route (Fengfan FU75XX, HPMicro HPM53M1, SpacemiT K3 motion control positioning); the architecture debate (Grinberg’s long article vs. responses from Global South engineers) showed rare consensus on “cheap embedded RISC-V is a must-win”; the embodied intelligence direction overall was in a release lull this week, with the main thread still being “cost-sensitive + real-time-first” motion control localization and edge perception stack refinement.

V. Summary and Trend Observations

A day of calm on the news side, active on the GitHub side: within the window there was only 1 new product on the news side (ESP32-P4X-EYE on sale), with zero HN hits in 24h and all vendor/Chinese-language queries empty; yet RISC-V official organizations and domestic teams remained highly active on GitHub—the “code is news” characteristic is evident.
HAC specification revisions intensive for the third consecutive day (15+ commits): ace.size semantics, padding/key derivation, ace.load/store cross-extension characterization—the FIPS 140-3-oriented post-quantum cryptography extension has entered a review convergence sprint, with security/cryptography being the current priority mainline for RISC-V official.
XiangShan main branch active again: 8 merges in a single day (MissQueue fixes, Tage random allocation, banked regfile refactor, IFU/Ftq fixes), breaking the main-branch silence since 08-14, with XiangShan’s development pace returning to active.
Domestic teams advancing on three fronts: Espressif (AI agent framework esp-claw 2014★ iteration + RISC-V toolchain sync), SpacemiT (humanoid RL runtime maintenance + K1 mainline kernel 7.2 landing in Yocto), Sophgo (toolchain agent-ification and disaster-recovery overhaul); T-Head/Nuclei/ESWIN silent.
Ecosystem infrastructure-level maintenance worth tracking: three instruction semantics fixes in riscv-unified-db (zalrsc/sstateen/c.sdsp) directly affect the correctness of toolchains such as arch-test/Sail; such “specification infrastructure” dynamics are leading indicators of ecosystem health.

Limitations note: The ESP32-P4X-EYE report body yielded only an empty shell page via gnews redirect; product details (kit contents, price) are subject to verification via the title and the official espressif.com page; GitHub data is based on the unauthenticated API (completed within the 60 req/h rate limit; some repository pushes are branch-level dynamics, and default-branch commits are subject to verification via the commits API); the sophon-tools merged content is internal toolchain iteration, with no business impact assessment performed.

Appendix: Complete Source List

No.	Event	Source Link
1	HAC spec revised intensively for the third consecutive day (15+ commits)	Link
2	8 commits merged into XiangShan main branch (#6308/#6354/#6349/#6357/#6358/#6361/#6359/#6333)	Link
3	Three instruction semantics fixes in riscv-unified-db (#2460/#2395/#2419)	Link
4	meta-riscv K1 mainline kernel 7.2 + u-boot fixes	Link
5	riscv-smmtt PR #303 (mptinval-after-iofence)	Link
6	AGaMEMnon pushed for the second consecutive day (Rule 1/Rule 2 implementation)	Link
7	Mouser begins selling ESP32-P4X-EYE (Electronic Design)	Link
8	ESP32-P4 official spec page (dual-core RISC-V 400MHz + AI extensions)	Link
9	Espressif llvm-project (toolchain sync)	Link
10	Espressif esp-claw (Chat Coding AI agent framework, 2014★)	Link
11	SpacemiT model_zoo_rl (K3 humanoid RL runtime)	Link
12	SpacemiT model-zoo-vision (YOLOP road scenes, etc.)	Link
13	Sophgo sophon-tools (agent batch merges)	Link
14	India C2S program 254 tapeouts (DD India, follow-up)	Link

Source Verification Table (Appendix for a Weak News Day)

| Source | Verification Result | |—|—| | Google News “RISC-V when:1d” (bare query as proxy check) | Valid (10 items): ESP32-P4X-EYE (2 items) included; VIHAAN (2 items) and C2S training (2 items) are follow-ups to items already reported on 08-16; 2 non-RISC-V noise items (Linux PowerPC/GPU Rust) excluded; 3 China open-source roundup items (Menafn/asatunews/Qatar Tribune) excluded for lacking RISC-V details | | Vendor English queries (SiFive / Andes / StarFive / Milk-V / SpacemiT / SOPHGO / Ventana / ESP32-P4) | SiFive: only IPO listing noise; Andes: hits were old GPU industry news, excluded; StarFive: hits were the 08-13 BMC report (already covered yesterday) + FIBA basketball noise; Milk-V / SpacemiT / SOPHGO / Sophgo: no hits; Ventana: all Big Sur wildfire noise; ESP32-P4: hit the Mouser kit (included) | | Chinese team keywords (T-Head / XiangShan / Nuclei / ESWIN / Espressif when:7d) | All no hits — quiet on the Chinese news side | | Direct RSS pulls (linuxgizmos / riscv.org / CNX) | No new items in window: linuxgizmos latest RISC-V item 08-06, riscv.org blog 07-29, CNX no hits | | HN Algolia “riscv” (24h) | 0 hits | | GitHub topic:risc-v pushed | 5 repos: apart from AGaMEMnon (included), all are noise such as grain OS forks/personal profiles | | Domestic org activity (GitHub API) | OpenXiangShan/espressif/spacemit-com/sophgo active (see main text); XUANTIE-RV/Nuclei/eswincomputing/sipeed silent |