RISC-V Daily Intelligence Report (2026-08-16)
Research window: Past 24 hours (2026-08-15 08:20 ~ 2026-08-16 08:20 Beijing Time) Sources: HN, Google News aggregation (English + Chinese), EE Times China/Sina Finance (gnews links), Japan Today (gnews links), GitHub API (riscv official organization/XiangShan/T-Head/SpacemiT/Sophgo/ESWIN/Nuclei/ESWIN), LinuxGizmos, Phoronix aggregation, etc. (see appendix for details)
I. Open Source Community and Software Ecosystem Updates
1.1 RISC-V High-Assurance Cryptography (HAC) Specification Sees Intensive Updates: ML-KEM/ML-DSA Post-Quantum Cryptography Descriptions Refined (Top Story of the Day)
Date: 2026-08-15 (approx. 20 commits between 11:34 and 23:25 UTC) Source: riscv/riscv-high-assurance-cryptography GitHub
The RISC-V International High-Assurance Cryptography (HAC) specification repository saw roughly 20 commits within the window, primarily focused on post-quantum cryptography and high-assurance implementations: revisions to instruction set descriptions for ML-KEM (Kyber post-quantum key encapsulation) and ML-DSA (Dilithium post-quantum signatures), wording unification in the ACE-ISA-unpriv specification (“must” changed to “shall”), streamlining of the OCB3 structure, clarification of CR representation and capacity limits, as well as handling review comments (review1.md) and AsciiDoc formatting fixes. HAC is RISC-V’s extension specification targeting FIPS 140-3-level high-assurance cryptographic implementations (constant-time, side-channel protection). Its ML-KEM/ML-DSA and other post-quantum instruction set descriptions entering an intensive revision phase signals that RISC-V cryptographic extensions are converging toward practical deployment and standardization—directly relevant to RISC-V entering the trust boundaries of finance/government/cloud, and echoing this week’s security trust discussions sparked by the Spectre paper.
1.2 XiangShan difftest Verification Framework Enhanced: Configurable mma Verifier Backpressure + Batch Verification + macOS arm64 Host Support
Date: 2026-08-15 (commits at 06:00/16:08 UTC, Beijing 14:00/08-16 00:08) Source: OpenXiangShan/difftest GitHub
The difftest (differential co-verification framework) accompanying XiangShan merged three improvements within the window: feat(mma): add configurable verifier backpressure (#923) (configurable mma verifier backpressure), feat(mma): batch contiguous verification requests (#920) (batching of contiguous verification requests to improve verification throughput), and fix(runtime): support Darwin arm64 hosts (#930) (new macOS Apple Silicon host support). The Darwin arm64 support is particularly friendly to local development verification workflows. Within the window, the main XiangShan repository pushed at 08-15 18:07 UTC (the most recent merge on the main branch remains the 08-14 satp fix #6014; the day’s activity was branch/CI-related), while peripheral repositories including XSCache (08-15 18:55 UTC), difftest, NEMU, CoupledL2, GEM5, env-scripts, and circt were simultaneously active—the full XiangShan stack continues its high-frequency iteration.
1.3 RISC-V P Extension Specification Syncs Toolchain Versions (#322)
Date: 2026-08-15 (09:28 UTC, Beijing 17:28) Source: riscv/riscv-p-spec GitHub
The RISC-V P extension (Packed SIMD) specification repository merged Sync gcc, binutils, QEMU version and links (#322), updating the supported GCC/Binutils/QEMU versions and links—maintenance of P extension toolchain support status. The P extension (fixed-length SIMD, targeting DSP-class workloads) has application potential in embedded and AI edge scenarios, and the specification side maintains low-frequency, steady progress. Separately, riscv-unified-db (RISC-V Unified Database) saw routine dependency updates (automated renovate PRs).
1.4 Open Source Project Watch: Sipeed PicoClaw—An Ultra-Lightweight AI Assistant Written in Go (29.8k stars)
Date: 2026-08-14 (pushed 18:19 UTC, three-day trend) Source: sipeed/picoclaw GitHub
Sipeed’s open source project PicoClaw has grown rapidly recently (currently 29.8k stars, created 2026-02): an ultra-lightweight AI assistant written in Go, targeting $10-class hardware/10MB memory/millisecond-level startup, with architecture badges explicitly indicating support for x86_64/ARM64/MIPS/RISC-V/LoongArch, positioned as “minimal AI deployable anywhere.” The project brings lightweight AI assistants to low-resource architectures such as RISC-V, representing an active new force in the edge AI software ecosystem (push time slightly precedes the window start; listed as a three-day trend).
II. Product and Ecosystem Developments
2.1 EE Times China Feature: How Dual-Core RISC-V RT-MCUs Underpin the Motion Control Foundation of Embodied Robots
Date: 2026-08-15 (09:00 CST) Source: gnews link (EE Times China)
EE Times China published a feature examining the role of dual-core RISC-V RT-MCUs (real-time control MCUs) in the motion control foundation of embodied robots: the real-time core handles motor/joint control loops (current loop, position loop), while the application core handles communication/sensing/edge AI. This dual-core division of labor matches robots’ heterogeneous requirements of “real-time control + intelligent decision-making.” The representative product is the Fortior Technology FU75XX series (2nd-generation ME + 32-bit RISC-V dual-core MCU, positioned as “born for future robots” at its launch in 2025-11; the dual-motor drive model FU7512L was nominated for the 2026 China IC Design Achievement Award). This feature, together with the motion control chip signals from the Dishui Lake Forum earlier in this window (Gejian’s 500-nanosecond current loop, HPMicro HPM53M1 joint control, and SpacemiT K3 motion control positioning), forms part of the same narrative: RISC-V motion control MCUs are moving from “single-core real-time” to “dual-core heterogeneous.” See Chapter IV for a dedicated section.
2.2 Sina Finance: ESWIN’s Hong Kong IPO “Eve of Listing” — Cumulative Loss of RMB 4.9 Billion Over Three Years
Date: 2026-08-15 (12:24 CST) Source: gnews link (Sina)
Sina Finance reported under the headline “Eve of Listing” that ESWIN (the second entrepreneurial venture of Wang Dongsheng, “father of BOE”) is sprinting toward the Hong Kong Stock Exchange: cumulative losses of RMB 4.9 billion over three years, with the “first RISC-V architecture stock” narrative entering its listing window. Several reports had already appeared during 8/10-14 (third attempt at the HKEX, continuous headcount reduction, RMB 6.5 billion capital increase for the Wuhan base, etc., covered in yesterday’s report). Today’s “eve of listing” report indicates the IPO process has advanced to the stage near listing. ESWIN Computing’s automotive-grade AI MCU (EAM2011) has entered the supply chain for Zunjie intelligent seats, and the EAI8800 automotive-grade CMS chip was released at the Dishui Lake Forum (08-13); automotive electronics remains the main commercialization line. Its public GitHub (eswincomputing) remained silent during this window (most recent push 07-14).
2.3 Japan Today Overview: China’s Influence in Open-Source Technology (Including AI) (Ecosystem Background)
Date: 2026-08-16 (published 04:10 CST) Source: gnews link (Japan Today)
Japan Today published an overview article titled “China shaping the future of open-source technology – including AI,” focusing on China’s shaping influence in global open-source technology (including AI and chip architecture ecosystems). The article was surfaced by Google News’ RISC-V query (it touches on the RISC-V open-source ecosystem) and is included as an English-language ecosystem overview background item within this window (body details are based on the title and aggregated information; see the limitations note).
III. Domestic Team Updates and Deep Dives
3.1 SpacemiT: llama.cpp branch merges SPERT whole-graph kernel path + FlagGems-RACE branch active
Date: 2026-08-15 (04:10 UTC commit, 12:10 Beijing) Source: spacemit-com/llama.cpp GitHub / spacemit-com/FlagGems-RACE
The SpacemiT llama.cpp branch merged spacemit: add spert whole-graph kernel path (#31) within the window (adding a SPERT whole-graph kernel path)—SPERT is its edge-side AI acceleration engine, and a whole-graph kernel path means offloading the complete inference graph to the SPERT engine for execution, a key step for NPU acceleration of K1/K3 edge-side LLM inference; on the branch side, add-spacemit-backend / add-spacemit-backend-ime2 / mtmd-backend and others advance in parallel (IME kernels are located in ggml-cpu/spacemit/). Meanwhile, the FlagGems-RACE branch remains active (pushed 08-15 05:26 UTC, branches such as spacemit-backend-ops), connecting with yesterday’s reported K1 backend 90+ operator matrix. Combined with the docs-ai DeepSeek inference harness documentation (08-14), SpacemiT’s NPU-ification path for its edge-side AI stack of “chip + operator library + inference engine” is clear.
3.2 Sophgo: sophon-demo merges YOLOv8-pose tail-batch processing fixes
Date: 2026-08-15 (03:18 UTC commit, 11:18 Beijing) Source: sophgo/sophon-demo GitHub
Sophgo’s sophon-demo merged two YOLOv8-pose (pose estimation) fixes within the window: fix(YOLOv8_pose): 修复 opencv 尾批关键点索引与结果结构错误 and fix(YOLOv8_pose): 修复尾批非整数倍时的关键点采集崩溃—both targeting boundary defects in inference tail-batch (batch remainder) handling, authored 08-12 and merged 08-15, part of a batch merge wrap-up. Pose estimation is a foundational algorithm for embodied intelligence / humanoid robot visual perception, and Sophgo’s edge-side AI example library (BM1688/CV186X, etc.) continues to patch production-grade defects, consistent with yesterday’s ArcFace platform support merge cadence.
3.3 Espressif: llvm-project push + SBOM security tool CVE exclusion + QOI codec component
Date: 2026-08-15~16 Source: espressif/llvm-project / esp-idf-sbom / idf-extra-components
Multiple Espressif repositories were active within the window: llvm-project (Xtensa+RISC-V toolchain fork) pushed 08-16 00:15 UTC; esp-idf-sbom (SBOM generation tool) merged an update 08-15 08:17 UTC excluding the non-applicable CVE-2026-63650; idf-extra-components added a QOI image codec component 08-15 01:54 UTC (#801). Sustained investment in toolchain and secure supply chain infrastructure (SBOM) reflects the maturity of the ESP32-C series RISC-V MCU ecosystem.
3.4 T-Head: opensbi / zero_stage_boot branch pushes
Date: 2026-08-15 (04:17 UTC) Source: XUANTIE-RV/opensbi
T-Head’s XUANTIE-RV opensbi and zero_stage_boot repositories had pushes at 08-15 04:17 UTC (branch-level activity; the master branch’s most recent commit remains the opensbi 1.9 version commit from late June), with an overall steady cadence. Routine maintenance continues on the firmware/boot chain side for XuanTie C-series cores.
3.5 Snapshot of domestic team organizational activity (GitHub API, within window)
- XiangShan OpenXiangShan: three consecutive difftest merges (mma backpressure / batch verification / Darwin arm64, see 1.2); XSCache 08-15 18:55 UTC, XiangShan 18:07 UTC, NEMU/CoupledL2/GEM5/env-scripts pushed throughout the day.
- SpacemiT spacemit-com: llama.cpp SPERT whole-graph kernel (12:10 Beijing), FlagGems-RACE branch push (05:26 UTC)—NPU inference path advancing (see 3.1).
- Sophgo sophgo: sophon-demo YOLOv8-pose tail-batch fixes (11:18 Beijing); sophon-tools updated 08-14 13:24 UTC (window edge).
- Espressif espressif: llvm-project (08-16 00:15 UTC), esp-idf-sbom (CVE exclusion), idf-extra-components (QOI component)—active across all three lines of toolchain + security + components.
- T-Head XUANTIE-RV: opensbi/zero_stage_boot branch pushes (04:17 UTC).
- Nuclei Nuclei-Software: no new pushes within the window (most recent lauterbach-startup 08-11), normal cadence.
- ESWIN eswincomputing: no new pushes (most recent 07-14), public repository side silent, activity concentrated on the IPO and product side (see 2.2).
IV. Special Chapter on Key Directions: Embodied Intelligence and Robotics
4.1 Dual-core RISC-V RT-MCU: the “heterogeneous division of labor” narrative for the motion control foundation takes shape
The most directional signal in this window is the EE Times China feature “How Do Dual-Core RISC-V RT-MCUs Support the Motion Control Foundation of Embodied Robots?” (08-15): the dual-core architecture (a real-time core running motor/joint control loops + an application core running communication/perception/edge AI) has become the mainstream design approach for the motion control foundation of embodied robots, with the representative product Fortior FU75XX series (32-bit RISC-V dual-core, dual-motor drive) positioned since 2025-11 as “born for future robots.” This is completely in sync with the motion control signals from the Dishui Lake Forum (08-13): Gejian Semiconductor’s 500-nanosecond current loop / single-chip 25 degrees of freedom (yesterday’s report 3.3), HPMicro HPM53M1 humanoid robot joint control, and SpacemiT K3 robot motion control positioning—domestic RISC-V motion control solutions are evolving from “single-core real-time DSP/MCU” to “dual-core heterogeneous (real-time + intelligent),” further concretizing the domestic substitution path at the motion control layer.
4.2 Edge-side AI inference NPU-ification: SPERT whole-graph kernel path
The SPERT whole-graph kernel path in the SpacemiT llama.cpp branch (3.1) and Sophgo’s production-grade YOLOv8-pose fixes (3.2) jointly point to the maturation of the embodied intelligence software stack: the former offloads LLM/VLA inference to the edge-side NPU engine (low-power real-time capability), while the latter continues to patch engineering defects in visual perception examples. Combined with yesterday’s LeRobot (SmolVLA/ACT) edge-side deployment and humanoid robot adaptation, the three-layer domestic path for RISC-V embodied intelligence—”perception (vision) — decision (edge-side LLM/VLA) — motion (dual-core RT-MCU motion control)”—is gradually becoming clear.
V. Summary and Trend Observations
- Post-quantum cryptography becomes a RISC-V specification hotspot: The official RISC-V HAC specification saw approximately 20 commits within the window refining descriptions of post-quantum cryptographic instructions such as ML-KEM/ML-DSA, with the cryptographic extension converging toward FIPS-level high-assurance implementations—aligned with the security trust discussion triggered by this week’s Spectre-on-RISC-V paper, security/cryptography is becoming an official priority topic in the RISC-V ecosystem.
- The “dual-core heterogeneous” narrative at the motion control layer takes shape: The EE Times China feature (dual-core RISC-V RT-MCU) + Fortior FU75XX + Dishui Lake Forum motion control new products (Gejian/HPMicro/K3) are in sync, with domestic RISC-V solutions for the embodied robot motion control foundation moving from “single-core real-time” to “real-time core + application core” dual-core division of labor.
- Edge-side LLM inference acceleration sinks to the NPU: SpacemiT’s llama.cpp merges the SPERT whole-graph kernel path, with edge-side large model inference moving from “running on CPU” toward “NPU whole-graph acceleration,” forming a complete chain with the operator library (FlagGems-RACE) and inference documentation (docs-ai).
- ESWIN’s IPO enters the “eve of listing”: The Hong Kong stock “first RISC-V architecture stock” narrative advances to the verge of listing; despite cumulative losses of 4.9 billion over three years, its automotive-grade MCU/CMS product line and the mainstream domestic RISC-V narrative endorse it.
- Verification infrastructure continues to ramp up: XiangShan difftest adds verifier backpressure control and batch verification (improving throughput) and adds macOS arm64 host support, making verification efficiency of open-source high-performance cores a focal point of competitiveness.
Limitations note: The EE Times China original site (eet-china) is unreachable due to anti-scraping; the details of the 2.1 feature body are cross-inferred from the title and existing product lines (Fortior FU75XX, etc.), and specific model descriptions should defer to the original text; the Japan Today overview (2.3) body could not be scraped (gnews redirects to an empty shell page), and is included only as ecosystem background based on the title and aggregated hit information; the Advantech AOM-2721 board Ubuntu certification reported by 9to5Linux (08-15) could not be confirmed as to platform due to a 403 on the original site and no RISC-V evidence terms on the vendor page, so the body was not included; expressions such as “first RISC-V stock” are media phrasing; GitHub data is based on the unauthenticated API (completed within the 60 req/h rate limit).
Appendix: Complete Source List
| No. | Event | Source Link |
|---|---|---|
| 1 | RISC-V HAC High Assurance Cryptography Specification (riscv org) | Link |
| 2 | XiangShan difftest enhancements (mma backpressure/batch/Darwin) | Link |
| 3 | RISC-V P extension toolchain sync #322 | Link |
| 4 | Sipeed PicoClaw (Go lightweight AI assistant) | Link |
| 5 | EE Times China: Dual-core RISC-V RT-MCU motion control feature | Link |
| 6 | Fortior FU75XX dual-core RISC-V MCU launch (background) | Link |
| 7 | Sina: ESWIN “on the eve of IPO” | Link |
| 8 | Japan Today: China shaping open-source future | Link |
| 9 | SpacemiT llama.cpp SPERT full-graph kernel #31 | Link |
| 10 | SpacemiT FlagGems-RACE branch | Link |
| 11 | Sophgo sophon-demo YOLOv8-pose fix | Link |
| 12 | Espressif esp-idf-sbom CVE exclusion | Link |
| 13 | Espressif idf-extra-components QOI component | Link |
| 14 | T-Head XUANTIE-RV opensbi | Link |
| 15 | 9to5Linux: Advantech AOM-2721 Ubuntu certification (unverified platform, not included) | Link |
Slow-News-Day Source Verification Table (Low-Volume Day Appendix)
| Source | Verification Result | |—|—| | HN (risc-v/riscv query) | No RISC-V related stories in window | | Google News “RISC-V when:1d” (bare query proxy check) | Valid (7 items), of which 4 ETH/crypto noise items removed; Japan Today roundup included (2.3) | | 9to5Linux Advantech AOM-2721 | Original site 403, no RISC-V evidence terms on vendor page, platform unconfirmable, removed | | CNX/LinuxGizmos/Phoronix RSS | No strongly RISC-V related entries in window | | GitHub topic:risc-v pushed (24h) | Only grain OS (1-2 stars, noise) and profile pages, no substantive projects; PicoClaw was pushed 08-14 (past three days) | | Vendor English queries (SiFive/StarFive/Milk-V/SpacemiT/SOPHGO/Andes) | Hits within window all belong to events already reported yesterday (SiFive kernel library, StarFive BMC), deduplicated |