RISC-V Daily Intelligence Report (2026-08-15)
Research window: Past 24 hours (2026-08-14 08:20 ~ 2026-08-15 08:20 Beijing Time) Sources: HN, Google News aggregation (English + Chinese), Dishuihu Forum series coverage (eet-china/EDN/Jiwei/Xinzhi/Sina Finance/International Electronic Commerce), The Register/SC Media, USENIX Security 26 paper author blogs, GitHub API (XiangShan/T-Head/SpacemiT/Sophgo/Espressif/Nuclei/ESWIN), LinuxGizmos, Phoronix aggregation, etc. (see appendix)
I. Open Source Community and Software Ecosystem Updates
1.1 USENIX Security 26 Paper: Spectre Fully Demonstrated on Commercial Out-of-Order RISC-V Silicon (Today’s Top Story)
Date: 2026-08-12 (paper acceptance and blog publication; media spread 08-12~13) Source: Lukas Gerlach’s blog (short version of paper) / The Register / SC Media
The paper “Spectre on RISC-V Silicon: Attacks and Defenses on Commercial Out-of-Order Processors” by German researcher Lukas Gerlach et al. has been accepted to USENIX Security 26 and made public. The study systematically validated on commercially available out-of-order RISC-V processors — T-Head XuanTie C910/C920 and SiFive P550 — that Spectre variants previously demonstrated on x86 are equally feasible on RISC-V (some requiring additional techniques). Key findings: First, whether Spectre-BTB (v2) is exploitable depends on whether firmware enables the indirect branch predictor — disabled by default on C910/P550, enabled on C920; when enabled, attacks succeed but occasionally cause machine crashes, suggesting a hardware defect. Second, the researchers constructed a practical exploit chain that reads arbitrary files via BPF probes: the RISC-V BPF JIT generates no instructions for the BPF_NOSPEC barrier inserted by the kernel, so the verifier believes the program is protected while the generated code actually has no barrier, forming a “speculative type confusion” gadget. Third, the tested cores separate the BTB between user mode and kernel mode, making traditional kernel Spectre exploit paths more difficult. The paper also provides defense recommendations. This is the first public systematic refutation of the “RISC-V is immune to Spectre” myth since the 2023 T-Head security advisory, and serves as an important reminder for building trust as RISC-V enters server/cloud infrastructure.
1.2 XiangShan: Fixes First Fetch Fault After satp Flush (#6014)
Date: 2026-08-14 (submitted 07:02 UTC, 15:02 Beijing time) Source: OpenXiangShan/XiangShan GitHub
The XiangShan open-source high-performance RISC-V processor (7,191 stars) merged fix(csr): fix first fetch fault after satp flush (#6014) within the window, fixing a first fetch fault after satp (page table base register) flush — a boundary-condition defect fix in the address translation/page table switching path, directly related to virtual memory switching correctness. Combined with continuous pushes to peripheral repositories including difftest/XSCache/GEM5/NEMU within the window (all updated within 15h), the XiangShan project team maintains a full-stack high-frequency iteration cadence. The 08-13 BERTi performance enhancement and elaboration parameter caching acceleration were already covered in yesterday’s report.
1.3 QEMU 11.1 Released: Adds RISC-V Big-Endian Support (Trend of the Past Three Days)
Date: 2026-08-11/12 Source: Linuxiac / Phoronix aggregation
QEMU 11.1 was released, adding RISC-V big-endian support along with ARM nested virtualization, UFS emulation, and other improvements. RISC-V big-endian support is meaningful for emulation validation of heterogeneous/specialized workloads, representing continued refinement of the RISC-V virtualization toolchain. The release window falls one day before the survey window, listed as a trend of the past three days.
1.4 Tenstorrent Ascalon XG Core GCC Patch + Open Source Project Watch
Date: 2026-08-12 (Phoronix report) Source: Phoronix aggregation
Tenstorrent submitted a GCC compiler patch for the Ascalon XG core (the centerpiece of its RISC-V server CPU product line), advancing formal GNU toolchain support for the core — another step in building the software ecosystem for RISC-V high-performance server cores (trend of the past three days; yesterday’s outlook already mentioned Tenstorrent’s export model differentiation). Also, active GitHub project watch (topic:risc-v, pushed within 24h): riscv/riscv-unified-db (209 stars, RISC-V Unified Database, updated 08-14), bbenchoff/AGaMEMnon (37 stars, AGM AG32 RISC-V MCU open-source SDK and embedded AGRV2K FPGA toolchain, created 08-15), w1ne/labwired-core (59 stars, ARM/RISC-V deterministic firmware emulator), etc. — small community projects continue to emerge.
II. Product and Ecosystem Developments
2.1 The 5th Dishui Lake China RISC-V Industry Forum: 40+ products showcased, mass production rate above 90%, 36 billion units shipped (Toutiao)
Date: Opens 2026-08-13, intensive coverage 08-13~14 Source: International Electronic Business / eet-china / Sina Finance / Jiwei
The results of the 5th Dishui Lake China RISC-V Industry Forum (Shanghai Lingang, opened August 13), previewed yesterday, landed in concentrated fashion today, becoming the biggest industry-side event of the day. VeriSilicon’s Dai Weimin disclosed: across four editions of the forum, 40 domestic RISC-V chips have been showcased cumulatively, with a mass production rate above 90%; this year’s forum conveyed industry signals — cumulative RISC-V chip shipments of 36 billion units, market share surpassing 30%, and penetration reaching 25%. The forum released 10 new domestic RISC-V chips, covering AI servers, robot motion control, automotive electronics, intelligent vision, network interfaces, and other directions (see 2.2~2.4 and Chapter III for details). Shanghai officials stated they will accelerate efforts to build a global RISC-V industry highland. International Electronic Business summarized it as “seeing RISC-V’s path to the mainstream through ten chips”: full coverage of the three major battlegrounds — embodied robotics, AI servers, and automotive electronics — marking the formation of an industry narrative in which domestic RISC-V transitions from “usable” to “mainstream.”
2.2 BlueCore Computing LX500: World’s first mass-produced RISC-V server CPU (48 cores, 75 TOPS)
Date: 2026-08-13 (debuted at Dishui Lake Forum) Source: eet-china / EDN China / Xinzhi Xun
BlueCore Computing released the LX500 at the Dishui Lake Forum, claiming it as the “world’s first mass-produced RISC-V server CPU”: 48 cores, 75 TOPS of AI compute, adopting a “compute-connectivity fusion” (CPU and AI acceleration fusion) architecture, focused on compute utilization, and ending the narrative of a separated “CPU + accelerator card” architecture. The company previously established a RISC-V + AI compute-connectivity fusion CPU joint innovation lab with Lenovo, and Lenovo also launched the world’s first open-architecture AI server (reported in July); BlueCore Computing’s Pre-B round received over RMB 300 million in exclusive investment from Longqiu Capital (July 1). If “mass-produced server CPU” holds true, this is a landmark moment for RISC-V’s push into the main compute node of data centers, forming a “compute + management” dual-track echo with yesterday’s StarFive BMC entry into the data center management side.
2.3 StarFive JH-B100 series: RISC-V BMC chips accelerate domestic substitution (follow-up to yesterday’s report, model confirmed)
Date: 2026-08-13/14 Source: EDN China / eet-china / Sohu
Yesterday’s industry news that “StarFive bets on AI data center BMC” materialized today into a concrete product: StarFive’s JH-B100 series RISC-V BMC chips (the earlier “Fang·Jinghong-B100” was a contender for the 2026 China IC Design Achievement Award) were reported by multiple Chinese media outlets under headlines such as “the invisible lifeline of intelligent computing centers, breaking global monopoly,” noting that it targets the explosive BMC demand in intelligent computing centers to accelerate domestic substitution. The BMC market has long been dominated by Aspeed; a RISC-V solution entering server out-of-band management is a low-cost, high-value path for the ecosystem to enter data centers.
2.4 Allwinner V861 and Timesintelli PT153S: Vision edge and NIC chips
Date: 2026-08-13 Source: eet-china V861 / eet-china Timesintelli / Sohu PT153S
- Allwinner V861: A new product at the Dishui Lake Forum, redefining intelligent vision edge chips with RISC-V + AI, focused on on-device visual understanding from “seeing clearly” to “understanding,” targeting intelligent security/vision IoT scenarios.
- Timesintelli PT153S: A fully domestic USB gigabit NIC chip based on RISC-V, claiming over one million units shipped in 3 months, leveraging the “from edge AI to high-speed interfaces” path to drive domestic substitution in NIC chips — RISC-V entering the network interface controller niche market.
2.5 ESP32-C6 Home Automation Kit (LinuxGizmos)
Date: 2026-08-14 (04:03 UTC) Source: LinuxGizmos
LinuxGizmos reported on a home automation kit based on the ESP32-C6 (Espressif RISC-V core MCU): integrating ESPHome and modular sensors, targeting smart home DIY scenarios. This is a routine new product in the ESP32-C series RISC-V ecosystem, corroborating the continued volume growth of Espressif RISC-V MCUs in the consumer/home market.
III. Domestic Team Updates and Deep Dives
3.1 SpacemiT: K3 Sets Four Global Firsts, RVA23 Lands, Robot Motion Control + DeepSeek Harness Documentation
Date: 2026-08-13 (release coverage) ~ 08-14 (GitHub doc update) Source: EDN China / eet-china / 芯智讯 / docs-ai GitHub
SpacemiT’s K3 became the most closely watched new product at the Dishui Lake Forum: multiple Chinese media outlets reported its “four global firsts” (RVA23 standard implementation, edge AI compute, and other dimensions). eet-china ran the headline “From RVA23 Standard Implementation to Robot Motion Control in Practice,” while EDN titled its piece “Ushering in the CPU 2.0 Era” — K3 is positioned as a flagship RISC-V edge AI SoC, with robot motion control as one of its primary deployment scenarios. On the software side, progress continues in parallel: spacemit-com/docs-ai merged the Chinese documentation for the DeepSeek inference harness (ds-harness, PR #157/#158) at 20:57 Beijing time on 08-14, and ai-sdk updated its vision submodule on its daily routine (latest at 18:16 Beijing time on 08-14), accelerating the documentation of the K3 edge large-model inference (DeepSeek family) toolchain. Combined with the previously reported FlagGems-RACE K1 backend 90+ operator matrix (yesterday’s report), SpacemiT’s three-in-one edge AI stack of “chip + operator library + inference documentation” is taking shape.
3.2 ESWIN Computing EAI8800: RISC-V Automotive-Grade Camera Monitor System (CMS) Dedicated Chip
Date: 2026-08-13 Source: SEMI 大半导体产业网 / eet-china / EDN China
ESWIN Computing’s Guo Guangkuo unveiled the EAI8800 at the Dishui Lake Forum: a RISC-V architecture-based automotive-grade Camera Monitor System (CMS) chip solution, focused on low latency and cost reduction, claiming resilience to DDR price hikes (through architecture/memory solution optimization). CMS is a new track in which smart vehicles replace traditional optical rearview mirrors. ESWIN Computing is concurrently in the Hong Kong IPO process (with the “first RISC-V architecture stock” narrative, its third attempt at the HKEX with cumulative losses of RMB 4.9 billion over three years, covered in multiple reports from 8/10-14). Its automotive-grade AI MCU (EAM2011) has entered the supply chain for Zunjie intelligent seats, and automotive electronics is the company’s main commercialization focus.
3.3 Gejian Semiconductor: 500-Nanosecond Current Loop, Single Chip Driving 25 Degrees of Freedom — A RISC-V Robot Motion Control Foundation
Date: 2026-08-13 Source: eet-china
Gejian Semiconductor showcased its RISC-V robot motion control solution at the Dishui Lake Forum: a 500-nanosecond current loop (current loop control period) and a single chip driving 25 degrees of freedom, pursuing a real-time control DSP approach (its GS32 series DSP received ASIL-B product certification in June, targeting high-end real-time control). This provides a domestic alternative at the “motion control foundation” layer of embodied intelligence for RISC-V — see Chapter IV for the dedicated section.
3.4 KaixinHong Completes Over RMB 100 Million Seed Round: Funds Directed at XiangShan IP Core Architecture Upgrade
Date: 2026-08-11 (past three-day trend) Source: 观点网
KaixinHong completed a seed round of over RMB 100 million, with funds explicitly directed at upgrading the XiangShan IP core architecture — the commercialization entity for the XiangShan open-source high-performance core has secured early-stage capital support, echoing the XiangShan project team’s recent full-stack iteration (see 1.2). This is news from August 11, at the edge of the window, and is included as a past three-day trend.
3.5 Snapshot of Domestic Team Organization Activity (GitHub API, Within Window)
- XiangShan OpenXiangShan: XiangShan pushed at 08-14 16:46 UTC (csr fix, see 1.2); XSCache (10h), difftest/GEM5/NEMU (15h) also active.
- SpacemiT spacemit-com: docs-ai (pushed 08-14 13:00 UTC, DeepSeek harness), ai-sdk (08-14 10:16 UTC, routine vision submodule update), model-zoo-vision/spine-runtime (updated within 16h) — high-frequency full-stack activity.
- Sophgo sophgo: sophon-demo merged ArcFace support for BM1688 (SE9-16)/CV186X (SE9-8) platforms at 08-14 07:25 UTC, sophon-tools updated 11h ago — edge AI inference examples continue to expand.
- Espressif espressif: llvm-project (0h), esp-idf-security-dashboard (0h), esp-nn (9h), esp-mqtt (8h) — toolchain and security infrastructure active.
- T-Head XUANTIE-RV: no new pushes within the window (damo-rv-priv-ats 39h ago, riscv-aosp 46h ago), normal cadence.
- Nuclei Nuclei-Software: no new pushes within the window (e603_hbird etc. 89h ago), consistent with its usual cadence.
- ESWIN eswincomputing: most recent push still on 07-14 (about 31 days ago), silent on the public repository side, with recent activity concentrated on the product and IPO side (see 3.2).
IV. Focus Area Deep Dive: Embodied Intelligence and Robotics
4.1 Dishui Lake Forum Releases Dense Robot Signals: Motion Control Chips Become a New Battleground for Domestic RISC-V
Multiple new products at the Dishui Lake Forum point to embodied intelligence: Gejian Semiconductor’s robot motion control solution with a single chip driving 25 degrees of freedom and a 500-nanosecond current loop (see 3.3) is the most concrete motion-control-level product signal within the window — the current loop period is the core metric of motion control real-time performance, and the 500-nanosecond level benchmarks against high-end servo control; SpacemiT K3 lists robot motion control as one of its primary scenarios (see 3.1), continuing spacemit-robotics’ existing layout in LeRobot (SmolVLA/ACT edge deployment) and humanoid robots (humanoid_unitree_g1); both International Electronic Business’ “RISC-V’s Path to the Mainstream Through Ten Chips” and Sina’s 8/14 overview “Servers, AI and Robots: China’s RISC-V Next Stop” list robotics as one of RISC-V’s three main markets. Motion control (real-time control DSP/MCU) and edge AI (VLA model inference) constitute the two parallel mainlines of RISC-V embodied intelligence, with the former seeing substantive new product launches this week.
4.2 Ecosystem-Side Support
Progress on high-performance cores and operator libraries from XiangShan/SpacemiT and others (see 1.2, 3.1) continues to provide the foundation for robot edge inference; the Gejian GS32 series has obtained ASIL-B certification (June), and automotive-grade real-time control chips also provide a certification basis for reuse in robot joint control.
V. Summary and Trend Observations
- Domestic RISC-V enters the “mainstream narrative” stage: The Dishui Lake Forum’s industry data — “36 billion units shipped, over 30% market share, over 90% mass production rate” — along with 10 new products (server CPU, robot motion control, automotive CMS, vision edge, NIC, BMC) showcased in a concentrated manner, covering the three major battlegrounds of AI servers, embodied robots, and automotive electronics. The narrative of domestic RISC-V transitioning from “usable” to “mainstream” took shape this week. Together with yesterday’s SiFive SKL open-sourcing (an arms race in software kernel libraries), this points to: the RISC-V hardware ecosystem is already rich enough, and the center of competition is migrating toward software stacks and industry deployment.
- A mass-production-grade node emerges on the RISC-V server path: BlueCore LX500 (48 cores, 75 TOPS, claimed as the world’s first mass-produced RISC-V server CPU) and StarFive JH-B100 BMC focused attention on the same day, forming a dual-track entry into the data center of “main compute + out-of-band management”; if the former’s mass production materializes as claimed, it will compete on the same stage as Tenstorrent Ascalon and T-Head XuanTie server cores (previously reported).
- Security and trust building becomes a new topic: A USENIX Security 26 paper publicly verified that Spectre holds on commercial out-of-order RISC-V silicon (including domestic C910/C920), and pointed out the specific software flaw of missing barriers in the BPF JIT. For RISC-V to enter the server/cloud trust boundary, security auditing and hardening (prediction barriers, firmware default configurations, JIT fixes) must proceed in parallel with the performance narrative, and related defense work deserves continued tracking.
- The embodied intelligence motion control layer welcomes domestic solutions: Gejian Semiconductor’s 500-nanosecond current loop/25-degree-of-freedom motion control chip and SpacemiT K3’s robot motion control positioning mark a breakthrough for RISC-V in the robot “motion control foundation” (previously mostly occupied by DSPs/dedicated MCUs), forming a complete deployment path together with edge AI inference (LeRobot adaptation).
- Commercialization of open-source high-performance cores accelerates: KaixinHong’s over RMB 100 million seed round directed at XiangShan IP core architecture upgrade, with XiangShan continuously merging correctness fixes within the window (satp flush instruction fetch error), further clarifying the model of “community iteration + commercial company undertaking” for open-source cores.
Limitations note: Most Dishui Lake Forum new products are based on release statements, and specific parameters should be based on official vendor data (the LX500 “mass production” timeline and the specific dimensions of K3’s “four firsts” await official white papers); original sites such as eet-china/EDN have anti-scraping measures, so body details are mainly based on headlines and multi-source cross-referencing; the Beijing chip startup incubated by NetEase completing over RMB 2 billion in Series B funding (36Kr/Zhidongxi, 8/14) is noted only as industry capital activity because its instruction set direction cannot be confirmed, and is not included in the main text; this report’s GitHub data is based on the unauthenticated API (completed within the 60 req/h rate limit).
Appendix: Complete Source List
| No. | Event | Source Link |
|---|---|---|
| 1 | Spectre on RISC-V Silicon paper blog | Link |
| 2 | Spectre RISC-V coverage (The Register) | Link |
| 3 | Spectre RISC-V coverage (SC Media) | Link |
| 4 | XiangShan GitHub | Link |
| 5 | QEMU 11.1 RISC-V big-endian (Linuxiac) | Link |
| 6 | Tenstorrent Ascalon GCC (Phoronix) | Link |
| 7 | Dishui Lake Forum industry data (International Electronic Business) | Link |
| 8 | Dishui Lake Forum opening (eet-china) | Link |
| 9 | 10 new products unveiled (Sina Finance) | Link |
| 10 | On the ground at Dishui Lake Forum (Jiwei) | Link |
| 11 | Blue Core LX500 (eet-china) | Link |
| 12 | Blue Core LX500 first mass-produced server CPU (EDN) | Link |
| 13 | Blue Core LX500 48-core 75TOPS (Xinzhi Xun) | Link |
| 14 | StarFive JH-B100 BMC (EDN) | Link |
| 15 | RISC-V BMC market shake-up (eet-china) | Link |
| 16 | StarFive JH-B100 domestic substitution (Sohu) | Link |
| 17 | SpacemiT K3 four global firsts (EDN) | Link |
| 18 | SpacemiT K3 from RVA23 to robot motion control (eet-china) | Link |
| 19 | SpacemiT K3 debut (Xinzhi Xun) | Link |
| 20 | SpacemiT docs-ai GitHub | Link |
| 21 | ESWIN EAI8800 (SEMI China) | Link |
| 22 | EAI8800 CMS track (eet-china) | Link |
| 23 | EAI8800 unfazed by DDR price hikes (EDN) | Link |
| 24 | Gejian Semiconductor robot motion control (eet-china) | Link |
| 25 | Allwinner V861 intelligent vision (eet-china) | Link |
| 26 | Timesintelli PT153S NIC chip (Sohu) | Link |
| 27 | Kaixin Hong seed round (Guandian) | Link |
| 28 | ESP32-C6 home automation kit (LinuxGizmos) | Link |
| 29 | Servers, AI and robots: the next stop for China’s RISC-V (Sina) | Link |
| 30 | The road to RISC-V mainstream, seen through ten chips (International Electronic Business) | Link |
| 31 | Shanghai builds a global RISC-V industry highland (Xinzhi Xun) | Link |
| 32 | RISC-V: They Should Have Known Better (dmitry.gr, trending on HN) | Link |
| 33 | AGaMEMnon open-source SDK (GitHub) | Link |
| 34 | NetEase-incubated chip startup raises over RMB 2B in Series B (Zhidx) | Link |