Research window: Past 24 hours (2026-08-13 08:24 ~ 2026-08-14 08:20 Beijing Time) Sources: HN, Google News aggregation, CNX Software, Jon Peddie Research, SiFive official blog, HPCwire reprints, finance.biggo.com (DIGITIMES-affiliated aggregation), GitHub API (T-Head/XiangShan/SpacemiT/Sophgo/Nuclei/Espressif/ESWIN), etc. (see appendix)

I. Open-Source Community and Kernel/Release Updates

1.1 SiFive Open-Sources Kernel Library (SKL): A General-Purpose High-Performance Kernel Library for RVV (Today’s Headline)

Date: 2026-08-13 (official blog post; same-day coverage from JPR/TipRanks and others)　Source: SiFive Official Blog / Jon Peddie Research

SiFive announced that SKL (SiFive Kernel Library), the optimized kernel library used in its internal performance benchmark demos, is now open-sourced under the MIT license. SKL is a highly optimized collection of compute kernels targeting the RISC-V Vector extension (RVV) and SiFive’s proprietary matrix engine extensions (the Xsfmm series). It is designed around a “single-file, independently extractable” principle (copying the three files kernel.c + kernel.h + skl-common.h is enough to embed it in any project), has no libc dependency and performs no memory allocation/IO/system calls, and can be integrated wholesale as a Git submodule. It currently covers AI/ML performance hotspots including matrix multiplication (GEMM, with FP16/BF16/INT8 quantization), nonlinear activations (exp/softmax/SiLU/GELU), depthwise convolution, data movement, and low-precision format conversion, and provides inline-assembly-level pipeline specializations for the SiFive X390 microarchitecture while retaining generic RVV vectorized versions. SKL is positioned to become the underlying compute foundation for frameworks such as vLLM (paged-attention rewrites and operator replacement) and PyTorch ATen (custom backend delegation)—that is, a “cuDNN/MKL-style” common kernel layer for the RISC-V ecosystem, offering a unified convergence point through which different vendors can distribute their own processor-specific implementations for their hardware. This is another major open-source software ecosystem move by SiFive following last year’s Freedom SDK, aimed directly at the performance competitiveness of LLM inference on the RISC-V platform.

1.2 XiangShan High-Performance Core Continues to Improve: BERTi Fixes, Faster Elaboration, MainBtb Improvements

Date: 2026-08-13 (commits at 11:11/09:26/02:17 UTC)　Source: OpenXiangShan/XiangShan GitHub

The XiangShan open-source high-performance RISC-V processor (7,187 stars) merged several commits during the window: perf(berti): bugfix and enhance (#5965) fixes and enhances BERTi (a branch-prediction-related module); build(elaboration): add a parameter cache to speed up the elaboration (#6336) accelerates the Chisel elaboration compile flow via a parameter cache; and area(MainBtb): use attribute to represent valid (#6350) optimizes the valid-bit representation of the main branch target buffer. On the same day, peripheral repositories including XSCache, difftest, NEMU, CoupledL2, GEM5, env-scripts, and XiangShanLab all saw routine pushes (active throughout 08-13), indicating that the XiangShan project team is in a full-stack continuous iteration cadence; on the CI side, the new gcc15-spec26 checkpoint and xscc weekly regression automation are also being advanced.

1.3 T-Head DAMO Academy Releases RISC-V Privileged Architecture Compliance Test Framework damo-rv-priv-ats (Continuously Updated During the Window)

Date: 2026-08-13 (updated 09:27 UTC)　Source: XUANTIE-RV/damo-rv-priv-ats GitHub

The DAMO Academy RISC-V privileged architecture test framework maintained by T-Head (the XUANTIE-RV org) merged Add whisper support and update CI (#23) during the window. The project (created 2026-06, written in C, continuously active) is a bare-metal compliance test framework: it covers 90+ privileged extensions in the RISC-V privileged specification, with each extension compiled into a standalone ELF binary that can run directly on a hardware DUT or on QEMU/Sail/Spike simulators, switching targets (including FPGA/haps) simply by changing the build configuration through a platform abstraction layer, with zero operating system dependency. The repository includes built-in SPEC (specification excerpts) and NORM (specification requirement ID → clause mapping) directories, forming a three-layer traceability chain of “specification clause—test plan—test case.” The recent commit sequence shows that the Hypervisor extension test suite (CSR/interrupt/exception grouping, Zicfiss compatibility) is being intensively expanded, reflecting T-Head’s systematic investment in privileged architecture compliance verification.

II. Product and Ecosystem Updates

2.1 WCH Releases CH32V407/467: RVV Vector MCUs Integrating Ethernet MAC+PHY and USB HS PHY

Date: 2026-08-13　Source: CNX Software / hackster.io

WCH (Nanjing Qinheng Microelectronics) has released the CH32V407 and CH32V467, a new generation of 200 MHz RISC-V microcontrollers. Both are based on the in-house QingKe V3V core (32-bit RISC-V IMACV-X custom extensions, supporting the RVV vector instruction set), achieving 4.11 CoreMark/MHz, which the company claims outperforms a typical Arm Cortex-M4. The key difference: the CH32V467 offers 4/8 MB of on-chip PSRAM (targeting display/HMI applications), while the CH32V407 does not. On-chip peripherals include a 100 Mbps Ethernet MAC + 10/100 Mbps PHY, two USB 2.0 High-Speed (480 Mbps) host/device interfaces (with built-in PHY), an LCD-TFT controller (LTDC), a 150 MHz DVP camera interface, CAN 2.0B, I3C, 10 USARTs, 77 mappable IOs, and dual 12-bit ADC/DAC, targeting industrial IoT and edge AI. The chip consolidates what previously required discrete solutions (MCU + external PHY/PSRAM) into a single package, and with vector extension support it is cost-competitive in edge AI (on-device inference) and industrial networking scenarios. Beyond the ESP32 ecosystem, the RISC-V MCU “high integration + vector computing” path has gained another entrant.

2.2 Spain’s Openchip BER10: Europe’s First Supercomputing-Oriented RISC-V Chip Draws Continued Attention (Follow-up)

Date: 2026-08-13 (reported 09:33 UTC; chip first reported 2026-07-30 by HPCwire)　Source: RUSSPAIN.com / first report HPCwire

The BER10 chip from Catalan chip startup Openchip (which previously received a €115 million investment from Spain’s strategic fund SETT) continued to appear in the news this week, with RUSSPAIN and others following up today under the headline “Europe’s first RISC-V supercomputing chip.” BER10 is positioned as a RISC-V processor for AI, HPC, and critical infrastructure, and is a flagship project under the EU’s “digital sovereignty” strategy (previously described by Diari ARA as “the foundation of Europe’s digital sovereignty”). The story was first reported on July 30 (HPCwire); this is subsequent coverage within the window, reflecting the latest attention on Europe’s RISC-V high-performance computing roadmap.

2.3 RISC-V Camp Enters the BMC Chip Market: StarFive Bets on AI Data Center Management

Date: 2026-08-13 (07:35 UTC)　Source: finance.biggo.com (DIGITIMES-affiliated aggregator)

Industry reports indicate that the RISC-V camp is moving into the server baseboard management controller (BMC) chip market, with StarFive betting on AI data center management. BMC is the core chip for server remote management (out-of-band monitoring, firmware management, power control), long dominated by traditional vendors such as Aspeed, with a stable market landscape; RISC-V is entering this field with its open instruction set, controllable supply chain, and customization flexibility, aligning with data center demand for “domestically developed + secure and trusted” management chips. StarFive has previously built out its JH series of application processors (JH7110 and others), and extending into BMC/server management chips signals a strategic expansion from consumer/edge into the data center infrastructure-grade market. This is an industry development (aggregated source); specific chip models and mass production timelines have not yet been disclosed and require follow-up on official announcements.

III. Domestic Team Updates and Deep Dives

3.1 SpacemiT: FlagGems RACE adaptation continues to deepen, K1 backend operator matrix takes shape

Date: 2026-08-13 (fork repo pushed_at 07:47 UTC)　Source: spacemit-com/FlagGems-RACE GitHub

FlagGems-RACE maintained by SpacemiT (spacemit-com) (forked from BAAI’s RACE-org/FlagGems, i.e., the RACE version of the FlagOS ecosystem’s core operator library) continued pushing within the window, and its spacemit-backend-ops branch has now formed a complete K1 (SpacemiT K1 RISC-V SoC) backend: src/flag_gems/runtime/backend/_spacemit/ops/ contains 90+ operator files including abs/add/addmm/amax/argmax, along with heuristics configurations and fused operator modules. The commit history shows that in July it completed the “restore operator registration + DISABLE_SPACEMIT_OPS switch” mechanism (supporting proper fallback when the spacemit backend is not enabled), and integrated device attribute (total_memory) reporting. This marks SpacemiT’s deep adaptation of the FlagOS Triton operator library (FlagGems) to its own K1 chip: under BAAI’s “unified open-source AI software stack” framework, SpacemiT takes on the role of landing operators on the RISC-V hardware backend. Combined with the daily routine updates of the ai-sdk submodule (vision) (latest at 08-13 12:27 UTC), SpacemiT’s AI software stack is in a state of high-frequency iteration.

3.2 Snapshot of organizational activity: XiangShan / T-Head / Sophgo / Espressif / Nuclei / ESWIN

  • XiangShan OpenXiangShan: See Section 1.2; the main XiangShan repository still had pushes at 08-14 01:36 UTC, with the entire project active.
  • T-Head XUANTIE-RV: Besides damo-rv-priv-ats, riscv-aosp (Android port, 481 stars) had a push at 08-13 02:41 UTC, zero_stage_boot was updated on 08-12; opensbi was updated on 08-10.
  • Sophgo sophgo: sophon-tools (08-13 09:54 UTC), edk2-platforms (09:36), manifest (04:54), and build (04:52) continued pushing; the boot chain (zsbl) was updated on 08-12, with BSP engineering active.
  • Espressif espressif: llvm-project (284 stars, 08-14 00:08 UTC), esp-tflite-micro (687 stars, 08-13 17:40), esp-idf (18,773 stars, 17:38), and openocd-esp32 saw high-frequency pushes — toolchain and inference stack are Espressif’s main investment directions for RISC-V (ESP32-C series).
  • Nuclei Nuclei-Software: Over the past week, e603_hbird (Verilog Hummingbird E603, 67 stars) was pushed on 08-07, nuclei-ai-models (AI model examples) was updated on 08-07, and nuclei-linux-sdk was updated on 08-05; no new pushes within the window, a normal pace.
  • ESWIN Computing eswincomputing: The most recent push was on 07-14 (routine sync of u-boot/linux-stable/opensbi), with no new activity within the window; its IPO process and automotive-grade AI MCU applications (EAM2011) remain recent hot topics (see yesterday’s report).

IV. Special Chapter on Key Directions: Embodied Intelligence and Robotics

No new embodied intelligence/robotics-specific events within the window, maintaining yesterday’s assessment: SpacemiT spacemit-robotics’ LeRobot adaptation (SmolVLA/ACT on-device deployment) remains the most concrete progress in the RISC-V embodied intelligence direction, with its last commit within the window on 08-10 (lerobot fix(onnx) hardening), while humanoid robot repositories such as reachy_mini/humanoid_unitree_g1 remain stable.

There are two new signals indirectly related to embodied intelligence: First, SiFive SKL open-sourcing (see 1.1) covers deep convolution and activation functions such as GELU/SiLU — these are precisely hot operators for vision-language-action (VLA) models and on-device perception inference; if SKL is integrated into PyTorch/vLLM as expected, it will provide a high-performance kernel foundation for RISC-V robot on-device inference. Second, WCH CH32V407/467 (see 2.1) features RVV vector support plus highly integrated peripherals (DVP camera, I3C, motor-control-related IO) targeting edge AI, suitable for low-cost RISC-V solutions in robot control/sensing front-ends.

Also note: the 5th Dishui Lake China RISC-V Industry Forum previewed yesterday (opening August 13, previously described as “10 domestic chip new products unveiled together”) had no independent reports of opening results as of the collection time (gnews Chinese sources were abnormal within the window, see limitations note); new product information needs follow-up tracking.

V. Summary and Trend Observations

  1. The software ecosystem has entered a “kernel library arms race” phase: SiFive SKL open-sourcing is the biggest event this week — the RISC-V ecosystem is replicating the x86/ARM path of “high-performance math kernel libraries” (benchmarking cuDNN/MKL), with vendors converging their respective microarchitecture-specific optimizations behind unified interfaces, directly serving LLM inference performance competition. This is a substantive positive for vLLM/PyTorch deployment on the RISC-V platform.
  2. Domestic high-performance core full-stack iteration continues unabated: Both XiangShan (BERTi/elaboration/CI infrastructure) and T-Head (privilege compliance test framework, Hypervisor test suite expansion) had substantive commits within the window; RISC-V high-performance processors are advancing on three fronts — “design—verification—compilation acceleration” — with engineering maturity continuing to improve.
  3. RISC-V is penetrating data center infrastructure: StarFive’s bet on BMC chips (AI data center management) echoes Openchip BER10 (European supercomputing) and Tenstorrent (export model differentiation, yesterday) — RISC-V is making multi-point breakthroughs from edge/embedded into infrastructure-level markets such as server management and HPC compute nodes.
  4. MCU vectorization and high integration proceed in parallel: WCH CH32V407/467 integrates RVV vector extension, Ethernet PHY, USB HS PHY, and large-capacity PSRAM on a single chip; its positioning at 4.11 CoreMark/MHz indicates that domestic RISC-V MCUs are attacking industrial IoT and edge AI with the dual selling points of “vector computing + highly integrated peripherals.”
  5. The RISC-V side of the FlagOS ecosystem has a clear undertaker: SpacemiT’s FlagGems K1 backend operator matrix has taken shape (90+ operators + switch mechanism); the landing of BAAI’s unified AI software stack on the RISC-V hardware side is being advanced by member vendors with divided responsibilities, dovetailing with the release cadence of the six FlagOS 2.1 components released in sync.

Limitations note: gnews Chinese retrieval (zh-CN region) was abnormal within the window (English worked normally, while all Chinese queries returned 0 results); domestic team coverage relied mainly on the GitHub API and English/aggregated sources, so the Dishui Lake Forum opening results and Chinese-language news from domestic vendors may be underreported; follow-up reports on StarFive BMC and BER10 are both aggregated sources or reprints, with details subject to the headline wording, and specific models/timelines pending official disclosure; the GitHub data in this report is based on the unauthenticated API (completed within the 60 req/h rate limit).

Appendix: Complete Source List

No. Event Source Link
1 SiFive Official Blog: Introducing SKL Link
2 SiFive SKL Open Source (Jon Peddie Research) Link
3 SiFive SKL Open Source (TipRanks) Link
4 WCH CH32V407/467 (CNX Software) Link
5 WCH CH32V407 Vector Extension and PSRAM (hackster.io) Link
6 Spain BER10 Follow-up Report (RUSSPAIN) Link
7 Openchip BER10 First Report (HPCwire, 2026-07-30) Link
8 StarFive BMC Chip (finance.biggo.com aggregation) Link
9 T-Head damo-rv-priv-ats Link
10 XiangShan Link
11 SpacemiT FlagGems-RACE (spacemit backend) Link
12 SpacemiT ai-sdk Link
13 Sophgo organization Link
14 Espressif organization Link
15 OpenXiangShan organization Link
16 XUANTIE-RV organization Link