RISC-V Daily Intelligence Report (2026-08-13)
Research window: Past 24 hours (2026-08-12 08:50 ~ 2026-08-13 08:24 Beijing time) Sources: HN, Google News aggregation, CNX Software, Phoronix, The Register, EE Times China, Sina Finance, ITHome, GitHub API, etc. (see appendix for details)
I. Open-Source Community and Kernel/Release Updates
1.1 USENIX Paper: Commercial Out-of-Order RISC-V Chips Susceptible to All Spectre Variants, Including Domestic XuanTie C910/C920 (Today’s Headline)
Date: 2026-08-13 (reported 08-12 20:42 UTC) Source: The Register
Researchers from Belgian and German universities have completed the paper “Spectre on RISC-V Silicon: Attacks and Defenses on Commercial Out-of-Order Processors,” accepted to the 35th USENIX Security Symposium. The findings directly refute the popular assumption that “the RISC-V architecture is too simple to be affected by Spectre”: commercial out-of-order RISC-V processors (SiFive P550, T-Head XuanTie C910/C920) are susceptible to all major Spectre variants, while in-order cores (SiFive U74, XuanTie C906/C908) show no vulnerabilities. The researchers implemented PoC attacks for all four Spectre classes—PHT/BTB/RSB/STL—on two chips, achieving 100% recall and over 97% precision, and leaked arbitrary Linux kernel memory on the XuanTie C910 at 338 B/s. The researchers emphasize that x86/ARM software mitigations cannot be directly ported (RISC-V lacks microarchitectural introspection interfaces, and ecosystem fragmentation makes unified mitigation difficult), requiring systematic work at the level of architectural primitives, hardware transparency, and ecosystem toolchains. Related patches have been merged into mainline upstream Linux (3) with 2 more under review; SiFive has addressed the P550-specific issue. For domestic RISC-V server and cloud scenarios, this is a direct warning about security baselines.
1.2 RISC-V Official Simulator and Test Suite Maintenance Updates
Date: 2026-08-12 (21:36/21:59 Beijing time) Source: riscv-isa-sim / riscv-tests / sail-riscv-tests
Routine updates in RISC-V software ecosystem infrastructure repositories during the window: the official ISA simulator Spike (riscv-isa-sim) merged build system cleanups (Boost detection moved up to the top-level configure, fixing duplicate link warnings and C99 designator warnings, PRs #2365/#2363/#2362); riscv-tests added a compatibility fix for debug tests to “accept GDB main thread identifiers” (#657); the sail-riscv-tests precompiled test suite was updated in sync. All are low-signal maintenance commits, part of the regular cadence of specification engineering, kept in sync with the RVA23 public review and unified database updates (riscv-unified-db).
II. Product and Ecosystem Updates
2.1 Tenstorrent Submits Ascalon XG GCC Patch: Likely an Export-Market SKU With Cryptography Removed
Date: 2026-08-13 (08-12 16:14 EDT) Source: Phoronix
Tenstorrent engineers submitted a patch to the GCC mailing list, publicly revealing for the first time a new core model, Ascalon XG—a new variant of the high-performance out-of-order RISC-V RVA23 core Ascalon X, aimed at upstream support in open-source GCC. The patch explicitly labels it “the global version of Ascalon X”: the only difference from Ascalon X is the removal of the zvkng vector cryptography extension, while everything else (rva23s64, zfbfmin, zfh, zvbc, zvfh, zvl256b, smaia, ssaia, etc.) remains intact, with the compiler target identifier tt-ascalon-xg. The removal of the cryptography extension and the reduced-throughput positioning are widely interpreted by the industry as a compliance SKU for export-control scenarios such as the Chinese market. This is another signal of the Tenstorrent Ascalon series’ positioning on the high-performance RISC-V CPU roadmap, and also indirectly confirms that export controls are driving model differentiation among high-performance RISC-V cores.
2.2 Apollo Launches $40 Official ESPHome Starter Kit Featuring RISC-V-Based ESP32-C6
Date: 2026-08-12 (18:55 Beijing Time) Source: CNX Software
Apollo Automation, in collaboration with the Open Home Foundation, has launched the first official ESPHome starter kit, priced at $40. The main control board is the ESPHome C6 Board, featuring the ESP32-C6-MINI-1 module (Espressif’s RISC-V core MCU, supporting 2.4GHz Wi-Fi 6, BLE, Thread/Zigbee), connected via two 14-pin FPC interfaces to four modules: the MH-SR602 PIR motion sensor, AHT20F temperature and humidity sensor, an RGB LED + buzzer notification module, and a button module, with USB-C power and an optional lithium battery. The kit emphasizes zero barriers to entry: paired with the ESPHome Device Builder desktop visual editor, it can be configured without writing YAML, and can run standalone or connect to Home Assistant. The ESP32-C6 (RISC-V) has become one of the de facto choices for official smart-home starter hardware, marking another instance of RISC-V MCU penetration into the consumer ecosystem.
(Note: The QEMU 11.1 release with its RISC-V big-endian support and K230 board-level emulation were covered in yesterday’s report and are not repeated today.)
III. Domestic Team Updates and Deep Dives
3.1 T-Head: Zhenwu AI chips cumulative shipments reach 560,000 units; Alibaba Cloud says capacity continues to rise
Date: 2026-08-12 (19:30 Beijing time) Source: EE Times China
EE Times China reports that as of April this year, T-Head’s Zhenwu AI chips have shipped a cumulative 560,000 units. Wang Zhaoyang, General Manager of Alibaba Cloud’s Global Data Center, stated publicly that T-Head’s capacity is gradually increasing, and that “what is highly certain for the future is that the capacity of domestically developed chips will continue to rise, with an ever-growing share, and the time needed for this capacity ramp will likely be less than three years.” This is a rare quantified statement from Alibaba Cloud on the pace of domestic self-developed chip capacity. Deep dive: T-Head is Alibaba’s wholly owned semiconductor entity, with a product line covering data center AI chips (Hanguang/Zhenwu), server CPUs (Yitian 710/730), and RISC-V processor IP (XuanTie series). Among these, the XuanTie RISC-V ecosystem (XUANTIE-RV organization) remained active this week — within the window, the zero_stage_boot repository (C-language zero-stage boot loader) was updated (08-12 19:18), while damo-rv-priv-ats and opensbi advanced in parallel, indicating that its RISC-V core and ecosystem engineering are being pursued in parallel with its AI chip business.
3.2 Xiaoduan Computing: Hundreds of millions of yuan Series A financing closed, headquarters relocated to Nanjing Jiangbei New Area, GigaDevice participated
Date: 2026-08-12 (18:01 Beijing time) Source: ITHome / PEdaily / Google News aggregation (Sina Finance)
Server CPU developer Xiaoduan Computing (founded in July 2022) announced that in July 2026 it completed the closing of a Series A round worth hundreds of millions of yuan, and simultaneously relocated its headquarters to Nanjing Jiangbei New Area. The round was led by Mingzhe Capital and Xianxiang Capital together with a leading VC, with participation from CSC Capital, BOC International, GigaDevice, Zhichen Capital, Zhuoyuan Asia, Shouzheng Capital, Dingxin Capital, among others — among them GigaDevice is a major domestic RISC-V MCU (GD32V series) vendor, and its participation confirms industrial capital’s bet on the localization of server CPUs. The company’s strategy is dual-track in parallel: on one hand, building its first-generation product BlueDot V1 based on the ARM v9 instruction set and Neoverse V3 cores (enhancing vector computation, out-of-order pipelines, and memory interconnect bandwidth, targeting cloud and edge AI inference); on the other hand, making forward-looking arrangements in RISC-V CPU architecture. The raised funds will be invested in BlueDot V1 tape-out verification and small-batch trial production by the end of 2026. The domestic inference server CPU track has gained another new player.
3.3 ESWIN Computing: Third attempt at the Hong Kong Stock Exchange, “first RISC-V stock” draws attention over continuous headcount reduction
Date: 2026-08-12 (18:58 Beijing time) Source: Google News aggregation (Sina Finance)
Sina Finance published a long-form analysis of the operational details behind ESWIN Computing’s third filing with the Hong Kong Stock Exchange: as a candidate for “the first RISC-V architecture stock,” the company’s revenue has continued to grow but its three-year cumulative loss stands at about 4.9 billion yuan, its customers are highly concentrated, and a continuous reduction in employee headcount has become a market focal point. Combined with previously disclosed information (the launch of its third Hong Kong listing attempt on August 7-8, and parent company Xi’an ESWIN’s 6.5 billion yuan capital increase for the Wuhan 12-inch wafer base), the ESWIN Group is advancing capital operations on dual tracks of “materials capacity expansion + computing chip IPO.” The relationship between changes in employee scale and the pace of R&D investment, as well as the ramp-up progress of its RISC-V automotive-grade MCU (EAM2011 deployed in the Zunjie V800), will be key points for follow-up tracking.
3.4 SpacemiT: AI SDK updates concentrated, robot learning framework LeRobot adaptation to K3 continues to advance
Date: 2026-08-12 (20:32 Beijing time) Source: spacemit-com/ai-sdk / spacemit-robotics/lerobot / spacemit-com/docs-ros
Multiple repositories under the SpacemiT GitHub organization were updated in a concentrated manner within the window: AI SDK (a collection of AI capabilities for K-series chips, organized as Git submodules) updated its computer vision, speech (VAD/ASR/TTS), LLM, and multimodal VLM components (08-12 20:32), while the model-zoo-vision vision model repository was updated in parallel (19:49); docs-chip/docs-buildroot documentation was updated (15:41/16:23). On the robotics side (spacemit-robotics): the LeRobot repository merged the “harden SmolVLA K3 runtime” ONNX hardening commit on 08-10, following earlier landing of an ACT (Action Chunking with Transformers) FP16 deployment example and ONNX inference robot tests; docs-ros (ROS documentation) and the Robot SDK IMU driver (peripherals-imu) were updated on the same day. K3 (a RISC-V 8-core AI SoC) is expanding its adaptation surface across robot learning frameworks and the ROS ecosystem; see Chapter IV for details.
3.5 SOPHGO: Boot chain components updated in a concentrated manner
Date: 2026-08-12 (14:41~14:47 Beijing time) Source: sophgo/zsbl / sophgo/sophgo-edk2 / sophgo/bootloader-riscv / sophgo/sophon-tools
SOPHGO’s RISC-V chip boot chain components saw concentrated updates within the window: zsbl (RISC-V Zero Stage BootLoader, 08-12 14:47), sophgo-edk2 (UEFI firmware, 14:41), bootloader-riscv (08-11 13:59), and the linux_5.10 kernel branch (08-11 16:40) received successive commits; sophon-tools continued to be updated today (08-13 07:05) (the SophLiteOS AI Agent feature was reported yesterday). The systematic advancement of the boot chain (ZSBL→UEFI→kernel) typically corresponds to the firmware readiness stage of a new chip platform, and can be seen as an engineering signal of SOPHGO’s mass-production preparation for a new platform.
3.6 Nuclei: Filing for the NEEQ Innovation Tier, targeted fundraising of 42 million yuan (trend over the past 3 days)
Date: 2026-08-10 Source: Google News aggregation (Sina Finance)
Leading domestic RISC-V CPU IP vendor Nuclei has filed for the NEEQ Innovation Tier, planning a targeted fundraising of 42 million yuan (reported by Sina Finance on August 10, falling before this window and included as a trend over the past 3 days). Capital-side developments are in step with the R&D side: on GitHub, the Nuclei-Software organization recently updated the Lauterbach TRACE32 debug script repository (lauterbach-startup, 08-11), the RV64GC Linux-capable core e603_hbird (08-07), and nuclei-ai-models (08-07), indicating that its complete layout spanning IP cores, debug toolchains, and AI model libraries continues to expand.
IV. Special Chapter on Embodied Intelligence and Robotics
The biggest highlight within the window: SpacemiT’s continued implementation on robot learning frameworks.
- LeRobot adaptation progress (spacemit-robotics/lerobot, commit on 08-10 16:20): merged “fix(onnx): harden SmolVLA K3 runtime” (#17) — SmolVLA is a lightweight vision-language-action (VLA) model, which SpacemiT deploys and hardens with an ONNX runtime on its K3 RISC-V SoC; previously it had landed an ACT (Action Chunking with Transformers) SpineTorch FP16 deployment example (#16) and ONNX inference robot tests (#14). Together with the SmolVLA ONNX pipeline since June (#12/#13), K3 has formed a “VLA + ACT dual-track” on-device deployment matrix for robot learning models. Within the same organization there are also humanoid robot adaptation repositories such as humanoid_unitree_g1/go1 (Unitree), humanoid_tiangong (Tiangong), and reachy_mini, along with Robot SDK motor/IMU peripheral drivers, constituting a complete robot software stack.
- ROS ecosystem: the docs-ros documentation repository was updated (08-10), complementing the ROS examples in the AI SDK.
- Dishui Lake Forum opens today: The 5th Dishui Lake China RISC-V Industry Forum is being held today (August 13), having previously been previewed as featuring “10 new domestic chip products unveiled together” (reported by Sina Finance on August 8); embodied intelligence-related new chip products are worth tracking after the event; as of the collection time of this report (08:24), there are no reports yet of results from the opening day.
- Adjacent signal: ESWIN’s EAM2011 automotive-grade AI MCU’s posture recognition application in the Zunjie V800 smart seat (reported yesterday); its “perception + dynamic adaptation” technology stack is shared with robot control, and can serve as a reference for the localization path of embodied intelligence chips.
V. Summary and Trend Observations
- Security baseline sounds the alarm: A USENIX paper confirms that commercial out-of-order RISC-V chips (including the domestic XuanTie C910/C920) are susceptible to all Spectre variants, and that x86/ARM software mitigations cannot be directly ported. In the scaling process of RISC-V in high-performance computing and cloud scenarios, the construction of microarchitectural security primitives and ecosystem-level defense toolchains will become a key competitive dimension, and domestic out-of-order cores (XuanTie, XiangShan, etc.) especially need attention.
- Export controls reshape product lines: The public debut of Tenstorrent Ascalon XG’s “crypto-stripped export model,” combined with the U.S. Congress pushing to tighten controls on AI chip flows, means that a “domestic version/international version” split for high-performance RISC-V cores may become the norm, with domestic substitution windows and compliance pressure coexisting.
- Domestic server CPU financing is active: Xiaoduan’s Series A (with GigaDevice participating, BlueDot V1 trial production by year-end), Nuclei’s NEEQ fundraising, and ESWIN’s third Hong Kong listing attempt — capital is pouring intensively into the domestic CPU/RISC-V IP track, and the ARM-plus-RISC-V dual-track approach has become standard for a new generation of startups.
- Robotics direction advances steadily: SpacemiT’s LeRobot SmolVLA/ACT on-device deployment and ROS adaptation are the most concrete RISC-V embodied intelligence progress this week; the Dishui Lake Forum opens today, and information on new chip products after the event is worth continued tracking.
- Ecosystem infrastructure proceeds at a normal pace: Maintenance updates to Spike/riscv-tests and commits such as XuanTie’s zero_stage_boot show that both specification engineering and vendor engineering are advancing at a routine pace.
Limitations note: Google News Chinese-language search is heavily polluted by SEO noise (gambling/e-commerce/real estate entries have been removed in bulk); results from the opening day of the Dishui Lake Forum have not yet been reported, and tomorrow’s report will focus on tracking them; the details of ESWIN’s “continuous headcount reduction” are inferred from the headline and previously disclosed information, as the full text was not obtained (Sina’s original article is anti-scraping), and citations should follow the headline’s wording.
Appendix: Complete Source List
| No. | Event | Source Link |
|---|---|---|
| 1 | USENIX paper: Commercial out-of-order RISC-V chips affected by Spectre | Link |
| 2 | Tenstorrent Ascalon XG GCC patches | Link |
| 3 | Apollo ESP32-C6 ESPHome starter kit | Link |
| 4 | T-Head Zhenwu AI chip shipments reach 560,000 units | Link |
| 5 | Xiaoduan Computing Series A funding | Link |
| 6 | Xiaoduan Computing Series A (PEdaily) | Link |
| 7 | Xiaoduan Computing Series A (Sina Finance aggregation) | Link |
| 8 | ESWIN’s third attempt at HKEX listing (Sina Finance aggregation) | Link |
| 9 | Nuclei Technology applies for NEEQ Innovation Tier (Sina Finance aggregation) | Link |
| 10 | SpacemiT AI SDK | Link |
| 11 | SpacemiT LeRobot adaptation | Link |
| 12 | SpacemiT ROS documentation | Link |
| 13 | Sophgo boot chain (zsbl/edk2/bootloader) | Link |
| 14 | XuanTie zero_stage_boot | Link |
| 15 | Official RISC-V Spike simulator | Link |
| 16 | Official RISC-V riscv-tests | Link |
| 17 | Nuclei Nuclei-Software organization | Link |
| 18 | Dishui Lake Forum preview (Sina Finance aggregation) | Link |