Reporting period: October 12, 2026 (Monday) to October 16, 2026 (Friday), 5 working days in total

Sources: 5 issues of this publication’s daily FlagOS updates (10-12 / 10-13 / 10-14 / 10-15 / 10-16, no gaps). The 10-12 issue is the Monday morning briefing, with a research window starting from 10-10 09:40 (following the 10-10 make-up report for the adjusted holiday), so some weekend-period content (three FlagQuantum candidate releases, Biren placement, MetaX university open-source tour) is included in this report via that issue and labeled with its original date.

Editorial note: Covers five dimensions: versions and releases, components and code co-development, member units and vendor adaptation, ecosystem and community, and trend observations. The weekly totals are based on GitHub search reinforcement verification (org flagos-ai, merge date 10-12 00:00 to 10-16 23:59, Beijing time): 385 PRs merged, 525 PRs newly opened, 338 open PRs updated within the window; total repositories increased from 55 to 61. Summing the five daily reports by their respective windows gives 453 commits and 364 merges (the windows of each issue are contiguous, including the 44-hour weekend covered by the 10-12 issue).

I. Weekly Highlights

  • FlagQuantum 0.3 line closed out: 0.3.0 and 0.3.1 released on the same day (10-16): 0.3.0 was released at 13:34 Beijing time (PR #629), and 0.3.1 at 19:20 (PR #634); both fell after the 06:00 cutoff of that day’s daily report and are backfilled here through supplementary verification. 0.3.0 is the stable package for the 0.3 line — Stable ABI wheels for Python 3.10 to 3.12, artifacts for three platforms (Linux x86_64 / macOS arm64 / Windows amd64), resumable jobs on Jiuding and Quafu (with optional receipts and ordered multi-circuit results), and bilingual Chinese-English versions of the six-lesson workshop; 0.3.1 adds the flagquantum.services local research capability service (typed request validation and estimation, local CPU operations, a two-qubit Pauli-sum ground-state VQE path, and versioned evidence bundles) while keeping the 0.3.0 public API unchanged. From the three release candidates (10-10 rc1, 10-10 rc2, 10-11 rc3) to the final release, the whole process took 6 days.
  • FlagOS 2.3 cycle opened and moved into substantive commits (10-13 ~ 10-15): community #126 merged the 2.3 schedule on 10-13 — FEP merge deadline 2026-11-13 (hard gate), feature freeze and rc0 11-30, rc1 12-07, rc2 12-14, final freeze 12-25, GA 12-30; the freeze rules explicitly state that “the GA manifest only accepts existing-tag release sources,” and announce that 2.2’s “trunk cutoff time” fallback was a one-off exception and will not be carried forward. From 22:35 on 10-14 to 01:49 on 10-15, 11 FEPs were opened in a single night (#139 to #149), covering the offline installer, vLLM 0.28 ten-platform compatibility, SGLang 0.5.18, Megatron three-model and ViT training, TransformerEngine upstream plugin migration, Compressor calibration quantization, the LightX2V generation plugin, and Torch-FL coverage capabilities; the corresponding offline one-click installer merged into build-infra #1348 on 10-15 (+1085 lines, with zero network dependency at install time via pip install --no-index).
  • Kunlunxin’s three-stage leap: dropping CUDA-boxing, switching to native XPU, entering XPU3 batch work (10-12 ~ 10-14): Torch-FL #502, at 47 files +5347/-2443, replaced the CUDA-boxing approach just landed on 10-11 with a native XPU path (native kKunlunxin backend slot, a pure-C libxpurt device layer, and an xdnn-based operator layer); #503 added a P800 CI lane the same day, #504 turned the lane green within 24 hours, and #507 / #508 completed backend key fixes and build-test merging. Starting 10-13, FlagGems opened 14 XPU3 batches in a single day (capability-gating infrastructure #7098 and operator implementations #7103 to #7117), and FlagTree released the 0.7.1a1+xpu3.6 build line the same day — integration, batch implementation, and CI hosting were all in place within one week.
  • Torch-FL became the unified entry point for vendor integration: five new paths landed in one week (10-12 ~ 10-15): Tsingmicro’s “FlagGems-only” operator path (#492 / #493), Kunlunxin native XPU (#502), Iluvatar’s “FlagGems-primary” backend (#514, +3805/-40) and its native vendor backend (#527, ixdnn / ixblas C ABI, +3022/-174), Tsingmicro collective communication through FlagCX (#536), and Apple Silicon Metal / MPS (#516 / #528, becoming the 11th accelerator). Meanwhile the CI layer converged into a config-driven matrix with change-aware routing (#519 / #521 / #534), and a hardware-agnostic runtime consistency contract suite was started (#497, 35 files +1947/-91).
  • Six new repositories created in one week, expanding the portfolio from LLM operators to vision, speech, and compiler bridges (10-12 ~ 10-14): Trident (public on 10-12, an experimental MLIR/LLVM compiler bridge whose master commit history traces back to May, 274 commits in total), optest (10-13, operator testing infrastructure), FlagCV and the three speech-audio repos kaldi-triton / puAudioAnalysis-sino / librosa-sino (10-14); puAudioAnalysis-sino was renamed pyAudioAnalysis-sino on 10-16 and CNPort localization porting notes were added. Total organization repositories grew from 55 to 61 (plus FlagQAI, created 10-10 and covered in the 10-12 issue).
  • Cross-chip Day-0 has become a pipeline: MiniCPM-V 4.7 on twelve platforms, three members announcing in succession; Step 5 Preview from four vendors on the same day (10-13 ~ 10-15): On 10-13, ModelBest and OpenBMB open-sourced MiniCPM-V 4.7 (35B-A3B and 1B variants), with twelve-platform Day-0 coverage completed the same day via vLLM-plugin-FL and adaptation images published under the FlagRelease organization; MetaX (10-14, its 42nd model cumulatively), Tsingmicro (10-14, with Math_500 / GPQA_Diamond / MMLU_Pro aligned to NVIDIA baselines), and Iluvatar (10-15, 400-plus models cumulatively) published official validation reports in succession. On 10-15, the day StepFun open-sourced Step 5 Preview, four member vendors — Ascend, MetaX, Biren, and Moore Threads — announced support the same day.
  • Conference readiness (10-17 / 18) and event operations (10-12 ~ 10-16): The full conference agenda and attendee guide were published on 10-12 (with FlagOS 2.2 and the Liangzhi Cloud platform listed for on-site release), livestream pages for three sub-forums went live on 10-15, and the agendas for the hands-on workshop and the International AI Computing Cooperation Forum were made public, with more than 17,000 followers on the registration page; the MiniCPM inference throughput optimization challenge jointly run by MetaX and FlagOS opened registration on 10-16 (deadline 2026-11-10, first prize RMB 30,000, with free compute provided by MetaX); the community competition Track1 had two concentrated cleanup rounds during the week (19 items each on 10-12 and 10-13) and added 3 new contest kernel submissions.

II. Versions and Release Activity

FlagQuantum 0.3 line: from three consecutive release candidates to two official releases

  • rc1 (10-10 14:42): The first release candidate in the 0.3 series, packaging circuit composition and output API extensions, gradient and vector derivative APIs, OpenQASM import, compiler optimization levels, distributed workflows, and updates to the Jiuding / Quafu provider guides.
  • rc2 (10-10 20:38): Introduced the cp310-abi3 wheel (covering Python 3.10 through 3.12); the native CPU extension was aligned with the PyTorch 2.10 Stable ABI baseline (runtime verified on 2.13 / 2.14); bundled flagquantum-compiler-qsteed 0.2.0.
  • rc3 (10-11 08:52): A single cp310-abi3 wheel per platform; completed MSVC portability fixes (Stable ABI flag injection, OpenMP SIMD, bit lookup); pipeline verification passed on all three platforms: Linux / macOS / Windows.
  • 0.3.0 official release (10-16 13:34): The stable package for the 0.3 line, including Stable ABI wheels for three platforms, PyTorch-first quantum simulation / training / remote execution, resumable jobs on Jiuding and Quafu (optional receipts and ordered multi-circuit results), and a six-lesson workshop in both Chinese and English.
  • 0.3.1 (10-16 19:20): Added the local research capability service approved after the 0.3.0 artifact build — flagquantum.services discovery and description, typed request validation and estimation, local CPU operation execution, and structured evidence validation, along with a two-qubit Pauli-sum ground-state VQE path and versioned evidence bundles; the release notes explicitly state that this release does not include constructing molecular Hamiltonians from chemical specifications, does not include quantum hardware execution, and does not include an MCP server or agent runtime (the MCP adapter is released separately as an independent package).
  • Engineering support: FlagQuantum merged 13 PRs during the week, including the QCIS static importer (#622, 110 tests passing), Quafu multi-circuit single-job submission (#627), qubit ordering and accelerator support documentation (#628), and two release PRs (#629 / #634).

FlagGems: 5.5 development line opened; 5.4 is the current official line

  • Line opened: The v5.5.0.dev0 tag was created on 10-12 11:23, opening the next-generation development line after 5.4 (released 09-28), following the same approach as the 5.4 cycle.
  • Official line alignment: On 10-13, #7025 aligned the deb / rpm packaging baseline with the 5.4.0 release line, aligning release engineering with the code line.
  • Merge intensity: 142 PRs merged during the week, the highest in the organization; by merge date: 13 on 10-12, 24 on 10-13, 25 on 10-14, 29 on 10-15, and 51 on 10-16, rising day by day through the week.

FlagTree: two build lines refreshed and the daily wheel mechanism

  • Build lines: 0.7.1a1+iluvatar3.6 (10-12 10:46; the Iluvatar CoreX 4.5.0 line moved from 0.7.0 to the first alpha in the 0.7.1 series; build-infra #1333 synchronized the matrix) and 0.7.1a1+xpu3.6 (10-13 16:36; the XPU build line upgraded from 0.7.0+xpu3.6 of 09-24, including the XPU backend and internal triton sync #1330).
  • Compiler upgrade: The TileIR backend was upgraded to CUDA Tile IR 13.4 (#1352, +7939/-1383, including descriptor reduce / gather / scatter lowering and scaled-dot), merged on 10-15 while retaining the per-kernel NVIDIA / TileIR routing model.
  • Daily wheels: Overnight on 10-15, the nvidia build machine was provisioned and 12 build-flow fixes were completed, establishing two new policies — daily wheels are released with a “date-only” version number (#1362), and manual replacement of the day’s wheel is supported (#1364) — shifting the release cadence from version releases to continuous daily delivery.
  • Tag status: No new tags from 10-14 to 10-16; 27 PRs merged during the week.

FlagOS 2.3 cycle: schedule, freeze rules, and the first batch of FEPs

  • Schedule (merged 10-13, #126): FEP merge deadline 2026-11-13 (unmerged ones are marked Deferred and carried over, with no retroactive acceptance; submitting two weeks early is recommended); feature freeze and rc0 on 11-30 (requiring consistency across tag, manifest, and package metadata); rc1 on 12-07; rc2 on 12-14; final freeze on 12-25; GA on 12-30 (Go/No-Go is an RM written report plus TSC vote 48 hours before GA).
  • Freeze rules: The GA manifest accepts only existing-tag release sources; security patches, critical defects, and CI blockers may use the [URGENT] fast track (requires TSC approval); the graduation criterion is item-by-item acceptance against an executable Test Plan (commands, environment, expected results, covering multi-chip scenarios).
  • Milestones and SIGs: The 2.1 and 2.2 milestones are closed (2.2 GA on 09-28); 2.3 is in progress with a deadline of 12-30; 8 active SIGs (operator / compiler / network / framework / training / kernelgen / chip / edge), plus planned directions such as sig-benchmark, sig-os, and sig-riscv (experimental RISC-V support).
  • First batch of FEPs (11): FEP-0139 offline one-click installer, FEP-0140 vLLM multi-version platform compatibility, FEP-0141 SGLang platform upgrade and model support (including DeepSeek-V4 W8A8), FEP-0142 Compressor calibration quantization, FEP-0143 LightX2V multi-chip generation plugin, FEP-0144 Megatron three-model multi-platform training, FEP-0145 Megatron ViT co-located training, FEP-0146 TransformerEngine upstream plugin migration, FEP-0147 TE Triton and CUDA FSA backends, FEP-0148 Torch-FL coverage and execution capabilities, FEP-0149 Torch-FL Iluvatar platform support.

Release engineering and artifacts

  • 2.2 tag pinning: build-infra #1339 (10-13) changed the packaging ref / ver for each component from post / rc2 snapshots to the official release-2.2 tags (v5.4.0, v0.3.0, v0.4.0, v0.2.0), switching 2.2 release artifacts from verification snapshots to the official baseline.
  • Wheel directory automation: Early in the week, #1325 through #1331 completed registration and backfilling of all 20 FlagCX v0.14.0 wheels, added python / os / arch dimensions and a “record on release” hook, and built the flagos-compressor wheel release pipeline; starting 10-13, wheel-info.yaml was renamed to packages.yaml, and each package gained a source tarball download URL.
  • Release infrastructure: FlagTree package publishing moved to self-hosted runners (#1341, because hosted runners accessed Nexus at only tens of KB/s and large packages failed to upload four times); at container startup, FLAGTREE_VERSION dynamically selects the version, eliminating the need to rebuild upper-layer images (#1342).
  • Offline deployment: The implementation corresponding to FEP-0139 was merged on 10-15 in build-infra #1348, followed by 14 fixes and enhancements throughout the night (#1349 through #1364); the release-info site was redeployed and refreshed twice, at 10-13 18:53 and 10-15 17:43.
  • Tags and Release list for this week: See the table below (by merge date).
Time (Beijing time) Component Tag / Version Description
10-12 10:46 FlagTree 0.7.1a1+iluvatar3.6 First 0.7.1 alpha on the Iluvatar CoreX 4.5.0 build line
10-12 11:23 FlagGems v5.5.0.dev0 5.5 development line opened (5.4 remains the official line)
10-13 16:36 FlagTree 0.7.1a1+xpu3.6 Kunlunxin XPU build line refreshed
10-16 13:34 FlagQuantum v0.3.0 Stable official release of the 0.3 line
10-16 19:20 FlagQuantum v0.3.1 Added local research capability service and VQE path
  • Weekend continuation (10-10 / 10-11, covered in the 10-12 issue): Three FlagQuantum v0.3.0rc1, rc2, and rc3 release candidates; no other new tags organization-wide outside the window.

III. Components and Code Co-building

FlagGems (142 merges, highest across the organization)

  • Benchmark system migration (10-16, #7169): 196 benchmark files migrated from the legacy input_fn generator to the case_fn / build_inputs_fn dual-function model (BenchmarkCasePlan), adding 294 case definitions, +14910/-1567 across 490 files.
  • KernelGen (Nvidia) continues supplying: this week merged matrix_exp, _linalg_solve_ex, _pack_padded_sequence, _scaled_mm_v2 (10-12) and a ten-operator batch (_reshape_copy, grid_sampler, atleast_3d, special_modified_bessel_i1, mH, dstack, glu_jvp, geqrf, istft, select_copy, 10-15), plus newly added cartesian_prod, atleast_1d, batch_norm_elemt (10-16).
  • Kunlunxin XPU: 10-12 six fixes and optimizations (CI, fake_quantize family, hardsigmoid_ and channel_shuffle, FP8 benchmark skip, three-operator optimization); since 10-13 fourteen XPU3 PRs under review (capability gating #7098, operator implementations #7103 through #7117); 10-15 batch-2 performance PR #6662 merged (all_dim and batch_norm pass the 0.8x threshold, fixing import-time global side effects); 10-16 seven more merged including rshift / batch_norm, three-operator fixes, sign_ / alpha_dropout / max_dim, and the foreach scalar family.
  • Ascend (KMCompiler): index_fill grid capping (#6946), mul launch grid overflow on large contiguous inputs (#6949), addmm / bmm auto-blockify (#7013), replication_pad2d_backward coreDim capping (#7081), unsafe_index_put grid capping (#7033), embedding_spmdm (#7149), linalg_qr benchmark trimming and linalg_lu grid limits (#7125 / #7165).
  • DAMO XuanTie (thead / PPU): ADDMM / ADDMM_ / router GEMM / BMM optimized and BADDBMM added (#6859), PPU-ZW810E switched to a unified test container (#7176).
  • Moore Threads: warp-specialized SQMMA pipeline (mm / bmm / addmm / baddbmm, #7093); Enflame: Enflame S60 added to the ops test backend (#6917), gcu300 benchmark fix for inflated baselines caused by CPU fallback (#7054), a 28-file +3549/-593 Enflame large update under review (#7077).
  • Testing and quality: weekly test fixes covering 29 operators (#6964) and five missing coverage items (#7029), sparse semi-structured tests made device-agnostic (#7056), quantized GRU case engine guard (#7057), new operators without CPU reference implementations tagged NoCPU (#7045).
  • Security and precision fix cluster: index_select out-of-bounds (#7106), argmin tail mask (#7119), pad mask (#7121), layer_norm backward (#7123) — four under review; four fixes including all / any strided and zero strided (#7158 through #7161).
  • CI infrastructure: five-PR robust-checkout composite action series (checkout hang hardening), CICD random / probe docs, run_tests.py probing accelerator SDK versions (#7182).

FlagTree (27 merges)

  • TLE and multi-backend: TLE-Raw base backported to the 3.5.x maintenance line (#1321), Ascend tle.pipe (#1275), HPU / Moore Threads integer dot and dot_scaled capability contracts (#1189), CommonIR lowering to TritonGPU with five backends wired up at once — enflame / HCU / Iluvatar / MetaX / mthreads (#1353, under review), iluvatar and PPU tle.gpu.alloc aliases (#1317 / #1320), tiled smem (#1161).
  • FlagMega cross-architecture: C++/FTT codegen backend on BI-V150 (claimed faster than Triton), GEMV thread-residency fix (12.25 down to 10.38 ms/token), GLU activation cross-N-tile reuse (-0.17 ms/token); a five-PR series under review (#1361 through #1365) brings TLE software pipelining / warp specialization / global barriers down to RDNA (gfx1100 / gfx1201), adds amd-gfx1100 / amd-gfx1201 and nvidia-sm89 (Ada) targets, and runs Qwen3-1.7B decode and prefill on W7900 / R9700 as a single cooperative megakernel.
  • CI and new hardware: CI auto-rerun watchdog extended to all workflows (#1351), xpu3.6 FlagGems baseline and test workflows (#1366), tsingmicro3.6 baseline and test workflows (#1371), SpacemiT build patch fix (#1337); under review: SpacemiT smt_rvisa raw-kernel eDSL (#1381) and HCU backend fp64 MMAC (#1384).
  • PPU fixes: fp32 AIU GEMM transposed memory-order incorrect results (issue #1359) and its fix (#1360, shared-memory to dot-operand conversion with tests).

Torch-FL (38 merges)

  • Integration line: Tsingmicro FlagGems-only (#492 / #493) → Kunlunxin CUDA-boxing (#495) → boxing-free native XPU (#502) → three CI PRs (#504 / #507 / #508) → Iluvatar FlagGems-primary (#514) and 37 failing operators routed to cpu_fallback (#518) → Apple Silicon Metal runtime foundation (#516) and MPSGraph native operators (#528) → Iluvatar native vendor backend (#527) → Tsingmicro collective communication via FlagCX (#536).
  • CI and process: config-driven matrix (#519), unified manifest pipeline (#534), change-aware platform routing and trusted-fork on-demand CI (#521), CUDA boxing changed to an explicit switch (#520), three-stage CI (pr / nightly / weekly).
  • BERT-fleet push (early 10-16): nine-PR series (#545 through #553) covering MUSA / GCU convolution and layer_norm device validation, DCU complex dtype routing, Ascend SDPA dropout contract, Tsingmicro view-operator routing, Ascend FlagTree 0.7.0 tuning-parameter rename bridge, GCU rsub native and eight-platform SDPA coverage from a single source.
  • Consistency suite: hardware-agnostic runtime contract tests (device / registration / allocator / transfer / stream and event / dispatch) wired into all CI, with cross-platform runs exposing and fixing 4 real gaps (Enflame GCU stream and event semantics, non-CUDA current_stream placeholder, Tsingmicro stream construction, Ascend matmul passthrough path).

FlagCX (13 merges)

  • Transport and performance: PXN relay transport (#648, 37 files +3711/-268, including topology-based routing and 8-GPU CI), CRL adds a pthread worker pool and shared P2P artifacts (#647), stream-based IPC Get with network fallback (#649), RMA and collective progress unified into the worker pool (#651).
  • Correctness and consistency: result-aware transport state API (#654 / #652), coalesced batch holds the group guard throughout, CRL path waits for IBRC visibility refresh before GPU READ (#657), CUDA / MetaX / Hygon / PPU four-platform adapters fail fast when GPU tests are skipped (#653).
  • CI and backends: unified CI framework (config-driven platform discovery plus per-platform Feishu notifications, #650); Tsingmicro backend support PR (#656) opened; Hygon Device API and IR CI (#643) merged on the evening of 10-16.

FlagQuantum (13 merges)

  • Version line in Chapter II. On the engineering side, there is also a concentrated fix line from the Jiuding workshop (personal notes and assignments isolated by platform identity, shared mounts and image alias directories deduplicated, Quafu authorized hardware target corrected), plus inline plotting, Chinese teaching-text conventions, and a three-PR merge of six aligned example notebooks.

FlagGems-vllm (24 merges)

  • Inference operators: block-scaled INT8 einsum (#857, 10-12), MetaX backend-specific GDN fused_recurrent (#907), chunk_kda XuanTie TLE path with K=192 dropped (#899), PPU INT8 block BMM and w8a8_block_int8_bmm (#760), MThreads FP8 varlen attention (#926), MLA concatenation and graph-safe paged MQA logits (#897), Ascend chunk_kda (#918).
  • Tooling and benchmarks: --base-data parameter support and CUDA baseline comparison (#912, +72550/-5), libtuner unified tuning of dequantize_and_gather_k_cache launch config (#916, covering MetaX / Hygon / Moore Threads / XuanTie), ops test backend sync (#917).

vllm-plugin-FL (10 merges)

  • vLLM 0.28 adaptation batch: Iluvatar CoreX BI-V150 (#566) and Ascend (#487) first batch merged; Kunlunxin P800 (#585, Qwen3.6-27B dense and 35B-A3B MoE end-to-end validation completed), Moore Threads MUSA (#575), XuanTie (#574), Enflame S60 (#582) under review.
  • Component integration: FlagGems-vllm introduced into the plugin system (#583, +1507/-173, 49 files); Kunlunxin supports FlagTree (#546); Iluvatar multi-attention cache binding fix (#579); cache operators warmed up before graph capture (#552).
  • CI: three-stage pipeline (pr / nightly / weekly) and diff-based platform routing (#581 / #592 / #599).

sglang-plugin-FL and FlagGems-sglang (1 merge / 24 merges)

  • sglang-plugin-FL: #132 implements Iluvatar fused operators for sglang 0.5.18 (merged 10-14); under review: Hygon BW1000 upgrade to 0.5.18 (single-node TP2 and dual-node TP4 / PP2 tested, #138), Iluvatar 0.5.18 empty runtime (#139), Moore Threads Qwen3.6 integration (#125).
  • FlagGems-sglang (competition Track1): 19 competition kernels merged in batches on 10-12 and 10-13 (gate_topk, sigmoid_gate_mul, seqlens_expand, group_norm_silu, fused_moe_dispatch_index, dsv3_fused_a_gemm, deepep_permute, concat_mla_k, etc.); benchmark suite supports --base-data baseline speedup (#153), batch6’s 17-operator test skeleton (#155, 51 files) and ops-test workflow (#156) landed.

FlagAttention (6 merges)

  • miniMax sparse attention prefill / decode optimization on sm_90 (#85), Hygon version optimization (#94), operator API and test standardization refactor (#91), ops-test integration (#93) and format / Enflame operator list path fixes (#96), PPU unified container and SDK probing (#98 / #99); under review: Cambricon rotary embedding backend (#84).

FlagScale / FlagBLAS / FlagDNN / FlagFFT (2 / 2 / 0 / 1 merges)

  • FlagBLAS: five-backend GroupGEMM (ascend / hygon / iluvatar / mthreads / thead, #23, +8730/-1188, 31 files) merged; under review: thead PPU GEMM series (sgemm / hgemm / bfgemm / dgemm, #148) and rpm packaging (#146).
  • FlagScale: PPU platform brought into the shared CI pipeline and CUDA TE-FL dependency improvements (#1300, +1540/-18); checkpoint heartbeat false-positive fix (#1268) and diagnostic stop lifecycle (#1271); under review: Qwen3.5 multimodal training sequence packing (#1308).
  • FlagDNN: equivalent-performance data rolled out to Ascend, Moore Threads, DAMO XuanTie and Hygon (as direct-push commits, three “add equivalent performance” PRs plus Hygon standard supplements).
  • FlagFFT: issue #31 notes that at tag v0.2.0 pyproject declares 0.2.3 while the tag / rpm / manifest are all 0.2.0 (main has moved to 0.3.0-dev1); dev-to-main merge line progressing.

Megatron-LM-FL and TransformerEngine-FL (2 / 1 merges)

  • Megatron-LM-FL: #184 (PPU CI support) and #187 (unit test groups reuse dependency wheels) merged; #199 adds the Biren SUPA platform — SUPA as an independent torch device type (torch_supa renamed PrivateUse1), torch_supa.contrib.transfer_to_supa patching torch.cuda call sites, distributed backend BCCL; #201 unified CI framework; #200 Ascend GDN coverage and #202 DeepSeek-V4 upstream sync under review.
  • TransformerEngine-FL: #129 (PPU unit and integration tests), #132 (backend test runner standardization), #134 (unified CI framework removing eight per-platform duplicate triggers) merged; #135 restores the transformer_engine_torch sys.modules alias after loading vendor extensions (MetaX line), #136 NPU vendor capability query and tensor scaling fix under review.

FlagTrain / FlagSparse / FlagOS-Compressor (8 / 2 / 0 merges)

  • FlagTrain: KMCompiler CI/CD Dockerfile (#8), lamb operator test updates on Nvidia and Hygon (#7), packbits (#11), Ascend backend CI (#14), evoformer_attn (#6) and unpackbits (#17) merged; fp8_gemm (#18) and mixed_gemm (#10) under review.
  • FlagSparse: external contributor NCIC-AlphaSparse’s DCU / ROCm sparse batch (#109, 30 files +1611/-241, including ROCm sparse caching, DCU and Ascend docs and CI) and maca opt (#112) merged; license tabulation and packaging verify-only (#110 / #111).
  • FlagOS-Compressor: INT8 export (BF16 excluded, FP32 retained, #10) and MXFP8 / NVFP4 checkpoint conversion (#11) under review; PyPI dependency lower-bound fix (#12) merged in sync with the wheel pipeline on 10-10.

build-infra (35 merges) and community (12 merges)

  • build-infra: five PRs for wheel directories and automatic accounting (#1325 through #1331), matrix upgrade (#1333), docs pipeline script migration (#1334), deb version internal check (#1336), source tarball URLs (#1337), packages.yaml rename (#1338), 2.2 release tag pinning (#1339), self-hosted runner (#1341), dynamic FlagTree version selection (#1342), offline installer (#1348) and the daily wheel fix batch (#1349 through #1364).
  • community: 2.3 schedule and FEP guidelines (#126), four-PR governance data series (#127 through #130, people.yaml covering 31 people, projects.yaml recording maintainers / emeritus per repo, SIG composition vocabulary converged, unit renamed to org), three-PR contributor data series (#133 through #135, including the Kubuds organization mapping of 14 FlagGems contributors), #136 (15 FlagTree contributors and the Sunrise / T-Head / NVIDIA organizations), #137 (FlagCX and TransformerEngine-FL vendor backend contributors), #138 (FlagGems confirmed contributors), and FEP batch #139 through #149.
  • docs: model library bot auto-updates (#542 and #549 through #551), six new FlagRelease model READMEs on 10-13 (Hy3-nvidia, MiniCPM5-1B-zhenwu, Qwen3.6-27B-hygon, Qwen3.8-27B in BF16 and W4A8 versions), and a 31-file +5373/-69 ModelScope sync on 10-14.

New repositories and new directions

  • Trident (public on 10-12): compiles Python functions of Triton / Torch-style computation to MLIR / LLVM and executes them via tvm_ffi, providing trident.jit and trident.compile, depending on apache-tvm-ffi and torch 2.10 or later; #1 through #3 during the week completed base guards and torch operator coverage tests.
  • optest (created 10-13): operator testing facility including report generation tooling, dovetailing with the FlagGems weekly test fix batch and the ops-test workflows (FlagAttention / FlagGems-sglang).
  • FlagCV and the speech/audio trio (created 10-14): FlagCV points to the computer vision line, kaldi-triton / pyAudioAnalysis-sino / librosa-sino point to speech recognition and audio analysis; pyAudioAnalysis-sino landed its README and first snapshot on 10-16, positioned as a CNPort localization port for domestic CPUs and the Python scientific computing stack.
  • flir: Ascend Lane Vectorize merged (#76), PointerCastOp fix and dialect include under review (#80 / #81).

IV. Member Units and Vendor Adaptation

  • Kunlunxin: The vendor line with the highest engineering density this week. Torch-FL completed the three-step sequence from CUDA-boxing removal replacement-level refactoring to CI turning green (#502 / #504 / #507 / #508); FlagGems had fourteen XPU3 batch additions plus a batch-2 performance batch (#6662) and seven optimization fixes; FlagTree released the 0.7.1a1+xpu3.6 build line; on the inference side, vllm-plugin-FL #585 completed vLLM 0.28 adaptation and end-to-end validation for P800.
  • MetaX: FlagQuantum runtime packaging protection (#620, bringing vendor-compatible PyTorch runtimes into the quantum line’s cross-platform packaging matrix); FlagGems-vllm block-scaled INT8 einsum (#857) and GDN fused_recurrent (#907); MetaX fix batch — reshape_and_cache_flash switched to FL dispatch (#586), dense MM aborted under MMA tiles smaller than 16 (#7108), fp16 rnn_tanh precision (#6971), cudnn_convolution cleanup (#7145); TransformerEngine-FL alias guard (#135); Torch-FL complex operators routed through boxing (#539). News side: at the Industrial Expo, Xisuo X302 won the “Guoxin Exhibition” Innovation Achievement Award; GROMACS free-energy perturbation code merged into the open-source mainline; the university open-source tour Shanghai stop visited three universities; MiniCPM-V 4.7 dual-spec Day-0 (the 42nd model cumulatively); Step 5 Preview Day-0 (the 43rd model); Newton physics engine running; SGLang Meetup three-party discussion on upstream co-building of Plugin.
  • Iluvatar CoreX: Dual lines of build and runtime — FlagTree 0.7.1a1+iluvatar3.6 and FlagMega millisecond-level optimization on BI-V150 (GEMV from 12.25 down to 10.38 ms/token); Torch-FL FlagGems-primary backend (#514) and native vendor backend (#527) merged successively, with 37 failing operators routed to cpu_fallback the same day (#518); on the inference side, vllm-plugin-FL #566 (vLLM 0.28), sglang-plugin-FL #132 (0.5.18 fused operators), and vllm-plugin-FL #579 merged; FlagGems conv1d / conv2d optimization (#6298) and FlagBLAS grouped GEMM dispatch. News side: the Industrial Expo first showcased the “Tiangai 300 IXL144” supernode solution (144 GPUs plus 18 CPUs per rack, about 10.1TB of memory); on 10-15, officially announced MiniCPM-V 4.7 dual-spec Day-0 (over 400 models cumulatively).
  • Moore Threads: FlagGems warp-specialized SQMMA pipeline (#7093) and moe_load_balance_loss / SDPA forward optimization (#6985 / #6984); FlagTree MTHREADS TLE two-in-a-row (#1267 / #1268) and Proton header guard (#1347), with persistent GEMM pipeline and SPMC synchronization (#1294) and TME caching (#1385) under review; FlagGems-vllm FP8 varlen attention (#926); vllm-plugin-FL MUSA 0.28 adaptation (#575). News side: MTT S5000 and MUSA completed Step 5 Preview Day-0, and disclosed technical highlights including hybrid attention, FP8 DeepGEMM, mixed precision, and MTP3 speculative decoding.
  • Enflame: FlagGems Enflame S60 entered the ops test backend (#6917), gcu300 benchmark baseline correction (#7054), and a 28-file Enflame large update batch under review (#7077); Torch-FL switched GCU embedding to native topsatenEmbedding and upgraded the consistency suite skip to a hard failure (#499); vllm-plugin-FL S60’s 0.28 adaptation (#582) under review; FlagTree CommonIR five-backend list includes enflame, and FlagPrism Enflame integration (#1239) continues to be updated.
  • Ascend: FlagGems had over ten fixes and optimizations (#6946 / #6948 / #6949 / #7013 / #7081 / #7033 / #7125 / #7149 / #7165, plus #7157 fixing a vLLM multi-process GIL crash, and #7134 correctness and FlagTree compatibility); the FlagTree Ascend line had seven merges (reduce sum strength, dist ops documentation, semantic renaming, tle.pipe optimization, cann9.1 workflow upgrade to torch2.12 image); FlagGems-vllm flash_mla support for Ascend (#863) and fused_marlin_moe W4A16 (#744); vllm-plugin-FL 0.28 upgrade (#487) as the first batch of landing points; FlagTrain and flir two each; FlagScale shared CI. News side: Step 5 Preview is supported by vLLM Ascend 0Day, and the 1024-card Atlas 950 SuperPoD liquid-cooled supernode lit up in sync with the model’s open-source release.
  • DAMO XuanTie (including Zhenwu PPU): Torch-FL pinned PPU’s FlagTree to the 0.7.0 build (#494); Megatron-LM-FL #184 and TransformerEngine-FL #129 completed PPU’s entry into the training stack CI matrix; FlagTree PPU fp32 AIU GEMM memory ordering fix (#1359 / #1360), capability contract extended with integer dot and dot_scaled (#1189), tle.gpu.alloc alias (#1317 / #1320), swizzled layout preservation (#1348 under review); FlagGems ADDMM series optimization (#6859) and PPU-ZW810E unified test container (#7176); FlagGems-vllm XuanTie TLE path (#899) and PPU INT8 block-wise BMM (#760), unified T-Head fused Marlin MoE (#752); FlagBLAS thead PPU GEMM (#148 under review); FlagDNN XuanTie equivalent performance data.
  • Hygon: FlagCX Hygon Device API and IR CI (#643) merged on the evening of 10-16, four-platform consistency tests cover Hygon (#653); FlagSparse DCU / ROCm sparse batch (#109); FlagGems index_copy (#6714) and FlagGems-vllm libtuner tuning coverage; FlagTrain lamb test (#7); sglang-plugin-FL BW1000 upgraded to 0.5.18 (#138 under review); FlagDNN equivalent performance standard.
  • Tsingmicro: Torch-FL “FlagGems-only” route (#492) and guard exemption (#493), collective communication connected via FlagCX (#536), view operator routing (#550); FlagCX tsingmicro backend (#656) opened; FlagTree tsingmicro3.6 FlagGems baseline and test workflow (#1371) merged; community governance data includes its contributors. News side: MiniCPM-V 4.7 dual-spec Day-0 and three-benchmark precision alignment, disclosing that FLIR’s first batch of adapted chips participated in the underlying definition of 76 Triton primitives and 103 FlagGems operators, and jointly open-sourced Open3D-PIMC with BAAI.
  • Biren: Megatron-LM-FL #199 adds the SUPA platform (independent torch device type plus BCCL distributed backend) — entering the FlagOS training stack for the first time this week; news side: Step 5 Preview first release (BIRENSUPA and SUPACODE adapted to DSA / SummaryCache / MoE modules); the HK$4.04 billion placement announced on 10-08 (about 70% toward supply chain and capacity, about 20% toward R&D including the software ecosystem) was supplemented by the 10-12 entry.
  • Cambricon / Horizon Robotics: Cambricon’s FlagGems philox layout fix (#7009) and FlagAttention rotary embedding backend (#84) are both under review; Horizon Robotics had no substantive activity on GitHub or in the news this week.
  • SpacemiT: Submitted the smt_rvisa raw-kernel eDSL to FlagTree (#1381, under review, retiring the embedded TLE dialect), and fixed the build patch (#1337) — the first entry into compiler language-layer extension in the RISC-V AI direction.
  • Sunrise: Entered the community governance data organization list, included in the MiniCPM-V 4.7 Day-0 platform list, and vllm-plugin-FL’s PTPU graph mode (#569) is under review.
  • SiliconFlow: Multiple FlagGems merges during the week (_fused_adamw_ and tensor-LR overloads, index_reduce_ benchmark grouping, startup boundary regression, stft / stft.center, triangular_solve), with additional performance fixes for scatter_reduce / argsort / convolution_backward / upsample under review.
  • NCIC-AlphaSparse: External institutions continue to submit DCU / ROCm sparse batches (#109) and maca opt (#112) to FlagSparse, with stable external collaboration on the sparse line.

V. Ecosystem and Community

  • Conference (10-17 / 18, Beijing Zhongguancun National Independent Innovation Demonstration Zone Exhibition Center): The full agenda and attendee guide were released on 10-12 — 1 main forum, 6 sub-forums (AI Systems / Quantum-AI Fusion / Embodied Intelligence / AI Agent / In-Vehicle Intelligence / International AI Computing Cooperation), 1 hands-on workshop, and 100+ speakers; FlagOS 2.2 and the Quantum-AI Cloud Platform were released on site. Starting 10-15, livestream pages for three sub-forums went live (Open Computing AI Systems Forum, Quantum-AI Fusion, AI Agent); the workshop focuses on operator engineering, on-device inference, operator optimization, quantum AI programming, and AI-Infra agent architecture; the registration page has over 17,000 followers.
  • Global AI Open Computing Faculty Development Program Phase 2 (classes begin 10-12): Hosted by BAAI together with the African Union—African Scientific, Research and Innovation Council, Peking University, and Renmin University of China, implemented through the Zhongzhi FlagOS community with support from the United Nations Development Programme; participants are nearly 50 leading university faculty from more than 30 countries, with the training period running from 10-12 to 10-25; the core course “Fundamentals of Intelligent Computing System Hardware and Software” covers system software, operator engineering, compilers, distributed training and communication, and performance benchmarking. FlagOS founder Lin Yonghua disclosed in the opening report: Zhongzhi FlagOS now covers more than 30 types of AI chips from over 20 chip vendors and is jointly built by more than 100 institutions.
  • Competitions and developer operations: FlagOS Open Computing Global Challenge Season 2, Track 2 — MiniCPM Model Inference Throughput Performance Optimization Challenge opened registration on 10-16 (based on vllm-plugin-FL and FlagGems, optimizing MiniCPM5-2B on MetaX Xiyun C series and another domestic GPU in a dual-chip setup, dual scenarios of 4k / 16k, 70% overall performance plus 30% technical report innovation, registration closes 11-10, first prize RMB 30,000); community competition Track1 saw two concentrated repository cleanups within the week and 3 new contest kernel submissions.
  • Industry-academia-research activities: The MetaX University Open Source Tour Shanghai stop ran from 10-13 to 10-16 at East China Normal University, Donghua University, and Shanghai University (theme “Let Open Source Be Your First Resume,” including the Youth Open Source Special Fund Seed Program and model intelligent routing practice; the MetaX developer ecosystem has invested more than 100,000 GPU card-hours and plans to support more than 80 open source projects); MetaX and the SGLang community held an AI Infra Meetup, where MetaX / SGLang / FlagOS formed an upstream co-building approach on “SGLang supporting different chip vendors through the Plugin mechanism”; MetaX previewed two special events at CNCC 2026 (10-22 to 24, Chengdu).
  • Industry-side observations: The 26th China International Industry Fair (10-12 to 10-16, Shanghai) set up an independent integrated circuit “National Chip Exhibition” for the first time, with supernodes replacing single cards as the display focus — the MetaX Xijing S600 features a single rack with 64 fully interconnected cards and supports horizontal scaling to ten thousand cards, while Iluvatar CoreX’s “Tiangai 300 IXL144” was presented from a systems engineering perspective; IDC expects China’s intelligent computing power to reach 2,576.5 EFLOPS in 2026, up 87.9% year on year. Xinliu Think Tank reviewed four routes — general-purpose GPU, reconfigurable computing, open instruction set, and high-speed interconnect — under the theme “Delivery Is the Real Computing Power.” NetEase Youdao exhibited at the conference’s FlagOS marketplace with the Confucius4 speech large model and the desktop-level AI Agent LobsterAI.
  • Official channels and search verification: Component-name queries (FlagOS / FlagGems / FlagScale / FlagTree / FlagPerf / FlagCX / KernelGen, etc., in Chinese and English, 24 query sets) produced zero valid hits for five consecutive windows; coverage was concentrated on member organizations and the industry side (Day-0 announcements, conference materials, the Industry Fair, and competitions). Eight query sets on HN Algolia produced no direct hits; the CSDN column added three sub-forum pages during the week; no entries within the window were detected in the BAAI community.

VI. Trend Observations

  • Release cadence shifts from “version releases” to “release trains plus daily delivery”: The 2.3 schedule turns FEP deadlines, freezes, three-tier release candidates, and GA into a hard timetable and abolishes 2.2’s one-off fallback wording; build-infra pins the packaging ref to the official release-2.2 tag and wires wheel accounting into pipeline hooks; FlagTree switches to date-only version numbers for daily wheels and supports same-day manual reruns; the FEP-0139 offline one-click installer lets air-gapped hosts deploy with a single command. Together, these four moves mean the unit of external delivery is shifting from “a version” to “a sustainable, offline-capable artifact stream.”
  • Torch-FL solidifies as the standard entry point for vendor onboarding: Within one week, five routes—Qingwei, Kunlunxin, Iluvatar, Qingwei collective communication, and Apple Silicon—entered the same repository, with a clear, reusable pattern: a new backend slot, a CI lane, a packaging and fallback safeguard (failed operators routed to cpu_fallback), and a hardware-agnostic consistency contract. Vendor onboarding shifts from “per-project customization” to “implementation against a spec,” which will directly cut the upfront cost of onboarding new chips in the 2.3 cycle.
  • The Kunlunxin case shows that authority over backend approaches has moved upward: The CUDA-boxing proposal was judged non-compliant and wholly replaced with native XPU less than a day after landing, followed within 24 hours by a CI lane, a green run, and fixes for first-run issues. This is not merely engineering speed but governance rules (backends must connect directly to the vendor runtime) exercising veto power over short-term feasible options—a judgment likely to become more common in 2.3 FEP reviews.
  • The compiler side becomes the biggest variable, with direction shifting from “multi-backend” to “unified IR and portable kernels”: FlagTree’s FlagMega expands from single-point optimization on BI-V150 to RDNA and Ada, with the same cooperative megakernel running decode and prefill on a real Qwen3-1.7B; TileIR upgrades to CUDA Tile IR 13.4; Trident uses MLIR / LLVM plus TVM FFI as a frontend compilation bridge; SpacemiT submits the smt_rvisa eDSL. All four lines point to the same question—whether a single intermediate representation can feed multiple chips at once—which will be the main thread of the 2.3 cycle’s technical narrative.
  • Day-0 adaptation has crystallized into external assets and operational levers for member organizations: MiniCPM-V 4.7 covered twelve platforms on the same day, with MetaX and Qingwei publishing that evening and Iluvatar making its announcement the next day; four vendors shipped Step 5 Preview on the same day; the subsequent challenge turns “cross-chip optimization” into a competition for global developers. Adaptation capability is no longer just an internal metric but a brand asset that can be published externally, used to recruit developers, and exchanged for compute investment.
  • Organizational boundaries continue to expand, and the quality and governance foundation is starting to be filled in: Six new repositories were created in a week (compilation bridge, test infrastructure, vision, speech and audio), extending the footprint from large-model operators to multi-domain toolchains; at the same time, optest landed, the ops-test workflow rolled out across repositories, and weekly-test fixes ran in parallel with four-platform consistency CI, while community codified contributor affiliation and governance roles into people.yaml / projects.yaml as a single source of truth. Expansion synchronized with governance is the structural feature that distinguishes this week from earlier expansion phases.
  • Next observation points: The on-site releases at the conference (10-17 / 18) and the first daily report after the conference; the actual delivery form of the FlagOS 2.2 public release and the Liangzhi Cloud platform; review and merge progress on the first batch of 2.3 FEPs (#139 to #149) (deadline 11-13); the merge cadence of FlagMega AMD / Ada five-in-a-row and the PPU fixes; the actual form of FlagTree daily wheels (version numbers and release site); the merge order of the remaining three vLLM 0.28 lines (MUSA / XuanTie / S60); and the scale of participation in the MiniCPM challenge.

Appendix: Sources and Verification