Research window: 2026-10-12 06:00 ~ 2026-10-13 06:00 (Beijing time, approx. 24 hours; Tuesday morning report, window starts from the cutoff of the previous daily report (10-12)).

Sources: GitHub (org: flagos-ai, full verification of pushed_at across 56 repos, full verification of 90 commit searches, verification of merged and open PR searches (68 / 192), atomic verification of Releases across 26 repos and tags across 7 repos, branch-level supplementation for repos pushed within the window), Google News RSS (24 sets of Chinese and English query terms, via proxy), HN Algolia, Tavily supplementary search, verification of the official CSDN column and BAAI community, verification of the Industry Expo and conference news via the original sites (see the appendix source list for details).

In This Issue

  • Today’s Highlights: 4 days to the conference — full agenda released; engineering advances on three fronts: Torch-FL Kunlunxin “de-CUDA-boxing” wrap-up, first batch of vLLM 0.28 adaptation merged (Iluvatar / Ascend), new Trident repo added to the org (10-12 ~ 10-13)
  • I. Open Source Project Progress (GitHub Activity)
    • 1.1 Org Cadence: 18 repos pushed, 90 commits, 68 merges (10-12 ~ 10-13)
    • 1.2 Torch-FL: Kunlunxin “de-CUDA-boxing” hat trick — native XPU path replacement, CI onboarding, first-run fixes (10-12 ~ 10-13)
    • 1.3 New Public Repo Trident: experimental MLIR/LLVM compilation bridge (10-12)
    • 1.4 FlagGems: 13 merges across multiple lines; v5.5.0.dev0 development line opened (10-12)
    • 1.5 FlagTree: FlagMega development line continuously optimized on BI-V150; 0.7.1a1+iluvatar3.6 build line refreshed (10-12 ~ 10-13)
    • 1.6 Inference Stack: first batch of vLLM 0.28 adaptation merged (Iluvatar / Ascend); MUSA / XuanTie / S60 sprinting through review (10-12 ~ 10-13)
    • 1.7 FlagGems-sglang: Competition Track1 clears another 19, benchmarking tools completed (10-12)
    • 1.8 Release Engineering & Governance: five build-infra commits, four community governance data updates, docs model library auto-update (10-12 ~ 10-13)
    • 1.9 Other Lines: FlagAttention / FlagQuantum / FlagDNN / FlagTrain / FlagGems-Experimental (10-12)
  • II. News & Ecosystem
    • 2.1 Full Conference Agenda and Attendee Guide Released: FlagOS 2.2, Liangzhi Cloud Platform on-site launch preview (10-12)
    • 2.2 CIIF Opens with Inaugural “National Chip Exhibition”: member units share the stage, supernodes become the main battlefield (10-12)
    • 2.3 MetaX: Xisuo X302 wins “National Chip Exhibition” Innovation Achievement Award; GROMACS free energy perturbation code merged into open-source mainline (10-12)
    • 2.4 Ecosystem Watch: ChipFlow Think Tank “four on one stage” roundup — Biren / Tsingmicro / Eswin / Moore Threads (10-12)
    • 2.5 Search & Official Channel Verification: component lines remain quiet (10-12 ~ 10-13)
  • III. Member Unit Deep Dive
    • 3.1 Kunlunxin: de-CUDA-boxing and XPU optimization batch (10-12 ~ 10-13)
    • 3.2 Iluvatar CoreX: Iluvatar build line refresh and FlagMega BI-V150 optimization (10-12 ~ 10-13)
    • 3.3 MetaX: MetaX line fixes, TE-FL alias guard, and CIIF dual threads (10-12)
    • 3.4 Moore Threads / Enflame: MUSA 0.28 sprint, MTHREADS batch, and S60 adaptation (10-12 ~ 10-13)
    • 3.5 DAMO XuanTie and Zhenwu PPU / Ascend: XuanTie TLE line, PPU capability surface expansion, and Ascend fix batch (10-12 ~ 10-13)
    • 3.6 Other Members: Hygon / Tsingmicro / Cambricon / Horizon (10-12)
  • IV. Summary and Trend Observations
  • Appendix: Source Verification Table
  • Complete Source List

Today’s Highlights: 5 Days to the Conference — Full Agenda Released; Engineering Advances on Three Fronts: Torch-FL Kunlunxin “De-CUDA-boxing” Wraps Up, First Batch of vLLM 0.28 Adaptation Merged, New Trident Repo Added to the Org (10-12 ~ 10-13)

Date: 2026-10-12 ~ 2026-10-13　Sources: Torch-FL #502 · vllm-plugin-FL #566 · FlagTree Trident · Conference Agenda (CSDN) (full list in appendix)

The 24-hour window remains at a high level: 18 of 56 repos had pushes within the window, commit search returned 90 hits, 68 PRs were merged (13 repos with merges), and another 192 open PRs were updated within the window; 2 new tags were added (both on the dev/build line) and 1 new public repo appeared. With 4 days to go before the October 17-18 conference, three main threads are advancing in parallel:

  • Kunlunxin “de-CUDA-boxing” wraps up (Torch-FL): #502 replaces the entire Kunlunxin CUDA-boxing backend that had just landed in the previous window with a native XPU path (native kKunlunxin backend slot + device layer based on the vendor XPU SDK’s pure-C libxpurt + operator layer based on the xdnn operator library, 47 files, +5347/-2443). #503 then spun up a CI lane for the P800, and #504 in the early hours is already fixing build issues exposed by the lane’s first run — from “it runs” to “managed along the native path,” three moves in 24 hours (see 1.2 for details).
  • First batch of vLLM 0.28 adaptation merged: The observation point from last issue is confirmed — Tianshu (#566, CoreX BI-V150) and Ascend (#487) both merged in succession; MUSA (#575), XuanTie (#574), and Enflame S60 (#582) are still under review, as batch adaptation enters its landing phase (see 1.6 for details).
  • New Trident repo added to the org + conference materials ready: The org has made public the experimental MLIR/LLVM compilation bridge project Trident (commit history since May, 274 commits cumulative), and FlagGems opened a 5.5 dev-line tag the same day; on the news side, the full conference agenda and attendee guide were officially released, with FlagOS 2.2 and the Liangzhi Cloud platform listed as on-site launch previews (see 1.3 / 2.1 for details).

Assessment: This window shows the classic dual signature of “pre-conference engineering sprint + external launch readiness” — on one side, “pre-launch wrap-up” actions such as de-boxing, CI lanes, version tags, and build matrices are landing densely (Torch-FL / build-infra / FlagTree / FlagGems all in the same window), while on the other, materials serving the launch day — agenda, attendee guide, model library docs — are all in place; the pace of 68 merges matches the post-holiday volume period, and for the first time we see a complete closed loop of “single-repo replacement-level refactor + CI follow-up within 24 hours,” a marked improvement in engineering maturity versus before the holiday.

I. Open-Source Project Progress (GitHub Activity)

1.1 Organization Cadence: 18 Repos Pushed, 90 Commits, 68 Merges (10-12 ~ 10-13)

Date: 2026-10-12 ~ 2026-10-13　Source: org: flagos-ai repository list · org repos API (verification baseline)

  • Repository surface: 56 repositories (+1 vs. previous period, new addition Trident); 18 repos had pushes within the window—FlagTree (10-13 01:07), Torch-FL (10-13 01:00), build-infra (10-13 00:57), Trident (10-13 00:50), community (10-12 23:22), FlagQuantum (10-12 21:46), FlagGems (10-12 20:35), docs (10-12 18:50), FlagFFT (10-12 17:47), FlagGems-vllm (10-12 17:31), FlagGems-sglang (10-12 17:22), FlagAttention (10-12 16:40), FlagDNN (10-12 15:52), vllm-plugin-FL (10-12 15:43), awesome-LLM-driven-kernel-generation (10-12 15:36), release-info (10-12 14:21), FlagGems-Experimental (10-12 10:37), FlagTrain (10-12 09:56).
  • Commits and merges: 90 commits from search (FlagGems-sglang 21 / FlagQuantum 15 / FlagGems 13 / community 8 / Torch-FL 7 / FlagGems-vllm 5 / build-infra 5 / FlagTree 4 / FlagAttention 3 / FlagGems-Experimental 2 / Trident 2 / FlagDNN 2 / vllm-plugin-FL 1 / awesome-LLM-driven-kernel-generation 1 / FlagTrain 1); 68 merges (13 repos, details in 1.2 ~ 1.9), 192 open PRs updated within the window (top 100 verified individually; FlagGems accounts for 54, one-third of the total, reflecting high-concurrency review on the optimization batch and KernelGen lines).
  • Releases: no new Release objects; 2 new tags—FlagGems v5.5.0.dev0 (10-12 11:23, opening the 5.5 development line) and FlagTree 0.7.1a1+iluvatar3.6 (10-12 10:46, Iluvatar build line refresh, paired with build-infra #1333 matrix upgrade).

1.2 Torch-FL: Kunlunxin “De-CUDA-boxing” Triple—Native XPU Path Replacement, CI Onboarding, First-Run Fixes (10-12 ~ 10-13)

Date: 2026-10-12 ~ 2026-10-13　Source: Torch-FL #502 · Torch-FL #503 · Torch-FL #504 · Torch-FL #498 · Torch-FL #500

  • #502 de-boxing refactor (merged 10-12 22:31, 47 files +5347/-2443): The Kunlunxin “CUDA-boxing” approach merged just in the previous window was replaced wholesale—a new native kKunlunxin backend slot, a device layer based on the vendor XPU SDK’s pure C interface libxpurt
    (csrc/runtime/accelerator/kunlunxin/), and an operator layer based on the xdnn operator library (aten/backends/kunlunxin/); the regenerated registration config no longer contains any cuda routing. The PR description explicitly records: the team decided Kunlunxin must not use CUDA-boxing, and the backend must connect directly to the vendor XPU runtime—P800 shifts from “borrowing CUDA” to “native hosting.”
  • #503 CI onboarding (merged 10-13 01:00): Added the .github/configs/kunlunxin.yml lane, environment hooks, and ci.yml routing; Kunlunxin gains a P800 CI lane on main isomorphic to other chips.
  • #504 first-run fixes (submitted 10-13 01:37, under review): The lane’s first run exposed issues at the build stage—the environment hook cannot locate the vendor xdnn operator library in the runtime image venv; and two guards in csrc/aten/sparse_csr_ops.cc still assume a CUDA-boxing build, causing the post-build import smoke test to fail on undefined cuSPARSE symbols. The fix PR is under review.
  • Other merges (5): #499 routes Enflame GCU embedding through the native topsatenEmbedding kernel and upgrades consistency-suite skips to hard failures; #500 adopts unified matrix discovery, nightly scheduling (02:00 CST), and Feishu notifications; #498 routes cat to FlagGems via the tensorlist_dim codegen category; #501 stops routing MetaX _softmax/embedding to the unbuilt FlagGems C++ path.

1.3 New Public Repository Trident: Experimental MLIR/LLVM Compilation Bridge (10-12)

Date: 2026-10-12　Source: flagos-ai/Trident · README · commit history

  • Positioning: Trident is an experimental compilation bridge—it compiles Python functions containing Triton/Torch-style computation into MLIR/LLVM, then executes via tvm_ffi; the core is C++/MLIR (CMake build, LLVM/MLIR pulled in as an external project), with Python-side entry points trident.jit and trident.compile, examples covering ATen operator lowering such as add / attn / mm / softmax, depending on apache-tvm-ffi and torch>=2.10.
  • Timeline: The repository was created and made public within the org on 10-12 16:47 (Beijing time); master branch commit history traces back to mid-May, 274 commits cumulative; 2 within the window—”refactor: unify FX and Triton imports around TVM FFI” (10-12 23:10) and “test: reorganize coverage and check e2e CUDA memory leaks” (10-13 00:50).
  • Observation: The project completed its migration from torch-mlir imports to direct FX-to-TVM-FFI connection in July; in form it is an exploration of a “frontend compilation bridge” for unified multi-chip onboarding, echoing FlagTree’s unified compiler route; its future direction (whether it converges with the TLE / FlagMega lines) is worth tracking.

1.4 FlagGems: 13 Merges Across Multiple Lines; v5.5.0.dev0 Development Line Opened (10-12)

Date: 2026-10-12　Source: FlagGems #7045 · FlagGems #7054 · FlagGems #6949 · FlagGems #7013 · FlagGems #6928 · FlagGems #5577 · v5.5.0.dev0 tag (remaining list in appendix)

  • 13 merges: Kunlunxin line (#7019 code formatting, #6943 inplace_fused_experts skipping vllm’s torch rewrite); SiliconFlow line (#6928 adds _fused_adamw_ and tensor-LR overloads, #6889 fixes index_reduce_ benchmark grouping, #6931 expands startup boundary regression coverage); KernelGen line (#5577 adds the special_spherical_bessel_j0 operator); testing and annotation (#7045 introduces the NoCPU tag for new operators without CPU reference implementations, #6972 fifth batch of explicit operator invocation tests, #7044 CICD random / probe documentation); Ascend line (#6949 fixes mul launch grid overflow under large contiguous inputs, #7013 extends auto-blockify to addmm / bmm); Enflame line (#7054 stops treating CPU fallback as the benchmark baseline—fixing the issue where trivial elementwise operators on gcu300 were reported with ~60x inflated speedups). Also #7017 decouples connection timeouts and transfer throughput in the CI robust checkout stage.
  • Line opened: New v5.5.0.dev0 tag within the window (10-12 11:23)—following the 5.4 release (09-28), the next-generation development line marker is opened (the repo’s 5.4 cycle also opened with v5.4.0.dev0, consistent pattern).
  • Active under review (54): Highlights include #7041 “optionally enabled ATen routing and launch plan caching” (off by default, +1965 lines), the Kunlunxin XPU optimization batch (#7049 / #7051 / #7052 / #7046 / #7053 / #7055 / #7018 / #7023 and a dozen more), #7048 (Ascend GRU launch count capped at coreDim), #7050 (DAMO XuanTie / MetaX linalg_matrix_power fix), #7042 / #7043 (KernelGen adds ger and multilabel_margin_loss), etc.

1.5 FlagTree: FlagMega Development Line Continues Optimizing on BI-V150; 0.7.1a1+iluvatar3.6 Build Line Refreshed (10-12 ~ 10-13)

Date: 2026-10-12 ~ 2026-10-13　Source: feature/flagmega branch · FlagTree #1352 · FlagTree #1353 · FlagTree #1189 · FlagTree #1347 · issue #1331

  • FlagMega development line (feature/flagmega branch): The compilation path for model-level fusion / packaging continues to heat up, with multiple performance commits within the window—”Add C++/FTT codegen backend, faster than Triton on BI-V150” (10-12 06:08), “Fix GEMV thread residency on BI-V150, 12.25 -> 10.38 ms/token” (16:09), “Reuse the GLU activation run across the N tile, -0.17 ms/token” (17:03), “Record why SME loses on issue slots too, not just bandwidth” (17:07); the companion tutorial line (Qwen3-1.7B, dual targets NVIDIA H800 / Iluvatar BI-V150) compilation issue #1331 was closed on 10-12 22:35 (submitted 10-08, norm_stats physical ABI mismatch).
  • Build line refresh: New 0.7.1a1+iluvatar3.6 tag (10-12 10:46)—the Iluvatar CoreX 4.5.0 line upgraded from 0.7.0+iluvatar3.6 to the first alpha of the 0.7.1 series; build-infra completed matrix sync the same day via #1333.
  • 4 merges: #1189 updates Zhenwu PPU / Moore Threads integer dot and dot_scaled support via the backend capability contract; #1351 extends the CI auto-rerun watchdog to all workflows (named failure modes); #1337 fixes the SpacemiT build patch (setup.py); #1347 guards the Moore Threads Proton tool registration header with __PROTON__.
  • Under review highlights: #1352 upgrades the TileIR backend to CUDA Tile IR 13.4 (65 files +7921/-1382, including descriptor reduce / gather / scatter lowering, scaled-dot, etc.); #1353 generalizes the CommonIR (tile dialect) → TritonGPU lowering into a shared TLE channel, connecting five backends—enflame / HCU / Iluvatar / MetaX / mthreads—in one pass.

1.6 Inference Stack: First Batch of vLLM 0.28 Adaptation Merges (Iluvatar / Ascend); MUSA / XuanTie / S60 Sprint Under Review (10-12 ~ 10-13)

Date: 2026-10-12 ~ 2026-10-13　Source: vllm-plugin-FL #566 · vllm-plugin-FL #487 · vllm-plugin-FL #575 · vllm-plugin-FL #582 · FlagGems-vllm #907 · FlagGems-vllm #916

  • First vLLM 0.28 batch landing points: #566 Iluvatar CoreX BI-V150 support (merged 10-12 10:43), #487 Ascend upgrade (merged 10-12 15:07)—the previous period’s “five lines still under review” observation is now realized on two lines.
  • Sprint under review: #575 (Moore Threads MUSA → 0.28.0) maintains high-frequency updates (as of 10-13 05:07), #574 (XuanTie → 0.28.0), #582 (Enflame S60 → 0.28.0: Qwen3.6-27B passes the original adaptation gate in both eager / graph modes, 35B-A3B passes eager, graph blocked by Mamba cache capacity), #581 (three-stage CI: pr / nightly / weekly + diff-based platform routing, 46 files under review).
  • Other merges: #552 prewarms cached operators before graph capture (Prewarm CachedOps); five FlagGems-vllm merges—#899 adds a XuanTie TLE path for chunk_kda and drops K=192 support, #902 adds extension-free M3 inference operators and optional W8A8 fusion, #907 adds a backend-specific GDN fused_recurrent kernel for MetaX, #916 unifies launch config tuning for dequantize_and_gather_k_cache via libtuner (MetaX / Hygon / Moore Threads / XuanTie multi-backend), #917 syncs operator test backends.

1.7 FlagGems-sglang: Competition Track1 Clears Another 19, Benchmark Tooling Completed (10-12)

Date: 2026-10-12　Source: FlagGems-sglang #128 · #153 benchmark tooling · #155 batch 6 skeleton · #156 ops-test

  • Between 11:51 and 12:04 noon, competition Track1 kernel batches merged in a burst of 19: gate_topk, sigmoid_gate_mul, seqlens_expand, residual_gate_add, group_norm_silu, gelu_tanh_and_mul, fused_moe_dispatch_index, fused_eh_norm, dsv3_fused_a_gemm, deepep_permute, deepep_post_reorder, concat_mla_k (two), create_flashinfer_kv_indices, clamp_position, compute_src2dst, build_trtllm_mha_page_table, fill_padded_rows, etc. (contributors include community participants c2flowDS / yzw1128 / xiaojiu1414 / goldenfox2025 / hangglider5, among others).
  • Companion: #153 merged at 14:35 “benchmark suite supports --base-data baseline speedup ratio” (+501/-3, giving each operator result a speedup ratio relative to baseline latency, with unmatched items retaining the original gems-vs-torch metric); #155 under review has laid out test / benchmark skeletons for batch6’s 17 operators (51 files, awaiting submission placement), #156 wires the ops-test workflow into the repository.

1.8 Release Engineering and Governance: build-infra Five Merges, community Governance Data Four-Pack, docs Model Library Auto-Update (10-12 ~ 10-13)

Date: 2026-10-12 ~ 2026-10-13　Source: build-infra #1333 · build-infra #1336 · community #127 · community #128 · docs #549

  • build-infra 5 merges: #1333 matrix upgrade of Iluvatar corex4.5.0’s FlagTree to 0.7.1a1+iluvatar3.6 (paired with the tag in the previous section); #1332 documents the wheel-info.yaml maintenance process; #1334 migrates docs pipeline scripts into scripts/docs; #1335 wrap-cmd comments point to the new path; #1336 passes the wheel version into the flaggems-deb build and verifies it inside the .deb. #1337 under review adds source package download URLs for each package (feat/source-info branch pushed 10-13 00:57).
  • community governance data four-pack (+291 lines): #127 introduces community/data/ as the authoritative data source for contributor affiliation and governance roles (people.yaml covers 31 people, starting with BAAI; projects.yaml records maintainer / emeritus for each repository, solving the drift problem of hand-maintained tables); #128 clarifies SIG = Chair + Tech Lead composition, with the role vocabulary consolidated into data/sigs.yaml; #129 renames unit to org and adds org domains and FlagGems contributors; #130 sorts by id. Governance moves from documentation to a “data-driven single source of truth.”
  • docs model library auto-update: #549 (bot auto-PR, 10-12 18:50) adds 6 FlagRelease model READMEs—Hy3-nvidia, MiniCPM5-1B-zhenwu, Qwen3.6-27B-hygon, Qwen3.8-27B-BF16-hygon, Qwen3.8-27B-BF16-zhenwu, Qwen3.8-27B-W4A8-arm (covering Hygon, Zhenwu, ARM, and other targets).
  • Release info side: release-info repository gh-pages pushed on 10-12 14:21 (release info site updated with release activity); FlagFFT filed issue #31—pointing out the inconsistency between the v0.2.0 release tag and package version (pyproject at the tag says 0.2.3, while the tag / rpm / manifest are all 0.2.0; main has moved to 0.3.0-dev1), a release engineering detail issue explicitly recorded.

1.9 Other Lines: FlagAttention / FlagQuantum / FlagDNN / FlagTrain / FlagGems-Experimental (10-12)

Date: 2026-10-12　Source: FlagAttention #85 · FlagAttention #94 · FlagQuantum #621 · FlagTrain #8 · FlagGems-Experimental #691

  • FlagAttention 3 merges: #85 miniMax sparse attention prefill / decode optimization on sm_90, #94 Hygon version optimization of the same kernel, #93 wires in the ops-test workflow—attention operators optimized in parallel on both NVIDIA and Hygon lines.
  • FlagQuantum: 15 commits + #621 merged—concentrated fixes on the Jiuding workshop line (personal notes and assignments isolated by platform identity, shared mounts and image alias directory deduplication, Quafu authorized hardware target correction, distinguishing remote completion from result visibility, etc.); the fix/metax-torch-runtime branch had a push on the evening of 10-11.
  • FlagDNN: 2 commits—adding equivalence performance standards for Hygon, adding NVIDIA performance data.
  • FlagTrain: #8 merged (KMCompiler CI/CD Dockerfile); #9 under review (update CI Dockerfile), #10 (add mixed_gemm operator, KMCompiler / NVIDIA line).
  • FlagGems-Experimental: 2 KernelGen merges (#691 _slow_conv2d_forward, #679 sparse_csr_tensor).
  • awesome-LLM-driven-kernel-generation: #10 merged (adds recent papers and code repositories).

II. News Coverage and Ecosystem

2.1 Full Agenda and Attendee Guide Released: FlagOS 2.2, Liangzhi Cloud Platform On-site Launch Preview (10-12)

Date: 2026-10-12　Source: Full agenda release (CSDN) · Media reprint (NetEase) · Registration and agenda page

  • On the evening of 10-12, the “2026 Artificial Intelligence Open Computing Conference & Zhongzhi FlagOS Technical Conference” (October 17-18, Beijing Zhongguancun National Independent Innovation Demonstration Zone Exhibition Center) officially released its full agenda and attendee guide: two days featuring a main forum, multiple sub-forums, and hands-on workshops, with 100+ speakers covering BAAI, CAS, Tsinghua, Peking University, Li Auto, Baidu, Tencent, NVIDIA, and others; FlagOS 2.2 and the Liangzhi Cloud Platform will be released on-site.
  • Agenda highlights: the Day 1 main forum includes Lin Yonghua (Deputy Director and Chief Engineer of BAAI) on “Zhongzhi FlagOS 2.2: From Token Economy to Physical AI,” “Compute Evolution in the Era of Trillion Tokens,” “World Models: The Next-Generation AI Foundation and Its Compute Bill,” and the roundtable “The Decade Debate on Next-Generation AI Compute Infrastructure”; technical sub-forums include “Zhongzhi FlagOS Innovations in RISC-V AI Chip Adaptation,” “RISC-V System Software Collaboration Practices for On-Device Agents,” and “Unified IR Breaks Through the Triton Programming Paradigm to Unlock Ultimate Multi-Chip Performance” (Yuan Sheng, Compiler Optimization System Architect), among others; the Day 2 Embodied Intelligence sub-forum (10-18 afternoon) brings together Infinigence AI, JIAJIA Vision, Huixi Intelligence, Xiaowu Intelligence, Kuawei Intelligence, Beihang University, the Institute of Computing Technology of CAS, and others.
  • The attendee guide covers time and venue, check-in (8:30-9:30 on the 17th), subway/bus/driving routes, and weather reminders; the registration page shows 17,000+ followers. This item is the core node of FlagOS’s external activities this week, continuing to validate the previous issue’s observation point on the “pre-conference external release cadence.”

2.2 CIIF Opens with First-Ever “National Chip Exhibition”: Member Units Share the Stage, Supernodes Become the Main Battleground (10-12)

Date: 2026-10-12　Source: 21st Century Business Herald · CIIF opening preview (Jiefang Daily)

  • The 26th China International Industry Fair (10-12 to 10-16, Shanghai) opened, setting up an independent integrated circuit exhibition, the “National Chip Exhibition,” for the first time (covering the full chain of design, manufacturing, packaging and testing, equipment, and materials, with over 300 participating companies); AI chip companies including MetaX, Enflame, Iluvatar CoreX, and Dongfang Suanxin share the stage, with the top three domestic EDA vendors present.
  • Supernodes have replaced single cards as the focus of each company’s display: MetaX’s Xijing S600 supernode integrates 64 fully interconnected cards per rack and supports horizontal scaling to 10,000-card scale; Iluvatar CoreX debuted its systematic supernode solution “Tiangai 300 IXL144” (144 GPUs + 18 CPUs per rack, approximately 10.1TB of memory), with Vice President Zou Xuan stating that “a supernode is not a single product but a systems engineering endeavor, and ultimately what is being compared is system economic efficiency”; IDC expects China’s intelligent computing capacity to reach 2,576.5 EFLOPS in 2026, up 87.9% year-on-year.

2.3 MetaX: Xisuo X302 Wins “National Chip Exhibition” Innovation Achievement Award; GROMACS Free Energy Perturbation Code Merged into Open-Source Mainline (10-12)

Date: 2026-10-12　Source: Award coverage (Securities Star reprint) · Product page (MetaX official site)

  • On 10-12, the CIIF “National Chip Exhibition” Innovation Achievement Award was announced, with MetaX’s fully self-developed scientific computing GPU Xisuo X302 selected: a fully self-developed GPGPU architecture with domestic advanced process, multi-precision mixed compute and large-capacity high-bandwidth memory, paired with the MXMACA software stack, targeting AI4S (meteorological and ocean forecasting, computational fluid dynamics, molecular dynamics, materials simulation, life sciences, etc.).
  • Open-source contribution: The coverage explicitly notes that MetaX is deeply involved in the GROMACS open-source community, and its free energy perturbation GPU acceleration code has been merged into the open-source mainline, making it the first domestic company to make significant code contributions to this core module — domestic GPUs moving from “compatible with open source” to “contributing to open source,” aligned with this stack’s open-source nature.
  • On the ecosystem deployment side: it is working with Hongzhiwei, Deep Principle, Weixin Technology, the Greater Bay Area National Innovation Center, and others to advance scenarios including new energy materials R&D, industrial coolant molecular screening, and AI nowcasting weather forecasting; the Hongyuan Intelligent Materials R&D Platform, jointly developed with Hongzhiwei, has completed industrial-grade validation.

2.4 Ecosystem Watch: Xinliu Think Tank’s “Four on the Same Stage” Review — Biren / Tsingmicro / Eswin / Moore Threads (10-12)

Date: 2026-10-12　Source: ZAKER reprint (Xinliu Think Tank)

  • The industry research account “Xinliu Think Tank” published a review on the same theme, with the headline “Delivery is the real compute”: whether it can run stably, how much power it consumes, whether migration is hassle-free, and whether multiple cards can work in concert are redefining “high compute.”
  • The article covers four differentiated routes — general-purpose GPU (Biren), reconfigurable computing (Tsingmicro TX82 series), open instruction set (Eswin), and high-speed interconnect (Moore Threads) — closely overlapping with the route distribution of this stack’s member units, and can serve as an ecosystem-side reference.

2.5 Search and Official Channel Verification: Component Line Remains Quiet (10-12 ~ 10-13)

Date: 2026-10-12 ~ 2026-10-13　Source: Google News RSS (24 sets of Chinese and English query terms, via proxy) · HN Algolia · CSDN column · BAAI Hub

  • Component-name queries (FlagOS / FlagGems / FlagScale / FlagTree / FlagPerf / FlagCX / KernelGen, etc., in Chinese and English) continued to yield zero valid hits within the 24-hour window (continuing the norm of the previously quiet window); hits were concentrated on member units and the industry side (7 items collected across the conference, CIIF, MetaX, and the four-company review, consolidated into 4 events), while the remaining 15 were market pieces, content farms, and gambling SEO pollution, all excluded.
  • HN Algolia’s 8 query sets (4-day window) produced no direct hits; the official CSDN column homepage top still shows previous competition/livestream content (latest entry from late August), with no new articles within the window; BAAI Hub search and homepage detected no FlagOS entries within the window. External facts should be based on the GitHub org and community channels.

III. Deep Dive into Member Units

3.1 Kunlunxin: De-CUDA-boxing and XPU Optimization Batch (10-12 ~ 10-13)

Date: 2026-10-12 ~ 2026-10-13　Source: Torch-FL #502 · Torch-FL #503 · Torch-FL #504 · FlagGems #7049 · FlagGems #7019 · FlagTree #1330

  • Main line: Torch-FL completed a replacement-level refactor from “CUDA-boxing → native XPU” within 24 hours (#502, 47 files) and attached the P800 CI lane (#503), with #504 already following up on first-run fixes—Kunlunxin becomes the vendor line with the highest engineering density in this window.
  • Operator optimization batch: Kunlunxin XPU optimization on FlagGems enters an intensive phase—#7019 (formatting) and #6943 (inplace_fused_experts skipping vllm rewrite) have been merged; over a dozen PRs under review cover scatter_reduce / euclidean_dist / normed_cumsum (#7049), foreach-family parameterized pointers (#7051), sign_ / hardshrink_backward / alpha_dropout / max_dim (#7018), linalg_lu_factor small shapes (#7046), normal_functional / min (#7052), iand / ior / rshift / avg_pool3d and other XPU overrides (#7023), te_rmsnorm / hc_head fused kernel performance (#7053), i0 (#7055), and the SDNN v12 conv carrier (#7003).
  • Compiler side: FlagTree #1330 (XPU backend synced with internal triton @de4bf790) is under review and continuously updated (10-13 01:28); on the vLLM side, P800-related PRs under review and CI readiness advance in parallel.

3.2 Iluvatar CoreX: Iluvatar Build Line Refresh and FlagMega BI-V150 Optimization (10-12 ~ 10-13)

Date: 2026-10-12 ~ 2026-10-13　Source: FlagTree 0.7.1a1+iluvatar3.6 · build-infra #1333 · feature/flagmega · vllm-plugin-FL #566

  • Build line: 0.7.1a1+iluvatar3.6 (10-12 10:46) becomes the latest Iluvatar entry among FlagTree build tags; build-infra upgraded the corex4.5.0 matrix from 0.7.0 to 0.7.1a1 the same day; on the vLLM side, CoreX BI-V150 adaptation to 0.28.0 (#566) was merged in the morning.
  • Continuous FlagMega optimization on BI-V150: C++/FTT codegen backend launched (claimed faster than Triton), GEMV thread residency fix (12.25 → 10.38 ms/token), packed weight address split fix (previously costing 8 ms/token), GLU activation cross-N-tile reuse (-0.17 ms/token)—single-card millisecond-level / token-level quantified optimizations advance in tutorial-reproducible form (Qwen3-1.7B dual-target tutorial line).
  • Under review: FlagTree #1317 (TLE tle.gpu.alloc alias support for Iluvatar) and #1293 (Iluvatar C++ source specialization) remain updated.

3.3 MetaX: MetaX Line Fixes, TE-FL Alias Guard, and Dual Threads from the Industry Expo (10-12)

Date: 2026-10-12 ~ 2026-10-13　Source: Torch-FL #501 · TransformerEngine-FL #135 · FlagGems-vllm #907 · Industry Expo report · Award report

  • Runtime fix line: Torch-FL #501 stops routing MetaX’s _softmax/embedding to the unbuilt FlagGems C++ path (consistency suite criteria correction); TransformerEngine-FL #135 (under review) always restores the transformer_engine_torch sys.modules alias after loading vendor extensions—compatibility issues between vendor extensions and framework namespaces are being closed out consecutively; the FlagQuantum fix/metax-torch-runtime branch advances in parallel.
  • Operator line: FlagGems-vllm #907 adds a backend-specific GDN fused_recurrent kernel for MetaX (merged); the libtuner multi-backend tuning batch in #916 covers MetaX.
  • Dual news threads: The Industry Expo Xijing S600 supernode (64-card full interconnect, ten-thousand-card scaling) and the Xisuo X302 “Guoxin Exhibition” Innovation Achievement Award + GROMACS open-source mainline contribution (see 2.2 / 2.3).

3.4 Moore Threads / Enflame: MUSA 0.28 Sprint, MTHREADS Batch, and S60 Adaptation (10-12 ~ 10-13)

Date: 2026-10-12 ~ 2026-10-13　Source: vllm-plugin-FL #575 · vllm-plugin-FL #582 · FlagGems #6984 · FlagTree #1347 · FlagGems #7054

  • Moore Threads: vLLM 0.28 adaptation (#575) maintains high-frequency cross-day updates (still active as of 10-13 05:07, the latest update among remaining under-review lines); FlagGems #6984 implements full attention (SDPA forward/backward + Flash / varlen entry points) under review; FlagTree #1347 merges Proton header guards, #1213 (RLC phased porting) remains updated; the codex/musa-ci-20261011 branch continues pushing on 10-12 (MUSA CI readiness building).
  • Enflame: FlagGems #7054 merged—fixes the gcu300 benchmark treating CPU fallback as baseline, which caused ~60x inflated speedup; Torch-FL #499 switches GCU embedding to native topsatenEmbedding (converting skips into hard failures); on the vLLM side, S60 adaptation to 0.28.0 (#582) is under review; FlagTree #1353’s CommonIR five-backend manifest includes enflame, and #1239 (FlagPrism analyzer / debugger integration) remains updated.

3.5 DAMO XuanTie and Zhenwu PPU / Ascend: XuanTie TLE Line, PPU Capability Expansion, and Ascend Fix Batch (10-12 ~ 10-13)

Date: 2026-10-12 ~ 2026-10-13　Source: FlagGems-vllm #899 · FlagGems-vllm #916 · FlagGems #7050 · vllm-plugin-FL #574 · FlagTree #1189 · vllm-plugin-FL #487

  • DAMO XuanTie: FlagGems-vllm #899 merged (chunk_kda TLE path, abandoning K=192); the tuning batch in #916 covers XuanTie; FlagGems #7050 (XuanTie / MetaX linalg_matrix_power fix) is under review; vLLM 0.28 adaptation (#574) remains updated—TLE and inference stack lines advance in parallel.
  • Zhenwu PPU: FlagTree #1189 updates Zhenwu’s integer dot and dot_scaled support via backend capability contract (merged), with the capability surface continuing to expand (continuation of last issue’s PPU CI dual-repo landing).
  • Ascend: vLLM 0.28 upgrade (#487) merged as one of the first landing points; FlagGems #6949 / #7013 both merged (grid overflow fix and auto-blockify extension); under review #7048 (GRU launch capping coreDim), #6930 (cudnn_convolution), and FlagTree #1273 (TLE reduce sum strength) remain updated.

3.6 Remaining Members: Hygon / VeriSilicon / Cambricon / Horizon (10-12)

Date: 2026-10-12　Source: FlagAttention #94 · FlagCX #643 · FlagDNN commits · Four vendors on the same stage (ZAKER)

  • Hygon: FlagAttention #94 merged (miniMax sparse attention Hygon optimization); FlagDNN adds Hygon equivalence performance standards; FlagCX #643 (Hygon Device API and IR CI tests) remains updated (10-13 01:13); the FlagGems-vllm #916 tuning batch covers Hygon.
  • VeriSilicon: No GitHub activity within this window; on the news side, only the industry review article in 2.4.
  • Cambricon / Horizon: No GitHub or news activity within this window (quiet window).

IV. Summary and Trend Observations

1. A distinct “pre-conference engineering week” pattern: 68 merges, 18 repos pushed, 13 repos merged — intensity on par with the post-holiday surge; but the content structure shifted from “feature development” to “pre-launch consolidation” — five categories of activity (de-boxing, CI lanes, version tags, build matrices, release documentation) appeared simultaneously within 24 hours (one each from Torch-FL / build-infra / FlagTree / FlagGems / docs). With 4 days remaining until the October 17-18 conference, external release cadence (FlagOS 2.2, QuantumAI Cloud Platform teaser) and internal engineering consolidation are proceeding in parallel.

2. Kunlunxin’s “CUDA de-boxing” is the most technically significant single change in this window: #502 replaced the CUDA-boxing approach landed just two days earlier with a native XPU path (libxpurt device layer + xdnn operator layer) across 47 files, followed by a CI lane within 2.5 hours and a first-run fix submitted in the early morning — the full “rapid trial → replacement → managed hosting” loop completed within 24 hours, indicating that the organization’s governance of vendor backends has moved from “able to integrate” to “managed under a standardized path.”

3. The vLLM 0.28 adaptation batch is entering its landing phase: Iluvatar / Ascend first batch merged; Moore Threads (#575 high-frequency cross-day updates), XuanTie (#574), and Enflame S60 (#582) under review — the previous observation of “five lines still under review” resolved two lines within a day, with the remaining lines still in motion; once this batch completes, vendor inference stacks will be unified on the 0.28 baseline, providing the version foundation for end-to-end demos during the conference.

4. Dense signals of “new fronts opening” on the development line: FlagGems opened a 5.5 development line (v5.5.0.dev0), the FlagTree Iluvatar build line advanced to 0.7.1a1, and the organization added the Trident compilation bridge repo — all three appearing within the same 24-hour window, compounded by FlagMega’s token-level quantization optimization on BI-V150 and the TileIR 13.4 upgrade (#1352) under review; the compilation and operator stack is in a superposition state of “closing out the previous delivery cycle + laying out the next.”

5. Next observation points: Conference (10-17 / 18) on-site announcements (FlagOS 2.2, QuantumAI Cloud Platform, and post-conference external materials); FlagQuantum 0.3.0 official release (consolidation cadence after three consecutive rcs); Torch-FL #504 merge and Kunlunxin CI first green; merge order of the remaining three vLLM 0.28 lines (MUSA / XuanTie / S60); whether the FlagMega branch converts to a PR and merges into mainline; 2.3-cycle FEP and milestone progress.

Appendix: Source Verification Table

Source Verification Method Result
GitHub org repos API (window pushes) All 56 repos; 18 repos pushed within window (details in 1.1)
GitHub Commit search (committer-date) 90 hits, all verified individually via API and categorized by repo
GitHub Merged PR search (is:merged) 68 PRs, 13 repos; details in 1.2 ~ 1.9
GitHub Open PR search (is:open) 192 updates; top 100 verified individually (FlagGems 54 / FlagTree 10 / vllm-plugin-FL 8 predominant)
GitHub Tag / Release atomic verification 26 repos’ releases + 7 repos’ tags; 2 new tags (FlagGems v5.5.0.dev0 / FlagTree 0.7.1a1+iluvatar3.6); no new Release objects
GitHub Branch / atomic source supplementary verification FlagFFT / docs / release-info / Trident / FlagTree (feature/flagmega etc.) — 5 repos’ window pushes verified branch by branch
Release artifacts release-info gh-pages Pushed 10-12 14:21 (release timeline site update)
News Google News RSS (24 sets of Chinese/English queries, via proxy) 22 hits: 7 included (consolidated into 4 events), 15 excluded (market pieces / gambling SEO / irrelevant content)
News Tavily supplementary search Conference full agenda, CIIF Guoxin Exhibition, MetaX award verified via original sites (CSDN / 21jingji / stockstar repost pages)
Community HN Algolia 8 query sets rechecked; no direct hits
Official channels CSDN column / BAAI Hub No new articles within window on column homepage (top still late-August content); no in-window entries detected on BAAI Hub
Conference channel bagevent registration page Agenda details (sub-forums / speakers / time and venue) verified
Historical comparison 10-12 daily report (previous issue) Deduplication check: previous issue covered through 10-12 06:00; all items in this issue postdate that cutoff

Complete Source List