Research window: 2026-09-23 10:00 ~ 2026-09-24 10:00 (approx. 24 hours; continues from the 09-23 daily report window with no gap) Sources: GitHub (org: flagos-ai, full review of pushed_at across 54 repositories, 23 repositories had pushes within the window; commit search returned 211 hits across 13 repositories; tags.atom verified per-repository for official release tags; release manifests and PR texts from community and build-infra compared item by item), Google News RSS (24 sets of Chinese and English query terms, via proxy), reports from Cailian Press / Guangming Online / Zhidx (Chipstuff) / Securities Times, etc. (see appendix source list for details)

Issue Index

  • Today’s Focus: 4 days to 2.2 GA (09-28) — official checklist begins including L1 operator libraries: ten components’ formal version tags land in bulk (09-24)
  • I. Open Source Project Progress (GitHub Activity)
    • 1.1 Release Engineering Supplement: rc2 checklist 13 modules post tags finalized; FEP-0085 scope narrowed (09-24)
    • 1.2 build-infra: FlagGems upgraded to 5.4.0, sglang0.5.12-thead-ppu2.1.0 application page, megatron_rl matrix opens 18 backends (09-23/09-24)
    • 1.3 FlagTree: 0.7.0 platformization tags produced in bulk — ppu / mthreads / xpu / tsingmicro / ascend five platforms landed (09-23/09-24)
    • 1.4 FlagGems: KernelGen adds 16 more Nvidia operators; Kunlunxin 31-operator optimization batch merged (09-23/09-24)
    • 1.5 FlagQuantum: Cirq and Qiskit Aer execution bridge landed — 35 commits in a single window (09-23/09-24)
    • 1.6 FlagSparse: AlphaSparse collaboration with six merges; ASCEND data and DCU / MUSA optimization advances (09-23/09-24)
    • 1.7 Inference and Plugin Lines: FlagGems-vllm 13 commits across four platforms in the same window; FlagGems-sglang fused MoE router three-way merge (09-23)
    • 1.8 Other Activity: Torch-FL platform detection unified; TE-FL MetaX layout support and PPU CI; Megatron-LM-FL two fixes (09-23/09-24)
  • II. News Coverage and Ecosystem
    • 2.1 AICC2026 post-conference summary released: Cailian Press reiterates FlagOS’s positioning in the diverse computing power ecosystem (09-23)
    • 2.2 3D computing power software foundation follow-up: Guangming Online publishes “Domestic 3D Computing Power Chip Ecosystem Construction Accelerates” (09-23)
    • 2.3 DAMO XuanTie: SAIL software stack expands open source, GitHub development branch to become the main R&D line (09-23)
    • 2.4 Component-level search: nineteenth consecutive quiet window (09-23/09-24)
  • III. Member Company Deep Dive
    • 3.1 Moore Threads: RLinf official CI integrates MTT S5000 — moving from “one-way adaptation” to “two-way co-building” (09-22/09-23 coverage)
    • 3.2 MetaX: Three lines in the same window — TE layout support, jit_fuser fix, persistent_topk (09-23)
    • 3.3 Ascend: FlagGems fix batch and FlagGems-vllm four operators; vLLM 0.28 adaptation under review (09-23/09-24)
    • 3.4 Hygon: mv optimization and INT8 RMSNorm registration; FlagSparse DCU series (09-23)
    • 3.5 Iluvatar CoreX: Iluvatar image rows and build authorization; solve_triangular TLE path closed (09-23/09-24)
    • 3.6 Enflame: sglang fused router upstream merge; image row registration (09-23)
    • 3.7 Tsingmicro: FlagTree platform tags and image rows — 3D computing power narrative in parallel (09-23/09-24)
  • IV. Summary and Trend Observations
  • Appendix: Source Verification Table
  • Complete Source List

Today’s Highlight: 4 Days to 2.2 GA (09-28) — Official Manifest Begins Accepting L1 Operator Libraries: Ten Components’ Formal Version Tags Land in Batch

Date: 2026-09-24　Source: community #114, community #113, release-2.2-rc2.yaml, official manifest release-2.2.yaml

The rc2 stabilization period enters its final day (official schedule closes 09-24, GA set for 09-28), and release engineering completed two things in the early hours of 09-24.

First, the official release manifest begins accepting L1 operator libraries. Between 01:49 and 01:50 on 09-24, formal version tags (bare version numbers, no rc / post suffix) were pushed in batch for ten L1 modules:

  • flaggems v5.4.0, flagfft v0.2.0, flagsparse v0.3.0, flagdnn v0.3.0, flagblas v0.3.0, flagtensor v0.3.0, flagaudio v0.3.0, flagattention v0.4.0, flaggems-vllm v0.2.0, flaggems-sglang v0.1.0.

Each formal tag was placed on the HEAD of the corresponding module’s rc2 branch (i.e., the latest verified post-tag commit), and after pushing, each was read back and verified against the remote one by one. The accompanying PR (community #114 “add L1 operator libraries to the 2.2 official manifest”) was opened at 01:51: it adds ten “official tag ← rc2 baseline” mappings to the official manifest release-2.2/release-2.2.yaml (flaggems v5.4.0 ← post4; flagattention v0.4.0 ← post1; flaggems-vllm v0.2.0 ← post1; flaggems-sglang v0.1.0 ← post1; all others ← post2). This PR is still under review (waiting merge). The official manifest previously contained only one entry, sglang-plugin-fl v0.2.0 (landed 09-22); this PR is the first batch inclusion at the L1 layer.

Second, the rc2 channel closed out with 13 modules’ post tags (09-24 00:42, community #113): the version fields of 13 modules in release-2.2-rc2.yaml were uniformly bumped to the latest verified tags at the HEAD of their respective rc2 branches — flaggems rc2.post4; flagfft / flagdnn / flagblas / flagtensor / flagaudio rc2.post2 (contents being the Debian / RPM packaging and Nexus release chain, plus the flagaudio gain identity fix); flagtree’s three lines 0.7.0rc2.post2; vllm-plugin-fl’s two lines post3; transformerengine-fl post2; flagscale post2. All tags were verified against the remote before pushing.

On the scope side, there was also a contraction record the same day: community #112 (FEP-0085) noted that rc2 testing found no implementation of GEMM+ReduceScatter in either FlagCX 0.14.0-rc2 or FlagTree 0.7.0-rc2-triton3.6 (see FlagCX#620); after consultation with the development line, the operator was moved out of 2.2 scope, with the FEP document, test plan, and implementation history revised in sync (this PR is still under review).

Assessment: The batch landing of formal tags + rc2 manifest closeout + scope contraction all appearing in the same window indicates that 2.2’s release surface has shifted from “code freeze” to “release artifact freeze” — manifest, tags, and scope are beginning to cross-validate one another. The observation points over the next four days are the merge of #114 and the inclusion order of the L2 / L3 batches (vllm-plugin-FL, TE-FL, FlagScale, KernelGen, etc.).

I. Open-Source Project Progress (GitHub Activity)

Window Overview: Of the 54 repos in the org, 23 had pushes during the window; commit search returned 211 hits (across 13 repos): FlagGems 59, build-infra 46, FlagQuantum 35, FlagSparse 20, FlagGems-Experimental 13, FlagGems-vllm 13, Torch-FL 10, FlagGems-sglang 5, docs 4, FlagTree 2, FlagAttention 2, community 1, FlagBLAS 1; additionally, tag and branch-side pushes for release-info (gh-pages), FlagScale, vllm-plugin-FL, TransformerEngine-FL, Megatron-LM-FL, flir, FlagFFT / FlagDNN / FlagTensor / FlagAudio, etc. were not counted in the search (tags.atom was verified repo by repo).

This window’s shape = “release artifact freeze” + “platform-surface expansion” + “operator acceptance batch”: For release engineering, see “Today’s Highlights” and 1.1 / 1.2; FlagTree’s five-platform tags and the thead-ppu application page appeared on the same day (1.2 / 1.3); FlagGems’ KernelGen batch and Kunlunxin optimization batch are pre-GA performance-target actions (1.4).

1.1 Release Engineering Supplement: rc2 Manifest’s 13 Modules Post-Tag Closure; FEP-0085 Scope Reduction (09-24)

Date: 2026-09-24　Source: community #113, community #112, community #47 tracking

  • 13-module bump (#113, merged 00:42): See the second item in “Today’s Highlights.” On the content side, changes in each module since the previous round of post tags fall into four categories: Debian / RPM packaging and the Nexus release chain (five domain operator libraries and FlagGems), FlagAudio gain identity operator fix, vllm-plugin-FL platform and shutdown fixes (#549 / #553), and TE-FL MetaX vanilla TE layout support; the FlagTree three-line post2 tags were created by each module maintainer and then verified item by item. Significance: The “final full alignment” of the rc2 line is complete; only hotfixes will be accepted afterward.
  • Scope reduction (#112, FEP-0085): rc2 testing did not find a GEMM+ReduceScatter implementation in FlagCX / FlagTree (recorded in FlagCX#620), and this operator is formally deferred out of 2.2; the wording for the three operators AllGather, ReduceScatter, and AllGather+GEMM in FEP-0085 is retained as the G4 acceptance surface. Significance: The only functional scope change in the window, and it landed in the repository through a complete chain of “test evidence + documentation revision,” a normal action under release discipline.

1.2 build-infra: FlagGems Bumped to 5.4.0, sglang0.5.12-thead-ppu2.1.0 Application Page, megatron_rl Matrix Opened to 18 Backends (09-23/09-24)

Date: 2026-09-23 ~ 2026-09-24　Source: build-infra #1080, #1081, #1057, #1079, Release Info Portal

build-infra had 46 commits in this window, with four lines running in parallel:

  • Version and manifest linkage: Bump FlagGems to 5.4.0 (#1080, 09-24 08:55) — linked with the official v5.4.0 tag, raising the FlagGems version in the 2.2 build matrix in place. This commit was merged about 7 hours after the official tag was created, a standard example of the “tag → build” sequence.
  • New application page (the most important newly visible artifact in this window): sglang0.5.12-thead-ppu2.1.0 application page (#1081, 09-24 09:45) — the DAMO XuanTie PPU sglang application image page (bilingual Chinese-English) entered the Release Info Portal. The image is the 2.2 test version of sglang0.5.12-thead-ppu2.1.0 (tag 2.2.0-beta-0.2.0, with checksum digest); the PR description states it is a manually written page, not built by the app/sglang/Containerfile pipeline (“from our own tested container,” a transitional form of register first, manage later).
  • Application matrix expansion: open the megatron_rl build matrix to all eighteen backends (#1057, 09-23 21:36) — the Megatron-RL application row restarted after being paused on 08-31: the unblocking conditions (MLF’s [rl] extra dependency declaration and the flash-attn version exemption) have both been merged, and the matrix is open to all eighteen backends. Supporting registrations: the megatron application image 2.2.0-0.2.3 landed in 14 platform rows (ascend double row, cambricon double row, iluvatar double row, metax, mthreads, tsingmicro, sunrise, enflame, kunlunxin, nvidia double row); the vLLM application image 2.2.0-0.2.2rc2.post2 and the sglang dev row landed on both Iluvatar lines.
  • Release CI hardening: pin each release build to the tag its code actually is (#1079), release verify step actually verifies and is triggered on PRs (#1078), symbol check only runs when all libraries are present (#1076), native-deb per-package enumeration (#1074), flagcx-rpm validates against the target repository (#1073) — five consecutive hardening commits, all with the semantics of “make release verification unambiguous.”
  • Also: the gh-pages branch of the release-info repo, which hosts the Release Info Portal, was rebuilt and pushed multiple times during the window (including the listing of the new application page).

1.3 FlagTree: Batch Output of 0.7.0 Platform Tags — ppu / mthreads / xpu / tsingmicro / ascend Five Platforms Land (09-23/09-24)

Date: 2026-09-23 ~ 2026-09-24　Source: FlagTree Tags, #1266, #1259, FlagTree Wiki

FlagTree produced a batch of 0.7.0-series tags during the window (the compiler version for 2.2; it was 0.6.0 in 2.1):

  • Three mainlines: 0.7.0+triton3.6, 0.7.0+triton3.5, 0.7.0+triton3.3 (09-23 19:10 ~ 19:12).
  • Five platforms: 0.7.0+mthreads3.6 (09-24 09:13), 0.7.0+ppu3.6 (09:15), 0.7.0+xpu3.6 (09:22), 0.7.0+tsingmicro3.6 (09:28), 0.7.0+ascend3.5 (09:56) — platform tags expanded from “mainline” to “vendor-specialized”, with ppu (DAMO XuanTie) as a new face this round.

On the commit side, two changes: FlagCX build dependency fix (#1266, [BUILD][FlagCX]) and PPU CI adding a pid check (#1259, [CI][PPU]). On the documentation side: the repo wiki had 4 page updates between 09:29 and 09:57 (multi-platform user manuals, including ppu / tsingmicro entries) — a signal of pre-release documentation preparation.

1.4 FlagGems: KernelGen Adds 16 More Nvidia Operators; Kunlunxin 31-Operator Optimization Batch Merged (09-23/09-24)

Date: 2026-09-23 ~ 2026-09-24　Source: FlagGems #6412, #6591, #6233, #6020, FlagGems-Experimental

  • KernelGen (Nvidia) 16 merged: put (#6020), quantize_per_tensor (#5941), row_indices_copy (#5939), kaiser_window (#6363), hspmm (#6182), batch_norm_backward_elemt (#5727), linalg_inv_ex (#5297), conj_physical (#5923), _linalg_svd (#5920), _pin_memory (#5921), _ctc_loss_backward (#5499), _cudnn_attention_backward (#5724), linalg_matmul (#5617), _aminmax (#5924), _stack (#5940), _trilinear (#6143); three more are under review (quantized_batch_norm, quantize_per_channel, put). The KernelGen long-tail supplementation cadence continues, and 16 in a single window is one of the recent peaks for this line.
  • Kunlunxin 31-operator optimization batch (#6412): 31 optimized operator implementations merged at once, of which 27 / 31 reached the 0.8x performance line; supporting changes include skipping FP8 tests on Kunlunxin (#6573), removing the import-time monkey patch (#6625), and fixes for std and special functions (#6550 / #6485 / #6585). This is a typical batch in the “acceptance + tuning” window shape — no longer adding new operators, but pushing existing operators past the performance line.
  • Hygon / Moore Threads: mv operator backend optimization implementation merged (#6591, [Hygon][MThreads]).
  • FlagTune (auto-tuning): Hopper and MetaX MM cost model support (#6233); FP8 MM local tuning enabled (#6620); legacy model validation fallback support under review (#6649).
  • Ascend fix batch: apply_rotary_pos_emb cos/sin duplication issue (#6613), batched linalg_solve_triangular incorrect results (#6596), INT8 RMSNorm registration and W8A8 HCU loading fix (#6611), log_ grid padding fix (#6579, merged 09-24 10:00).
  • Testing and CI infrastructure: candidate pre-check and in-process profiling hooks (#6621), benchmark profile collection changed to pytest plugin injection (#6628), weekly backend container image update (#6630), flagtree replaced with triton in CI (#6626), pad_sequence shared dtype mutation fix (#6618).
  • FlagGems-Experimental: 13 commits in the same window — 11 Kunlunxin specializations (#706 ~ #717 series) + 2 Nvidia (_dimI, _nnz).

1.5 FlagQuantum: Cirq and Qiskit Aer Execution Bridges Land — 35 Commits in a Single Window (09-23/09-24)

Date: 2026-09-23 ~ 2026-09-24　Source: FlagQuantum #206, #204, #202, #199

FlagQuantum had 30+ commits for the second consecutive window (38 in the 09-22 window, 35 in this window), with four lines running in parallel:

  • Multi-framework interoperability (this window’s theme): Cirq Simulator execution bridge (#206), Qiskit Aer namespace alignment (#205) and explicit execution bridge (#204), Cirq matrix gate custom unitary contract (#196), Cirq terminal measurement conversion (#194), Cirq measurement contract (#190) — following Braket / CUDA-Q / Azure in the previous window, both the Cirq and Qiskit Aer mainlines are now connected, and the “multi-framework execution bridge” matrix is approaching completeness.
  • Simulation performance: large-size CPU state-vector dense fusion widening (#201), non-adjacent two-qubit CPU gate acceleration (#199), adjacent two-qubit gates routed by shape (#195), batched two-qubit layer fusion (#181) — large-state performance continues to be strengthened.
  • Benchmarking and evaluation: simulator comparison report generation (#203), Cirq and PennyLane CPU run rounds (#202), interoperable CPU simulator comparison (#200).
  • Robustness gates: explicit reporting of MPS dense fallback (#198), tensor-network noise-channel rejection documentation (#197), explicit rejection of multiple wire out-of-bounds and illegal sampling budgets (#176 / #177 / #179 / #182 / #185 / #186 / #187 / #192).

1.6 FlagSparse: Six AlphaSparse Collaboration Merges; ASCEND Data and DCU / MUSA Optimization Advance (09-23/09-24)

Date: 2026-09-23 ~ 2026-09-24　Source: FlagSparse #81 to #86

FlagSparse had 20 commits and six upstream merges in this window (#81 ~ #86 are all NCIC-AlphaSparse-side syncs) — bilateral collaboration with NCIC-AlphaSparse has entered a high-frequency period:

  • Data and fixes: ASCEND numerics and tianshu debugging, biv f32/f64 transpose defect fix, precision supplementation.
  • Platform optimization: DCU checklist and spv precision, MUSA optimization, CI refinement.
  • Structure: Merge branch 'main' of ... bidirectional syncs alternating with ci again / ci refines, a collaboration shape of “R&D advances on the fork side and is fed back in merge batches.”

1.7 Inference and Plugin Lines: FlagGems-vllm 13 Commits Across Four Platforms in the Same Window; FlagGems-sglang Fused MoE Router Merged in Three Paths (09-23)

Date: 2026-09-23　Source: FlagGems-vllm #835, #845, #834, FlagGems-sglang #106, vllm-plugin-FL #530

  • FlagGems-vllm (13 commits, four platforms in the same window): Moore Threads shared INT4 / FP8 fused Marlin MoE (#835) and TLE-optimized topk_softplus_sqrt (#838), silu_and_mul_with_clamp performance optimization (#839); DAMO XuanTie TLE version of topk_softplus_sqrt (#845); Ascend lightning indexer (#791), kv_rmsnorm_rope_cache (#790), indexer_gemm_score (#819), group_list_cumsum (#818), top_k_per_row refactor fix (#841); MetaX persistent_topk MC550 backend (#834); Gemma RMSNorm completed for three platforms at once (Ascend #762 / DAMO XuanTie #766 / Moore Threads #782). “Contrasting implementations of the same operator across multiple platforms” has become this repo’s standard working mode.
  • FlagGems-sglang (5 commits): fused MoE router merged in three paths — Kunlunxin and MUSA integration (#106), two Ascend tensorcore variants (#102 / #104), Enflame tensorcore dot-acc (#105).
  • vllm-plugin-FL: dual-line post3 tags landed (see “Today’s Highlights”); the review queue continues to expand — Biren SUPA backend (#530, a new vendor face), Ascend vLLM 0.28 adaptation (#487, 910C), Sunrise 0.2.1 patch port (#555), operator-level profile (#422), compile-time dispatch freeze (#448); there is also a ci workflow optimization branch push.

1.8 Other Activity: Torch-FL Platform Detection Unified; TE-FL MetaX Layout Support and PPU CI; Two Megatron-LM-FL Fixes (09-23/09-24)

Date: 2026-09-23 ~ 2026-09-24　Source: Torch-FL #405, #399, TE-FL #128, #129, Megatron-LM-FL #185

  • Torch-FL (10 commits): platform detection unified and capability matrix documentation added (#405); FlagGems RNG bridge remains installed when the module is abnormal (#406); multi-device contract CI selected by marker (#407); Ascend topk falls back to the aclnn kernel (#399); SDPA routing head_dim / dtype / query-length boundaries relaxed (#404); sparse COO constructed on flagos devices (#403); version pins centralized in a single file (#401); PPU _unsafe_view and slice routing (#397); strided softmax operand materialization on MUSA (#398); import-time side effects consolidated into an ordered phase pipeline (#396).
  • TransformerEngine-FL: MetaX vanilla (≥2.13) TE package layout support (#128, including cherry-pick #130 to the 0.3.0-rc2 line); PPU unit and integration test support under review (#129, updated 09-24 09:24); NPU Grouped GEMM checkpoint save compatibility under review (#120).
  • Megatron-LM-FL: jit_fuser kept as a no-op on MetaX builds to prevent memory leaks (#185 / #186, including cherry-picks); Sunrise PT-PU as a supported platform (#181); txda graph capture state truthfully reported (#180); two related MC550 defect tickets closed.
  • FlagScale: v2.1.0-rc2.post2 tag; PR queue (MemRift training compression #1274, NPU profiler #1294 / #1297, heartbeat false-alarm fix #1268, PPU 810E training CI #1300, Hygon DCU health sampling #1299).
  • FlagAttention: v0.4.0 tag; test runner dependency sync (#73), documentation update (#72).
  • docs / flir: four model manifest updates (ModelScope / HuggingFace, etc.); flir repo development branch push.

II. News Coverage and Ecosystem

2.1 AICC2026 Post-Event Roundup Released: Cailianshe Reiterates FlagOS’s Position in the Diversified Computing Power Ecosystem (09-23)

Date: 2026-09-23　Source: Cailianshe (republished by East Money)

On 09-23, Cailianshe published the AICC2026 roundup “Agents Accelerate Toward Deployment — How Will the Computing Power Industry Break Through?” FlagOS-related content: remarks at the conference by Lin Yonghua, Vice President and Chief Engineer of BAAI — “AI workloads will not converge, nor will computing architectures be reduced to just one. For hardware innovation to translate into usable computing power, it needs the support of a shared software ecosystem. Zhongzhi FlagOS lowers the repeated adaptation cost of diverse chips through unified compilers, operators, communication, and training/inference frameworks, enabling different computing architectures to enter the AI ecosystem faster.” The same article also includes: MIIT’s Jin Lei on requirements for factor coordination, conference initiator Wang Endong’s “three structural problems,” SGLang core contributor Zhang Xiaoyu’s argument on unifying Kernel interfaces, IDC’s forecast for agent and Token growth rates, and the list of 20-plus co-builders of the “Reliable AI” evaluation system. This article is the post-event roundup of conference coverage from 09-21 to 09-22, once again placing FlagOS’s “unified software stack” positioning at the center of the industry narrative.

2.2 Follow-Up on the 3D Computing Power Software Foundation: Guangming Online Publishes “Ecosystem Building for Domestic 3D Computing Power Chips Accelerates” (09-23)

Date: 2026-09-23　Source: Guangming Online, CNR (09-18 background), Xinhua Net (09-14 background)

On 09-23, Guangming Online published an article focused on Open3D-PIMC (a 3D computing power chip programming model and open-source framework jointly developed by Qingwei Intelligent and BAAI, now incorporated into the FlagOS system): the core facts match the earlier coverage (the release took place on 09-11 at the China Computing Power Conference; Xinhua Net reported on 09-14 and CNR on 09-18; this daily brief also covered it in the 09-14 to 09-18 window), and this piece is a post-conference follow-up. Incremental information: remarks by BAAI AI Systems Research Lead Men Chunlei and Qingwei Intelligent Software Vice President Li Bin are cited again — “the lack of a supporting compiler leads to advanced hardware and inefficient software” and “Open3D-PIMC targets more than 30 domestic chips and explores a global standard for 3D chip compilers.” Assessment: this is an extension of an already-covered topic, for ecosystem tracking purposes.

2.3 DAMO XuanTie: SAIL Software Stack Expands Open Source, GitHub Development Branch to Become the Main R&D Line (09-23)

Date: 2026-09-23　Source: Xinzhidong (under Zhidx, Chen Junda)

On 09-23, Xinzhidong published a long-form article on the DAMO XuanTie (T-Head) software stack, “Opening Up the Low-Level Software Stack, Trying to Let the Ecosystem Grow”:

  • New developments: On the day after the Yunqi Conference opened (09-22), DAMO XuanTie announced the latest progress on open-sourcing the SAIL software stack, declaring further expansion of open-source efforts in framework adaptation, acceleration libraries, toolchains, communication libraries, and other areas; Senior Director of Software Ecosystem Lu Shenghua said SAIL open-source code has been published to GitHub, and “future development branches based on GitHub will serve as the main R&D line.”
  • Data points: As of September, 39 quantized models aligned with Zhenwu hardware’s low-precision features have been open-sourced, with cumulative downloads exceeding 348,000; SAIL has adapted more than 260 frameworks including PyTorch / TensorFlow / vLLM / SGLang, with average adaptation time for mainstream inference frameworks under 7 days; the Zhenwu series has served more than 650 enterprise customers (including the Zhenwu V900 released on 09-22).
  • Link to FlagOS: The sglang0.5.12-thead-ppu2.1.0 application page newly added to build-infra the same day and FlagTree’s 0.7.0+ppu3.6 tag (see 1.2 / 1.3) indicate that DAMO XuanTie PPU is entering FlagOS’s build and application matrix in a real capacity; the “open-source software stack + GitHub mainline” approach is in sync with FlagOS’s “unified stack for diverse chips” in ecosystem narrative.

2.4 Component-Level Search: Nineteenth Consecutive Quiet Window (09-23/09-24)

Date: 2026-09-23 to 2026-09-24　Source: Google News RSS (via proxy)

Across 24 Chinese and English query sets (7 component names plus ecosystem and member-organization terms), searches for component names within the 24-hour window recorded a nineteenth consecutive window with zero hits; ecosystem-side hits were all extensions of conference-season coverage (see 2.1 to 2.3). Baidu searches for “FlagOS” still return official sources mainly from the BAAI community and GitHub. Quiet windows have become the norm, and FlagOS’s incremental external information remains concentrated around release cadence and conference milestones.

III. Member Unit Deep Dive

3.1 Moore Threads: RLinf Official CI Integrates MTT S5000 — From “One-Way Adaptation” to “Two-Way Co-Building” (09-22/09-23 coverage)

Date: 2026-09-19 (salon) ~ 2026-09-23 (coverage)　Source: Securities Times · People’s Finance, EEFocus, PChome

The “MUSA Open Source Tech Salon: RLinf × MUSA Meetup” hosted by Moore Threads (09-19, Beijing) disclosed a set of embodied intelligence reinforcement learning benchmark results: RLinf official CI has integrated MTT S5000 since version 0.3, requiring all code merged into the main branch to pass automated verification on domestic compute; RLinf now officially supports the MUSA backend. Key data: under 248 parallel environments, identical recipes, and random seeds, the S5000 training curve achieves a stepwise correlation coefficient of r = 0.976 with mainstream international GPUs (191-step common window); in real-machine LIBERO-Spatial evaluation, policy success rates align across both hardware sets; on the engineering side, full-step time dropped from 2549 seconds to 1888 seconds (-26%), and GPU idle rate compressed from 18.5% to 3.1%; operator-level benchmarks show S5000’s GEMM and attention performance reaching 1.6–2× that of mainstream international GPUs. The two parties will also co-build an end-cloud collaborative framework (cloud S5000 / edge MTT E300). “From one-way adaptation to two-way co-building” is the core characterization of this entry — an open-source framework writing domestic compute into its CI directory represents a shift in ecosystem positioning.

Operator-side actions in the same window: FlagGems mv optimization (#6591), FlagGems-vllm shared INT4 / FP8 fused Marlin MoE (#835) and TLE topk_softplus_sqrt (#838), FlagGems-sglang MUSA fused router (#106), FlagSparse MUSA optimization, Torch-FL MUSA strided softmax fix (#398), FlagTree 0.7.0+mthreads3.6 tag.

3.2 MetaX: Three Tracks in the Same Window — TE Layout Support, jit_fuser Fix, persistent_topk (09-23)

Date: 2026-09-23　Source: TE-FL #128, Megatron-LM-FL #185, FlagGems-vllm #834

MetaX left substantive actions across three repositories in this window:

  • TE-FL: Support for vanilla (≥2.13) TE package layout (TE_METAX_TE_HOME environment variable path); after #128 merged, it was cherry-picked to the 0.3.0-rc2 line via #130 — also entering the post tag content of rc2.post2 (see “Today’s Highlights,” item two).
  • Megatron-LM-FL: jit_fuser remains no-op on MetaX builds to prevent memory leaks (#185 / #186); two related MC550 training interruption and Triton compilation defect tickets closed.
  • FlagGems-vllm: persistent_topk adds MetaX MC550 backend (#834).
  • Also: FlagGems’ FlagTune cost model covers MetaX MM (#6233), build-infra MetaX image lines maca3.7.2.1 / 3.8.1.3 continuously registered. The action density on the MetaX line is strongly correlated with rc2 closure — all three fixes made it into the 2.2 release artifacts.

3.3 Ascend: FlagGems Fix Batch and FlagGems-vllm Four Operators; vLLM 0.28 Adaptation Under Review (09-23/09-24)

Date: 2026-09-23 ~ 2026-09-24　Source: FlagGems #6613, FlagGems-vllm #791, vllm-plugin-FL #487, Torch-FL #399

  • FlagGems fix batch: apply_rotary_pos_emb cos/sin duplication (#6613), batched linalg_solve_triangular incorrect results (#6596), log_ grid padding (#6579), INT8 RMSNorm registration and W8A8 HCU loading (#6611, same commit as Hygon).
  • FlagGems-vllm four operators: lightning indexer (#791), kv_rmsnorm_rope_cache (#790), indexer_gemm_score (#819), group_list_cumsum (#818), plus Gemma RMSNorm (#762) and top_k_per_row refactor (#841).
  • Plugins and frameworks: vllm-plugin-FL’s Ascend vLLM 0.28 adaptation (#487, 910C) under review; Torch-FL’s Ascend topk fallback to aclnn (#399); FlagSparse ASCEND numerical and tianshu debugging; build-infra Ascend image lines cann8.5.0 / cann9.0.0 dual-line registration.

3.4 Hygon: mv Optimization and INT8 RMSNorm Registration; FlagSparse DCU Series (09-23)

Date: 2026-09-23　Source: FlagGems #6591, FlagGems #6611, FlagSparse, FlagScale #1299

Hygon (DCU) left traces across three repositories in this window: FlagGems’ mv backend optimization (#6591, same commit pattern as Moore Threads), INT8 RMSNorm registration and W8A8 HCU loading fix (#6611); FlagSparse’s DCU checklist and spv precision series submissions (dcu check list / dcu spv acc); FlagScale’s DCU hardware health sampling PR (#1299, under review). The action pattern is concentrated at the “precision and acceptance” level, consistent with the rc2 stabilization phase positioning.

3.5 Iluvatar: Iluvatar Image Lines and Build Authorization; solve_triangular TLE Path Closed (09-23/09-24)

Date: 2026-09-23 ~ 2026-09-24　Source: build-infra #1052, #1041, FlagGems #6595

  • Image registration: Megatron application line 2.2.0-0.2.3 lands on both Iluvatar lines (corex4.4.0 / 4.5.0); vLLM application line 2.2.0-0.2.2rc2.post2 lands on the same two lines; sglang dev line two entries; changelog authorizes Iluvatar application image rebuild (#1041).
  • Operator side: FlagGems closes the TLE path for Iluvatar’s linalg_solve_triangular (#6595, forming a contrast with the Ascend fix for the same operator).
  • Combined with the previous window’s Iluvatar wheel rebuild (Ubuntu 22.04), the Iluvatar line’s share in 2.2 release artifacts continues to expand.

3.6 Enflame: sglang Fused Router Upstream Merge; Image Line Registration (09-23)

Date: 2026-09-23　Source: FlagGems-sglang #105, build-infra

Enflame’s actions in this window are concentrated in FlagGems-sglang: Enflame tensorcore dot-acc fused router branch upstream merge (#105), landing in the same window as Kunlunxin / MUSA / Ascend; on the build-infra side, megatron application image line enflame-tops1.10.6 registered. No new acquisition/capital-side developments entered the window (A-share listing was covered on day one, omitted).

3.7 Tsingmicro: FlagTree Platform Tag and Image Line — 3D Compute Narrative in Parallel (09-23/09-24)

Date: 2026-09-23 ~ 2026-09-24　Source: FlagTree Tags, build-infra

Tsingmicro has two tracks in this window: Engineering side — FlagTree issues the 0.7.0+tsingmicro3.6 platform tag (09-24 09:28), build-infra’s megatron image line tsingmicro-tsm260610 continuously registered; Ecosystem side — Open3D-PIMC post-event coverage continues (see 2.2), with the “enterprise core contribution + open-source community co-building” 3D compute software narrative advancing in parallel with the FlagOS multi-backend landscape.

IV. Summary and Trend Observations

  • The 2.2 release surface enters “release artifact freeze”: ten-component official version tags batch-landed (01:49 ~ 01:50), rc2 checklist 13-module post tags closed (00:42), FEP-0085 scope contraction (17:52) — three lines completing the alignment of “tags, checklist, scope” within the same window. 4 days from GA (09-28), the rc2 stabilization period ends today; the observation point shifts to checklist L2 / L3 batch inclusion and Go/No-Go.
  • The platform surface continues to expand, with differing paths: thead-ppu2.1.0 application page represents a transitional form of “manual registration, later managed”; FlagTree’s five-platform tags formally incorporate “vendor specialization” into the version system; vllm-plugin-FL’s Biren SUPA backend PR is another example of “new vendors entering through the plugin repo.” The multi-chip landscape continues to expand before GA.
  • Operator libraries fully shift into “acceptance and tuning” cadence: KernelGen 16 in a single window (long-tail supplementation continues) + Kunlunxin 31-operator optimization batch (27/31 meeting targets) + mv / GEMM / attention multi-platform fixes — fully consistent with the post-feature-freeze scheduling pattern, with the final week’s performance actions before GA released in concentrated form.
  • Quantum and sparse, two “non-mainline” components, establish their own rhythm: FlagQuantum with 30+ entries across two consecutive windows and completing the Cirq / Qiskit Aer dual bridge; FlagSparse and NCIC-AlphaSparse with six bilateral synchronization entries. Their engineering maturity has risen significantly before GA, constituting long-term observation items beyond 2.2.
  • External information surface: conference season finale + open software stack narrative in sync: AICC2026 post-event recap restates FlagOS positioning, Open3D-PIMC follow-up coverage, DAMO XuanTie SAIL “GitHub R&D mainline” — two narratives, domestic AI chips’ “software stack openness” and FlagOS’s “unified multi-stack,” released in concentrated form in the same week, while component-level search remains in its nineteenth quiet window, indicating that information increments are still driven by release cadence rather than the media side.
  • To watch: ① community #114 merge and L2 / L3 batch inclusion; ② official Release and documentation corresponding to the FlagTree 0.7.0 series tags (wiki already under preparation); ③ subsequent management of DAMO XuanTie PPU at the runtime / compiler / operator layers (TE-FL PPU CI, FlagGems-vllm TLE operators are already leading signals); ④ merge progress of new vendor backends such as Biren SUPA and Sunrise.

Appendix: Source Verification Table

Category Source Verification Method Result
GitHub org: flagos-ai repos API Full verification of pushed_at across 54 repos 23 repos active within window
GitHub Commit search + per-repo cross-check Item-by-item verification within window 211 entries (13 repos); branch and tag-side pushes not counted
GitHub tags.atom per-repo cross-check Official tags for ten components v5.4.0 / v0.4.0 / v0.3.0×5 / v0.2.0×2 / v0.1.0, 10 total; FlagTree 0.7.0 series, 8 total
Release Engineering community #112 / #113 / #114 and manifest originals Item-by-item comparison rc2 closes out 13 modules; L1 inclusion PR pending merge; FEP-0085 shrink under review
Release Engineering build-infra PR and release-info portal Original text retrieval and cross-check FlagGems 5.4.0 bump; thead-ppu application page; megatron_rl 18-backend matrix
News Google News RSS (24 query sets in Chinese and English, via proxy) 24-hour window filter + item-by-item exclusion Zero hits on component terms (19th quiet window); 3 items retained on ecosystem side
Media Cailian Press / GMW.cn / Xindongxi (Zhidongxi) / Securities Times / EEFocus Original text retrieval and review AICC post-conference recap, Open3D-PIMC follow-up, SAIL open-source progress, RLinf hands-on test
Community HN Algolia / BAAI Community Search review No new FlagOS-related posts (all hits were fuzzy matches on unrelated terms)
Historical Comparison FlagOS daily reports from the previous three days Deduplication check Entries such as RoboBrain / FlagOS-Robo thousand-GPU training verified as old news from January, not included

Complete Source List