Research window: 2026-08-27 10:18 ~ 2026-08-28 10:18 Beijing Time Sources: GitHub (org: flagos-ai 52 repos + commit search + PR/Release API), Google News RSS (multiple Chinese and English queries, proxy chain normal), HN Algolia, Tavily/web cross-validation (see appendix for details)

Index

  • I. Open-Source Project Progress (GitHub Activity)
    • 1.1 Qwen4 sparse attention kernel five-backend batch, in sync with Qwen3.8-Flash-Next release (08-27)
    • 1.2 Torch-FL: TileOPs optional operator library integration, Apex optimizer zero-copy view enabled (08-28)
    • 1.3 FlagCX: Enflame collective flow closed loop (08-27)
    • 1.4 FlagScale: Qwen3.6 LLM Backbone and weight conversion support (08-27)
    • 1.5 vllm-plugin-FL: W8A8 inference adapted to vLLM 0.24, main-line CI migration initiated (08-27/08-28)
    • 1.6 build-infra: metax sgl-kernel wheel empirically verified free of CUDA dependency, CANN 8.5.0 dependency, verl integration plan refined (08-27/08-28)
    • 1.7 Compiler stack: flir Common IR POC, FlagTree TLE all-backend primitives (08-27)
    • 1.8 Other repository activity (FlagGems, FlagSparse, docs) (08-27/08-28)
  • II. News Coverage and Ecosystem
    • 2.1 Headline: Moore Threads and BAAI FlagOS complete Day-0 adaptation for Qwen3.8-Flash-Next (08-26/08-27)
    • 2.2 Component-level keywords: first break of zero hits in nine days
    • 2.3 Ecosystem-side observations and exclusions
  • III. Member Company Deep Dive
    • 3.1 Moore Threads: Day-0 dual-track adaptation and sgl-kernel no-CUDA empirical verification (08-26/08-27)
    • 3.2 Enflame: FlagCX communication flow closed loop (08-27)
    • 3.3 Hygon/Ascend/Iluvatar/MetaX: Qwen4 kernel five-backend coverage (08-27)
    • 3.4 AI Agent participation in FlagOS development: Apex fix submitted by Claude Code (08-28)
  • IV. Summary
  • Appendix: Complete Source List

I. Open-Source Project Progress (GitHub Activity)

Window Overview: Of the 52 repos in the org, 12 had pushes during the window; commit search returned 42 in-window commits (build-infra 12, FlagGems-vllm 5, FlagSparse 4, Torch-FL 4, FlagGems 3, docs 2, vllm-plugin-FL 2, FlagTree 2, flir/FlagScale/FlagCX 1 each). Main threads this window: 1) Operator reserves for the Qwen4 architecture — FlagGems-vllm merged 5 Qwen4 sparse attention (QSA) kernels in a single day, covering five chip backends, in sync with Alibaba’s release of Qwen3.8-Flash-Next based on the Qwen4 architecture (8/26); 2) Framework-layer architectural breakthroughs — Torch-FL integrated the TileOPs operator library (60 code-generated routes, correcting the earlier conclusion that “adapters must be hand-written”), and the Apex optimizer was enabled on flagos devices; 3) Member-company depth — Enflame’s FlagCX communication flow closed the loop, and build-infra compiled sgl-kernel with Moore Threads’ MACA toolchain, proving it has no CUDA dependency; 4) On the news side, the first break in nine days of zero component-level hits: Moore Threads, together with FlagOS, completed Day-0 adaptation of Qwen3.8-Flash-Next.

1.1 Five-backend batch of Qwen4 sparse attention kernels, in sync with the Qwen3.8-Flash-Next release (08-27)

Sources: FlagGems-vllm #715, #716, #717, #718, #719

  • From 13:52 to 23:06 on 8/27, liuhycs merged 5 Qwen4 kernel PRs in succession: qwen4_compress_norm_mrope_store_groups (compression normalization and mrope group storage), qwen4_qsa_mqa_paged_dot (QSA MQA paged dot product), qwen4_ple_state_scatter (PLE state scatter), qwen4_hc_inject_combine (HC inject combine), and qwen4_store_qsa_kv_rows (QSA KV row storage).
  • Each kernel provides vendor-optimized Triton implementations for five backends — Ascend 910, Hygon DCU, Iluvatar, MetaX, and Moore Threads (Mthreads) (e.g., Ascend 2D grid single warp, Hygon 3D grid four warps, tuned to each chip’s memory characteristics).
  • Together with the Qwen4 in-house Triton kernels and vendor baselines merged on 8/26 (#713/#681), this forms a dual track of “in-house + vendor-optimized.”

Interpretation: The core feature of the Qwen4 architecture is sparse attention (QSA) — Alibaba officially previews Qwen3.8-Flash-Next as based on the Qwen4 architecture (explicitly stated on its ModelScope page). FlagOS has completed five-backend adaptation of the full QSA kernel chain (KV storage, compression normalization, paged dot product) before the model is officially available — a Day-0 forward reserve of “operators before the model arrives”; combined with the 2.1 headline, the FlagOS adaptation chain for the Qwen4 architecture (kernels → inference → deployment) is essentially ready.

1.2 Torch-FL: TileOPs optional operator library integration, Apex optimizer enabled via zero-copy views (08-28)

Sources: Torch-FL #44, #216, #212, #211

  • #44 (merged 8/28 09:23, lvyufeng): Integrates TileOPs as an optional SM90-specific operator library, covering 60 aten-aligned routes code-generated from the TileOPs manifest (rather than hand-written). Key correction: earlier research held that “adapters must be hand-written operator by operator,” but it was found that constructor parameters can be mechanically derived from aten call sites (68 of 102 alignments can be auto-derived).
  • #216 (merged 8/28 09:22, lvyufeng): Enables NVIDIA Apex FusedAdam/SGD/LAMB optimizers by converting flagos tensors to zero-copy CUDA views at Apex’s MultiTensorApply entry point. Notably, this PR was written by Claude Code CLI (Claude Opus 5) and human-reviewed (see 3.4).
  • #212/#211 (8/27 13:10–14:47): Restore autograd for aten::narrow on PrivateUse1; copy paths across backends follow lazy conj/neg math bits.

Interpretation: Torch-FL’s path shifts from “operator-by-operator adaptation” to “manifest-based code generation + reuse of upstream operator libraries,” which will significantly lower the cost of operator coverage for new backends; enabling the Apex optimizers fills the optimizer ecosystem gap on the training side for flagos devices.

1.3 FlagCX: Enflame collective flow closes the loop (08-27)

Source: FlagCX #554 (merged 8/27 11:05, lvyufeng)

  • Completes the Enflame GCU path introduced by #546 via FLAGCX_TORCH_BACKEND=flagos: FlagOS intermediate tensor allocation and list-collective flatten/unflatten copies are all routed through FlagCX, and it does not import/link torch_gcu, keeping the PAL (portable abstraction layer) architecture clean.

Interpretation: Enflame’s adaptation at the FlagOS communication layer moves from “skeleton” to “closed loop.” Combined with yesterday’s FlagCX openEuler 24.03 RPM build matrix and Hygon DCU adaptation, FlagCX’s multi-vendor collective coverage (Ascend/Enflame/Hygon/NVIDIA) continues to expand.

1.4 FlagScale: Qwen3.6 LLM Backbone and weight conversion support (08-27)

Source: FlagScale #1273 (merged 8/27 14:24, lxd-cumt)

  • Adds support for the Qwen3.6 LLM Backbone (with the vit module disabled) and improves checkpoint conversion logic.

Interpretation: FlagScale continues to track Qwen-series iterations on the training side (previously Qwen3.5/3.8 series); the Qwen3.6 backbone merge provides a unified entry point for multi-chip training.

1.5 vllm-plugin-FL: W8A8 inference adapted to vLLM 0.24, main-line CI migration begins (08-27/08-28)

Sources: vllm-plugin-FL #336 (merged 8/27 21:26), #415, #414, #412

  • #336 (rdzhu225): Adapts compressed-tensors W8A8 inference to the vLLM 0.24 plugin line — rebuilt directly on v0.3.0-dev (replacing the 0.20.2-targeted implementation in #335): reuses vLLM 0.24’s native INT8 scaled-mm candidates, with per-token INT8 MoE routed to vLLM’s functional Triton experts path.
  • New open-PR developments: #415 (8/28) migrates CI-related code from release/0.2 to main — the 0.2 maintenance line begins to converge, with resources concentrating on main/v0.3.0; #414 optimizes vLLM 0.24 batched MTP xGrammar masks performance; #412 tunes Moore Threads GDN packed decode launch.

Interpretation: v0.3.0 is still in the rc stage (rc0 released 8/24), but merges such as W8A8 quantization adaptation and CI migration all point to the imminent official v0.3.0 release; the low-bit (W4A16/W8A8) dual-precision paths advance in parallel on the main line.

1.6 build-infra: metax sgl-kernel wheel empirically has no CUDA dependency, CANN 8.5.0 dependencies, verl integration plan refined (08-27/08-28)

Sources: build-infra #598, #597, #596, #595, #594, #593, #591

  • #598 (merged 8/28 07:57, tengqm): Uses Moore Threads’ mxcc (MACA) toolchain to compile a 10-operator subset of sgl-kernel and packages it as sgl_kernel 0.4.1+flagos (cp312, linux_x86_64), empirically proving sgl-kernel does not depend on CUDA; sglang 0.5.10 on metax passes serve sampling E2E via both flagtree / vendor triton compilation paths.
  • #597 (8/27 21:38): Fills in Ascend CANN 8.5.0 runtime dependencies (decorator/attrs/psutil) — the Ascend validation line follows CANN 8.5.
  • #596 (8/27 21:32): Pins numpy==1.26.4 across the full stack (all backends) — eliminating numpy 2.x compatibility drift.
  • verl plan refinement (#591/#593/#594/#595): The sglang research doc is made self-contained; the verl app image plan specifies Path B follows the vllm 0.20.2 fork branch line, records TE-FL wheel feasibility, marks FlagCX as a non-hard dependency, and installs verl with its dependencies, landing as a megatron-core base wheel.

Interpretation: The theme of this build-infra cycle is “making validation and packaging repeatable engineering”: the metax compilation proof for sgl-kernel means the inference kernel layer is no longer bound to CUDA — direct evidence on the packaging side for the “unified stack, multiple chips” narrative; verl integration (RL framework) continues to advance, and the framework landscape is nearly complete.

1.7 Compiler stack: flir Common IR POC, FlagTree TLE all-backend primitives (08-27)

Sources: flir #68, community #95, FlagTree #1054, #1053

  • flir #68 (merged 8/27 16:38, zhongsanming): [KMCompiler][TLE] Common IR POC (Triton 3.5) — introduces a new Common IR as a complement to TTIR, exposing a lower-level abstraction to the operator layer to unlock more optimization opportunities; environment requires CANN 9.1.0+, Ascend 910B/910C. Related to community #95 FEP(sig-compiler): Common IR serves as the input receiving layer for a unified IR (DSA/GPGPU), enhancing TLE’s data representation and pipeline control abstractions.
  • FlagTree #1054 (8/27 20:43): [TLE] Adds a list of supported TLE primitives for each backend; #1053 (8/27 14:11) [XPU] fixes a Discrete offset chain wraparound issue.

Interpretation: The FlagOS compiler stack (FlagTree/flir/KMCompiler) enters the “IR abstraction layer design” stage — the Common IR proposal is a forward-looking design for unified compilation targeting DSA (domain-specific accelerators) and GPGPU, while the all-backend TLE primitive list improves compiler front-end consistency.

1.8 Other repo activity (08-27/08-28)

  • FlagGems: #5800 (merged 8/28 10:11, tspyc072) adds the conj_physical_ operator (complex-tensor contiguous-view Triton kernel, no launch for real tensors); #5787 CI rule-check phase 1 and 2 (gavin0x01); #5777 cleans up dead ATen registrations and non-standard registration names. Wave of open PRs (15+ created 8/27–28): KernelGen batch Nvidia operators (ldeexp/masked_select_backward/cudnn_rnn/_thnn_fused*cell series/_fused_adagrad/histogramdd and 9 others), Hygon FlashAttention forward/backward fix (#5822), Kunlunxin slice_scatter out-of-bounds fix (#5816), Moore Threads channel_shuffle block-copy optimization (#5814), QC FP8 W8A8 FlashAttention-2 (#5817), KMCompiler Ascend linalg_solve_triangular (#5821).
  • FlagSparse: #48 (merged 8/27 18:50, zyq1105331849) updates the spmm BELL format and spsv SELL format — sparse matrix kernels continue to be filled in.
  • docs: #476/#477 (merged 8/27 10:33, github-actions bot) sync ModelScope model READMEs (17 new files) and the model list — the FlagRelease model repo keeps updating with new adaptations.

II. News Coverage and Ecosystem

2.1 Headline: Moore Threads and BAAI FlagOS Complete Day-0 Adaptation for Qwen3.8-Flash-Next (08-26/08-27)

Sources: Sina Finance reprint of Beijing Business Today (8/27), East Money (indexed 8/27; Beijing Business Today filed at 21:57 on 8/26), ModelScope Qwen3.8-Flash-Next official page

  • Alibaba Qwen recently open-sourced the multimodal MoE model Qwen3.8-Flash-Next (based on the Qwen4 architecture, featuring a novel sparse attention mechanism; official release was previewed for 8/26 15:00 UTC).
  • Moore Threads announced on 8/27 that, leveraging its full-ecosystem compatibility, it rapidly completed Day-0 standalone adaptation of the model on the MTT S5000 based on Triton; in parallel, jointly with the Zhongzhi FlagOS community, it completed Day-0 adaptation, precision alignment, and deployment validation, becoming the first to offer a BF16 precision version, now open-sourced on ModelScope and HuggingFace, giving developers an out-of-the-box solution.
  • The FlagRelease (FlagOS official) account on ModelScope already hosts Qwen3.8-series multi-chip quantized images (e.g., Qwen3.8-2.4T-A95B-INT8-metax-FlagOS); this BF16 release continues to use that distribution channel.

Analysis: This is the second consecutive Day-0 for the Qwen3.8 series on the FlagOS side (8/13 was Day-0 for Qwen3.8-2.4T across nine chips; 8/17 was Qwen3.8-27B across eleven chips). This time Moore Threads led the effort and presented it in a dual-track form of “standalone adaptation + joint FlagOS.” The cadence of “multi-chip adaptation completed on model release day” has shifted from exception to norm; the new Qwen4 architecture features (sparse attention) and the earlier FlagGems-vllm Qwen4 kernel groundwork (1.1) corroborate each other — behind the adaptation speed lies kernel engineering that began months in advance.

2.2 Component-Level Keywords: First Break in Nine Days of Zero Hits

Across multiple gnews queries in Chinese and English (FlagOS/FlagGems/FlagScale/FlagTree/FlagPerf/FlagAttention/FlagCX/KernelGen/FlagOS-Robo/FlagQuantum/FlagPrism when:7d/14d), the FlagOS keyword scored 1 hit on 8/27 (the 2.1 headline, reprinted via Beijing Business Today/Sina Finance/East Money), breaking a record of eight consecutive days of zero component-level hits; the remaining component names (FlagGems/FlagScale/FlagTree, etc.) still returned zero hits. HN Algolia (FlagOS/FlagGems) produced only irrelevant false matches; Tavily cross-validation confirmed this news item was the only component-level report within the window. The overall pattern on the news side — “GitHub activity dominant, media exposure sparse” — remains unchanged, but the propagation chain for model Day-0 adaptation news (vendor official → financial media → financial platforms) has now stabilized.

2.3 Ecosystem Observations and Exclusions

  • BAAI Community 8/26: “China’s AI Breakthrough in ‘Chipmaking Methodology’! Agent Legions Take Over the Entire Chip Design Workflow” — a methodology report on AI Agents for chip design, not a FlagOS component update, and outside the window, so excluded from the main text (forming an interesting echo with the Claude Code development PR in 3.4).
  • BAAI Community 8/28 08:30 (Beijing): Zhipu GLM-5.3-Flash released (the “mystery Niu Lai model” revealed) — a domestic model-side development with no FlagOS adaptation report yet; placed under observation.
  • BAAI Community 8/22: FlagEval-Robo officially released (“simulation + real machine” dual-track evaluation, establishing a true capability benchmark for embodied intelligence) — a background item outside the window; BAAI’s embodied evaluation toolchain echoes the FlagOS-Robo direction, and the embodied end-to-end data pipeline direction tracked in this month’s report continues to show ecosystem signals.
  • Other BAAI Community articles (HuggingFace acquisition rumors, Opus 5.1, OpenAI in-house chips, etc.) are all macro industry developments and excluded.

III. Deep Dive into Member Organizations

3.1 Moore Threads: Day-0 Dual-Track Adaptation and sgl-kernel CUDA-Free Proof (08-26/08-27)

Sources: Sina Finance, build-infra #598, FlagGems-vllm #715/#719

  • Moore Threads advanced on three fronts within the window: on the news side, it led the MTT S5000 Day-0 standalone adaptation of Qwen3.8-Flash-Next plus joint synchronized adaptation with FlagOS (BF16 open-sourced on ModelScope/HF); on the operator side, it submitted mthreads-optimized implementations of the Qwen4 QSA kernel series to FlagGems-vllm; on the packaging side, it compiled a 10-operator subset of sgl-kernel with the mxcc/MACA toolchain and completed E2E validation of the dual-compilation path for sglang 0.5.10, proving that inference kernels can break free of CUDA.
  • Connecting with yesterday’s report (full-chain validation of dual MUSA versions of Megatron turning green): Moore Threads’ participation in FlagOS spans four layers—validation, operators, kernel packaging, and model adaptation.

3.2 Enflame: FlagCX Communication Flow Closed Loop (08-27)

Source: FlagCX #554

  • The FlagCX collective path for Enflame GCU (FLAGCX_TORCH_BACKEND=flagos) completed its closed loop: intermediate tensor allocation and list-collective copies are all routed through FlagCX, without introducing a torch_gcu dependency. Following Enflame’s participation in yesterday’s multi-backend maintenance of vllm-plugin-FL for Ascend/Cambricon, its communication-layer adaptation has advanced another step.

3.3 Hygon/Ascend/Iluvatar/MetaX: Five-Backend Coverage of Qwen4 Kernels (08-27)

Sources: FlagGems-vllm #715-#719, Torch-FL #212, build-infra #597

  • All 5 Qwen4 kernels in FlagGems-vllm cover five backends—Ascend 910, Hygon DCU, Iluvatar, MetaX, and Moore Threads (vendor-optimized versions); among them, Hygon additionally has an open FlagGems PR for a FlashAttention fix (#5822). On the Ascend side, build-infra filled in the CANN 8.5.0 runtime dependencies, with the validation line following up on the new software stack version. Multiple vendors merging in “the same batch of kernels on the same day” is the underlying engineering guarantee for Day-0 capability.

3.4 AI Agent Participation in FlagOS Development: Apex Fix Submitted by Claude Code (08-28)

Source: Torch-FL #216

  • The PR description for Torch-FL #216 (enabling Apex FusedAdam/SGD/LAMB) notes that it was written by Claude Code CLI (Claude Opus 5, 1M context) and manually reviewed by @lvyufeng; the entire workflow—from “investigating Apex failures on flagos devices → locating the MultiTensorApply entry point → zero-copy CUDA view approach → fix”—was completed by an AI Agent.
  • Interpretation: This is the first merged PR in the FlagOS repositories explicitly labeled as fully written by an AI Agent (repositories such as AiMOS previously had bot-submission conventions, but this is an LLM programming Agent). This corroborates the BAAI Community’s 8/26 report on “Agent legions taking over chip design”—open-source system software stack development is becoming an early high-value scenario for AI programming tools; this model is additional leverage for FlagOS’s narrative of “a unified stack reducing the labor cost of multi-chip adaptation.”

IV. Summary

Window Main Threads: One, Qwen4 architecture reserves and Day-0 adaptation resonating in sync—FlagGems-vllm merged 5 Qwen4 sparse attention kernels in a single day (QSA KV storage/compression normalization/page dot product, etc.) covering five backends—Ascend/Hygon/Iluvatar/MetaX/Moore Threads—and on the same day Moore Threads jointly with FlagOS announced completion of Day-0 adaptation for Qwen3.8-Flash-Next (based on the Qwen4 architecture), with the BF16 version open-sourced to ModelScope and HuggingFace, breaking an eight-day zero-hit streak for component-level news. Two, framework-layer architecture upgrades—Torch-FL integrated the TileOPs code-generation operator library (60 aten routes) and enabled Apex optimizers, while FlagScale added a Qwen3.6 backbone. Three, “CUDA-free dependency” proof—build-infra compiled sgl-kernel with the Moore Threads MACA toolchain and passed E2E on the dual-compilation path, yielding reproducible evidence of de-CUDA-binding at the inference kernel layer. Four, depth across member organizations—Enflame’s FlagCX communication flow closed loop, Ascend’s CANN 8.5.0 follow-up, and the vllm-plugin-FL 0.2 maintenance line converging toward migration to main. Five, AI Agent development model appears in FlagOS—an Apex fix PR fully written by Claude Code was merged.

Next Watch Points: vllm-plugin-FL v0.3.0 official release (rc0 is out; W8A8 0.24 adaptation and CI migration have been merged into the main line); the BF16 image of Qwen3.8-Flash-Next landing on the ModelScope FlagRelease account and multi-chip expansion; out-of-the-box validation of Qwen4 QSA kernels on the vllm side; FlagScale Qwen3.6 training validation; SIG progress on flir Common IR (community #95); final acceptance wrap-up of FlagGems 5.3.5 across all backends; OASIS-AI call for papers closing 8/31.

Limitations Note: Commit counts and merge times come from commit search and the repos/commits API (the search index may lag slightly; the flagtree-cpu push within the window was a PR branch push with no new merges to the main branch, which has been verified); the publication time of the Qwen3.8-Flash-Next report is Beijing Business Today 8/26 21:57, indexed by gnews at 8/27 08:08, at the edge of the window start (8/27 10:18); it had not yet been indexed when yesterday’s report was collected, so it is included here as in-window news; “written by Claude Code” is based on the PR description’s self-report; the BF16 image link for the ModelScope FlagRelease account was not directly verified (the ModelScope search page only shows historical images such as INT8), so the official report’s wording is taken as authoritative.

Appendix: Complete Source List

No. Event Source Link
1 Moore Threads and BAAI FlagOS complete Qwen3.8-Flash-Next adaptation (Beijing Business Today / Sina Finance) https://finance.sina.com.cn/jjxw/2026-08-27/doc-inipuqhs0655624.shtml
2 Same story (East Money) https://wap.eastmoney.com/a/202608273856909629.html
3 Qwen3.8-Flash-Next official page (ModelScope, Qwen4 architecture notes) https://modelscope.cn/models/Qwen/Qwen3.8-Flash-Next
4 FlagGems-vllm Qwen4 compress_norm_mrope_store_groups (#719) https://github.com/flagos-ai/FlagGems-vllm/pull/719
5 FlagGems-vllm Qwen4 qsa_mqa_paged_dot (#718) https://github.com/flagos-ai/FlagGems-vllm/pull/718
6 FlagGems-vllm Qwen4 ple_state_scatter (#717) https://github.com/flagos-ai/FlagGems-vllm/pull/717
7 FlagGems-vllm Qwen4 hc_inject_combine (#716) https://github.com/flagos-ai/FlagGems-vllm/pull/716
8 FlagGems-vllm Qwen4 store_qsa_kv_rows (#715) https://github.com/flagos-ai/FlagGems-vllm/pull/715
9 Torch-FL TileOPs integration (#44) https://github.com/flagos-ai/Torch-FL/pull/44
10 Torch-FL Apex optimizer zero-copy views (#216, written by Claude Code) https://github.com/flagos-ai/Torch-FL/pull/216
11 Torch-FL aten::narrow autograd restoration (#212) https://github.com/flagos-ai/Torch-FL/pull/212
12 FlagCX Enflame collective flow (#554) https://github.com/flagos-ai/FlagCX/pull/554
13 FlagScale Qwen36 backbone + CKPT conversion (#1273) https://github.com/flagos-ai/FlagScale/pull/1273
14 vllm-plugin-FL W8A8 adaptation for vLLM 0.24 (#336) https://github.com/flagos-ai/vllm-plugin-FL/pull/336
15 vllm-plugin-FL CI migration to main (#415) https://github.com/flagos-ai/vllm-plugin-FL/pull/415
16 build-infra metax sgl-kernel wheel (#598) https://github.com/flagos-ai/build-infra/pull/598
17 build-infra cann8.5.0 runtime deps (#597) https://github.com/flagos-ai/build-infra/pull/597
18 build-infra numpy 1.26.4 full-stack pinning (#596) https://github.com/flagos-ai/build-infra/pull/596
19 build-infra verl Path B plan (#595) https://github.com/flagos-ai/build-infra/pull/595
20 flir KMCompiler Common IR POC (#68) https://github.com/flagos-ai/flir/pull/68
21 community FEP sig-compiler Common IR (#95) https://github.com/flagos-ai/community/pull/95
22 FlagTree TLE all-backend primitives (#1054) https://github.com/flagos-ai/FlagTree/pull/1054
23 FlagSparse spmm/sp sv update (#48) https://github.com/flagos-ai/FlagSparse/pull/48
24 FlagGems conj_physical_ operator (#5800) https://github.com/flagos-ai/FlagGems/pull/5800
25 FlagGems CI rule-check phase 1/2 (#5787) https://github.com/flagos-ai/FlagGems/pull/5787
26 docs ModelScope model list sync (#476/#477) https://github.com/flagos-ai/docs/pull/477
27 org repos overview (52 repos, 12 active within window) https://api.github.com/orgs/flagos-ai/repos?per_page=100&sort=updated
28 commit search (42 unique commits within window) https://api.github.com/search/commits?q=org:flagos-ai+committer-date:%3E2026-08-27T02:18:00Z
29 gnews component-level query (1 FlagOS hit, zero for the rest) https://news.google.com/rss/search?q=FlagOS+when%3A7d&hl=zh-CN&gl=CN&ceid=CN%3Azh-Hans
30 HN Algolia (irrelevant false match) https://hn.algolia.com/api/v1/search_by_date?query=FlagOS
31 FlagEval-Robo release (BAAI community, 8/22, background item) https://hub.baai.ac.cn
32 GLM-5.3-Flash release (BAAI community, 8/28, watch item) https://hub.baai.ac.cn