Research window: Past 24 hours (2026-09-16 05:18 ~ 2026-09-17 05:18, Beijing time) Sources: Hacker News, Google News aggregation (multiple Chinese and English queries, via proxy), EE Times Asia, Futurum Group, HPCwire, XDA, Tampere University, OSCHINA, deepin community (community monthly report, planet.deepin weekly, deepin-ports SIG blog), openRuyi official website, RISC-V International Foundation member company website sweep (391 companies), and GitHub (XiangShan/XSCache/NEMU/GEM5/difftest, revyos, Sophgo, SpacemiT, Sipeed, DAMO XuanTie, Espressif, Radxa Linkr and other organizations and key repositories’ push and commit searches)

Index

  • Today’s Highlights: The RISC-V data center narrative shifts from “launch” to “third-party validation” — the AMD ROCm 10.0 inference demo on the SiFive BigSky platform enters independent analysis follow-up (09-16); on the domestic side, the deepin 25 RVA23 release completes adaptation for SpacemiT K3 (09-17)
  • I. Open Source Community and Software Ecosystem
    • XiangShan: Vector floating-point unit refactoring, VFALU and VFMul merged into VFMac fused unit (09-16)
    • XiangShan: Batch of 13 timing optimizations landed, covering memory access and rename critical paths (09-16)
    • XiangShan simulation chain GEM5: Branch prediction moved to pipeline stage 2 and 3 other items (09-16)
    • XiangShan simulation chain NEMU: Interrupt throw path log format unified (09-16)
    • revyos: SG2044 UEFI firmware build extension and boot chain adjustments (09-16)
    • openRuyi: September release page still does not exist, specification files continue to be filled in (09-16 check)
    • Tampere University: Research on customized tools for RISC-V processor design (09-16)
  • II. Product and Ecosystem Updates
    • SiFive BigSky completes AMD ROCm 10.0 inference demo, industry discusses its “neutral head node” positioning (09-16)
    • RISC-V cores inside NVIDIA GPUs already handle a large amount of graphics driver work (09-16)
    • deepin 25 RVA23 release adapts to SpacemiT K3, small-form-factor board runs large models locally (09-17)
  • III. Domestic Team Deep Dive
    • DAMO XuanTie: Two toolchain repos have pushes within the window, no new commits on maintenance branches (09-16 check)
    • SpacemiT: Bianbu documentation v4.0.7 and Spine-Runtime documentation refactoring (09-16)
    • Sophgo: sophon-tools unified build image v1.2.0, built-in domestic GOPROXY and Win7 flashing toolchain (09-16)
    • Sipeed: SLogic16U3 mass production flashing toolchain refactoring (09-16)
  • IV. Embodied Intelligence and Robotics Special Chapter
    • SpacemiT spacemit-robotics: Upper body motion takeover capability merged into humanoid common library and Linglong (09-16)
    • SpacemiT spacemit-robotics: G1 manual reference trajectory replay and constraint documentation (09-17)
    • UC Berkeley: Machine learning and robotics tutorial for heterogeneous RISC-V systems-on-chip (09-17)
  • V. Summary and Trend Observations

Today’s Focus: The “Third-Party Validation” Phase for RISC-V in the Data Center

Date: 2026-09-16　Sources: Futurum Group, “SiFive Demos AMD ROCm on RISC-V. Is BigSky Now the Neutral Head Node?”, HPCwire, “SiFive and AMD Collaborate to Optimize AMD ROCm on RISC-V Datacenter Servers”

On September 15 at the AI Infra Summit in Santa Clara, SiFive and AMD demonstrated large-model inference running on AMD ROCm atop the SiFive BigSky datacenter development platform. The new information in this issue comes from third-party analysis that appeared the following day: the demo used ROCm 10.0 to host Gemma 4 E2B model inference, with a SiFive Performance P870-D processor acting as the head node and an AMD Radeon AI PRO R9700 GPU handling inference offload. The demo system, BigSky SF-2U870, is specified with 32 P870-D cores at 2.0 GHz, 256 GB of DDR5-5600 memory, four PCIe Gen5 x16 slots (64 lanes total), two 7.68 TB U.2 NVMe SSDs, and 10/25 Gb networking.

Two judgments from the analyst firm are worth noting. First, the “launch narrative” is being replaced by “time-to-arrival”: when BigSky launched on August 24, the industry positioned it as a validation platform to “compress the customer software porting phase”; CUDA was running on the large-model head node on launch day, and ROCm 10.0 followed within three weeks—both GPU software stacks landed on the RISC-V host side within three weeks of the platform’s market debut, reducing the risk premium for hyperscale customers evaluating RISC-V head nodes in next-generation custom SoC projects. Second, the notion of the “neutral head node”: a RISC-V host simultaneously supporting both the CUDA and ROCm accelerator ecosystems gives RISC-V a chance to become a neutral host not tied to any single GPU vendor—which is the origin of the question posed in the analysis headline.

The boundaries must be made clear: this demonstration is a “demo-only” system, the model is compact in scale, and the GPU is a workstation-class product; SiFive and AMD say they will continue to evaluate ROCm optimization on RISC-V servers, targeting larger models and more acceleration scenarios. The corresponding observation point on the domestic industry side is whether the combination of “open instruction set plus open software stack” can form reusable software assets on the datacenter side (see the isomorphic path on the edge side in 2.3).

I. Open-Source Community and Software Ecosystem

1.1 XiangShan: Vector Floating-Point Unit Refactored, VFALU and VFMul Merged into VFMac Fused Unit

Date: 2026-09-16　Source: OpenXiangShan/XiangShan commit log

A grouped set of vector unit changes was merged into the main XiangShan repository during the window: complete datapaths for VFALU, VFMul, and VFMac were added, and the original VFALU and VFMul functional units were merged into a single VFMac fused unit, with the supporting arithmetic unit implementations updated as well. A separate fix(vfmac) corrects mask writeback for floating-point compare instructions—i.e., floating-point compare results are no longer redundantly written back to the vector mask register, avoiding disruption of subsequent computation sequences that depend on the mask. The author dates for this batch cluster between September 11 and September 15, marking it as newly developed work (not a backlog batch). The direction is consolidation and streamlining of the vector floating-point multiply-add path: fused multiply-add is a key structure for vector compute utilization, and merging functional units typically means fewer issue ports and bypass conflicts and a shorter critical path.

1.2 XiangShan: Batch of 13 Timing Optimizations Landed, Covering Memory Access and Rename Critical Paths

Date: 2026-09-16　Source: OpenXiangShan/XiangShan commit log

The same batch also merged 13 timing optimizations, with author dates spanning August 31 to September 10, making this a batch wrap-up merge. By module: page table walk (PTW) optimizes second-level address generation; on the memory access side, replay reasons are precomputed, timing paths for the bitmap and load replay queue are corrected, the uncached and prefetch paths are shortened, the unaligned forwarding path is optimized, the illegal issue check is moved forward to stage S0, and pipelining is added to the vector store queue’s recovery and dequeue paths; on the rename side, free-list pre-allocation is simplified. This concentration of critical-path convergence work ahead of tapeout or performance benchmarking is consistent with earlier observations in this report.

1.3 XiangShan Simulation Chain GEM5: Branch Prediction Moved to Pipeline Stage 2, Plus 3 Other Items

Date: 2026-09-16　Source: OpenXiangShan/GEM5 commit log

Four effective commits in the XiangShan companion GEM5 model window: MBTB (multi-branch target buffer) and TAGE prediction were moved to pipeline stage 2, aligning prediction timing with the real microarchitecture’s staged structure; a 3-cycle latency was set for vector memory access writeback in the out-of-order core; the second-level request source tag is preserved during cache buffering, fixing loss of request source; and there is one change to link-layer parameter settings. All four share the same goal—gradually aligning the simulation model’s timing assumptions with the hardware implementation.

1.4 XiangShan Simulation Chain NEMU: Unified Log Format for Interrupt Raise Path

Date: 2026-09-16　Source: OpenXiangShan/NEMU commit log

One commit in the XiangShan reference simulator NEMU window, unifying the log format of the interrupt raise function. This is an observability maintenance change with no functional or performance advance, recorded for traceability.

1.5 revyos: SG2044 UEFI Firmware Build Expansion and Boot Chain Adjustments

Date: 2026-09-16　Source: firmware-sg204x commit log, zsbl commit log

Work continued in the revyos firmware repositories for the Sophgo SG2042/SG2044 platforms: CI adds two SG2044 board firmware variants (SD3-10 and SD3-12), the device tree source switches to the 7.3 kernel branch, build targets converge to EDK2 firmware only, the toolchain cache is fixed, and x64 UEFI emulation support is enabled for SG2042; the companion zsbl (zero-stage boot loader) now loads the EDK2 device tree from a standard-named device tree file. This indicates that the platform’s UEFI boot chain and firmware delivery process are being engineered toward convergence rather than remaining at single-board spot checks.

1.6 openRuyi: September Release Page Still Nonexistent, Spec Files Continue to Be Filled In

Date: 2026-09-16 ~ 09-17　Source: openRuyi official news page, openRuyi repository commit log

A check of this report’s regular source, the openRuyi distribution (led by the Institute of Software, Chinese Academy of Sciences): the September release page still returns nonexistent, and the latest official release remains 2026.08 (released August 27). On the repository side, spec file (SPECS) work continued to be merged during the window, adding or fixing Go ecosystem and Kubernetes-related packages (including code generators, dependency injection frameworks, gRPC examples, etc.) and completing libabigail’s dependency declarations—routine filling-in of the distribution’s package library, with no version-level signal yet.

1.7 Tampere University: Research on Customized Tools for RISC-V Processor Design

Date: 2026-09-16　Source: Google News inclusion: Tampere University report

Finland’s Tampere University published a report on the work of researcher Kari Hepola: using customized compilation and design tools to make RISC-V processor design faster and easier. The report covers academic-side toolchain work and is included here under the “ecosystem foundational research” category, without capability assessment. The public value of this direction lies in the fact that the degree of automation in processor design toolchains directly determines the barrier to entry for small and mid-sized teams and universities pursuing their own RISC-V IP.

II. Product and Ecosystem Updates

2.1 SiFive BigSky Completes AMD ROCm 10.0 Inference Demo; Industry Discusses Its “Neutral Head Node” Positioning

Date: 2026-09-16　Source: EE Times Asia report (indexed by Google News), Futurum Group analysis

The demo (see today’s top story) entered a phase of follow-up coverage by international media and analyst firms on September 16. EE Times Asia reported it under the headline “SiFive and AMD Demo ROCm AI Workloads on RISC-V Data Center Platform,” while analyst firms further discussed whether a RISC-V host platform can become a neutral head node not tied to any single GPU vendor. The implication for the domestic industry: RISC-V’s path to data center deployment is shifting from “chip performance benchmarking” to competition along the dimensions of “software stack delivery speed and ecosystem neutrality.” This report previously covered the release of the demo itself; this issue adds the follow-up analysis and third-party commentary without repeating the release information.

2.2 RISC-V Cores Inside NVIDIA GPUs Already Handle Much of the Graphics Driver Work

Date: 2026-09-16　Source: XDA, “Your Nvidia GPU has dozens of RISC-V cores inside it”

Tech outlet XDA published a long-form explainer tracing the history of NVIDIA embedding RISC-V microcontrollers in its GPUs: early designs used the in-house FAst Logic CONtroller (Falcon) as the logic controller, before switching to RISC-V starting in 2016, after which the architecture settled into “multiple embedded RISC-V microcontrollers per chip.” One of these became the GPU System Processor (GSP), which since 2018 has taken over a substantial portion of the work previously handled by the graphics driver, translating high-level commands from the host-side driver into internal GPU register operations. The article notes that as more control was handed to this RISC-V processor, open-source drivers gained capabilities such as frequency control that were previously impossible. Scope note: This is a retrospective piece aimed at a general audience, not an official NVIDIA announcement; statements such as “dozens of RISC-V cores” and “driver takeover” are drawn from public technical materials and open-source driver progress. Its value lies in illustrating that RISC-V shipment volumes have long since entered mainstream compute chips at scale via embedded controllers, rather than existing only in standalone processor products.

2.3 deepin 25 RVA23 Edition Adapts to SpacemiT K3; Small-Form-Factor Board Runs Large Models Locally

Date: 2026-09-17　Source: OSCHINA, “Small board runs large models: deepin 25 RVA23 edition adapts to SpacemiT chip K3”, deepin Community Monthly Report (August), planet.deepin community blog

The deepin community’s RVA23 edition for RISC-V has completed adaptation to the SpacemiT K3 chip, enabling small-form-factor boards to run large models locally. Based on deepin community public materials, the technical highlights of this work include: the RVA23 repository packaging enables the GCC 16 toolchain with RVA23 support, and pushes GCC 15 and binutils patches for SpacemiT’s IME vector extension into the next repository; on the image side, it updates the K3 device image, unifies the platform kernel and bootloader source addresses under SpacemiT’s official organization, and builds both the K3 U-Boot and ESOS components within the kernel build process; on the application side, llama.cpp and ggml full-architecture builds were previously completed with GGUF model inference verified, RVV acceleration was confirmed effective on K3, and local models run on 8 AI cores. Assessment: On-device (board-level) large model inference is currently the scenario where the gap between RISC-V and desktop-class x86/ARM is smallest and where scaled deployment is most likely; the real-world benefits of the RVA23 specification and vector extension (RVV) will be measured by joint “distribution plus chip” adaptation results like this one.

III. Deep Dive on Domestic Teams

3.1 DAMO XuanTie: Pushes in Two Toolchain Repos Within the Window, No New Commits on Maintenance Branches

Date: 2026-09-16　Source: XUANTIE-RV/gcc branches and commits, XUANTIE-RV/binutils-gdb branches and commits

Following the daily GitHub organization review process, we checked the DAMO XuanTie (XUANTIE-RV) toolchain repositories: gcc (65 branches) and binutils-gdb (316 branches) both showed pushed_at updates within the window. After branch-by-branch verification, we confirmed that no new commits landed on the maintenance branches within the window — the latest GCC-side commit is on the xuantie-gcc-14.3.0 branch (September 13), and the latest binutils-side commit is on the xuantie-binutils-gdb-2.42 branch (September 13), with no new branches appearing in the window. We therefore judge this push to be a repository action at the reference or tag level, with no new code merged; this report records it faithfully as “push verified, no new commits” to avoid misreading a repository action as version progress.

3.2 SpacemiT: Bianbu Documentation v4.0.7 and Spine-Runtime Documentation Restructuring

Date: 2026-09-16 ~ 09-17　Source: docs-bianbu commit history, spine-runtime commit history

SpacemiT’s official documentation repository merged the v4.0.7 release notes (one Chinese and one English version) within the window; the Chinese version was completed the previous day, with the English version added in this period — a routine synchronization of release documentation. Under the same organization, the spine-runtime repository completed a documentation restructuring — the repository name points to a runtime framework, about which relatively little public information has been disclosed previously; systematic documentation organization typically appears at the stage of productization push, and is worth tracking going forward.

3.3 Sophgo: sophon-tools Unified Build Image v1.2.0, Bundling a Domestic GOPROXY and a Windows 7 Flashing Toolchain

Date: 2026-09-16　Source: sophon-tools commit history

Sophgo’s toolset repository committed feat(docker): 统一构建镜像 v1.2.0 within the window: the build image switches to a domestic GOPROXY mirror source and pre-bundles a flashing toolchain targeting Windows 7. For a chip vendor, the availability of the build image and flashing pipeline directly affects the onboarding efficiency of customers and ecosystem partners — compatibility with domestic sources and legacy Windows clients is an engineering optimization for actual domestic production environments, not a feature expansion. A previous issue already covered this repository’s move to incorporate the SE flashing tool (which by default outputs only a Windows version and does not bundle an image); this period represents continued refinement of the same product line.

3.4 Sipeed: SLogic16U3 Mass-Production Flashing Toolchain Refactoring

Date: 2026-09-16　Source: slogic16u3-tools commit history

Sipeed’s logic analyzer product line tool repository saw 9 commits within the window, concentrated on refactoring the mass-production flashing pipeline: unifying the switching flow between DFU and APP modes (a three-stage sequence of USB reconfiguration, flasher fallback, and UI prompts); consolidating all flasher operations under a single command-line prefix and removing wrapper scripts; adding external flasher detection and staged UI enablement; making eFuse writing and locking a precondition for blank flashing and removing the standalone button; correcting the run number used for the bitstream firmware in blank flashing; hardening Windows packaging (Python version check and DLL bundling) and exposing the APP-side USB serial number for version identification. Signal significance: moving from “can flash” to “mass-producible, traceable, and resistant to misoperation” is a typical toolchain investment as a hardware product enters the volume delivery stage.

IV. Embodied Intelligence and Robotics Special Section

4.1 SpacemiT spacemit-robotics: Upper-Body Action Takeover Capability Merged into Humanoid Common Library and Linglong

Date: 2026-09-16　Source: humanoid_common commit log, humanoid_linglong commit log

The SpacemiT robotics software stack organization resumed activity during the window (the previous period had no pushes). humanoid_common merged two capabilities: manual reference playback and upper-body action takeover; humanoid_linglong (Linglong humanoid robot) concurrently merged standing policy interaction and the first round of interaction policy configuration, and merged the action takeover feature. Interpretation: Action takeover means upper-layer applications can temporarily take over control of upper-body joints (e.g., teleoperation or manual intervention). Combined with “reference trajectory playback,” this forms a foundational capability for humanoid robots in real-machine debugging, teaching, and safe takeover scenarios—a necessary engineering step from “the policy can run” to “humans and machines can collaboratively debug.” This report has previously documented the organization’s progress in perception modules and whole-body control; this period continues the trajectory in motion policy and interaction layers.

4.2 SpacemiT spacemit-robotics: G1 Manual Reference Trajectory Playback and Constraint Documentation

Date: 2026-09-17　Source: humanoid_unitree_g1 commit log

In the same batch, the repository targeting the Unitree G1 humanoid platform merged manual reference trajectory playback support and supplemented it with constraint documentation for the feature (specifying the replayable state range and limitations), followed by merging the corresponding feature branch. Three repositories (common library, Linglong, G1) completed alignment on the same feature within the same time window, indicating that this capability is a unified cross-platform implementation rather than a single-model customization.

4.3 UC Berkeley: Tutorial on Machine Learning and Robotics for Heterogeneous RISC-V Systems-on-Chip

Date: 2026-09-17　Source: IISWC 2026 tutorial repository

The UC Berkeley BAR group created a tutorial site repository for the 2026 IISWC conference, titled “Building, Tracing, and Optimizing End-to-End Machine Learning and Robotics Workloads on Heterogeneous RISC-V Systems-on-Chip,” using the lightweight Zephyr real-time runtime as the vehicle. Observations: First, the topic places “ML workloads” and “robotics workloads” side by side, consistent with the domestic industry’s positioning of “RISC-V plus embodied intelligence”; second, it adopts a lightweight real-time kernel like Zephyr rather than Linux, indicating the tutorial targets the real-time constraints of robot control loops; third, as teaching material from an academic group aimed at an industry conference (IISWC), it typically reflects their judgment on the future skill stack of engineering talent.

V. Summary and Trend Observations

The main thread on the industry side this period is “validation,” not “launch.” Independent analytical follow-ups on the SiFive–AMD ROCm demo appeared the day after launch, with the discussion shifting from “can it run on RISC-V” to “time-to-availability and ecosystem neutrality” — two GPU software stacks landing on the RISC-V host side within three weeks of platform launch is seen by analyst firms as a signal of reduced customer risk premium. The strength of this narrative depends on whether Instinct-level validation follows; the demo system remains positioned as “demo only.” On the domestic side, the deepin 25 RVA23 release completed adaptation to the SpacemiT K3, and joint “distro plus chip” adaptation on the edge continues to advance in small, rapid steps, forming an isomorphic relationship with progress on the datacenter side: both are speaking in terms of “is the software stack in place” rather than pure performance metrics.

The technology side this period centers on two things. The first is the XiangShan vector pipeline refactor: VFALU and VFMul merged into a VFMac fused unit with a new datapath, a newly developed result (author dates September 11–15), layered on a batch of 13 memory-access and rename timing optimizations — still a “critical-path convergence ahead of performance benchmarking” cadence; the accompanying GEM5 moves branch prediction into the second pipeline stage, and NEMU unifies interrupt logging, with the simulation chain continuing to align with hardware timing assumptions. The second is domestic vendors’ toolchain and volume-delivery capabilities: Sophgo’s unified build image switches to domestic mirrors and preloads a legacy Windows flashing tool, Sipeed refactors the logic analyzer’s flashing path into a production-ready DFU flow, and SpacemiT adds English release notes and reorganizes runtime documentation — none of this work appears on performance leaderboards, yet it directly determines customer onboarding and delivery efficiency.

Three threads to track. First, the DAMO XuanTie toolchain repos show “pushes present but no new commits on the maintenance branch” — watch whether this is a precursor to version tagging or branch restructuring. Second, the openRuyi September release page continues not to exist (verified across multiple consecutive periods); if there is still no release this month, the distro’s cadence warrants attention. Third, SpacemiT’s spacemit-robotics motion takeover and trajectory replay capabilities — when will these expand from “public libraries and single models” to full-robot demos or a publicly released SDK.

Source Verification Table

Source Verification Result
Google News aggregation (English: RISC-V, SiFive, RISC-V datacenter/RVA23, RISC-V Linux kernel, RISC-V robotics, Andes/StarFive/Milk-V/SOPHGO, RISC-V Summit) Valid: follow-up analysis of the SiFive–AMD ROCm demo (included in today’s highlights and 2.1), explainer coverage of RISC-V cores inside NVIDIA GPUs (included in 2.2), coverage of Tampere University’s processor design tools (included in 1.7); Excluded: MLPerf cluster benchmarks (unrelated to RISC-V), AMD SEV-TIO kernel patches (x86 security feature), automotive chip market size forecasts, Infineon’s sale of its NOR flash business, mismatches with the Chilean Andes地名 and ski events (entire batch excluded)
Google News aggregation (Chinese: RISC-V, XuanTie/DAMO, XiangShan processor, SpacemiT, Sophgo, ESWIN, etc.) Valid: deepin 25 RVA23 adaptation to K3 (OSCHINA, included in 2.3); Noise: Nuclei matches on nuclear physics and biomedical literature (entire batch excluded), sports and gambling SEO pieces (entire batch excluded), listed companies “Xiangshan Co.” and “ESWIN Materials” (off-topic)
GitHub organization checks (XiangShan, DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT, spacemit-robotics, Sipeed, revyos, openhwgroup, Radxa Linkr, 24-hour window) Pushes within window: XiangShan series (XiangShan, XSCache, NEMU, GEM5, difftest), revyos (7 repos), Sophgo (5 repos), SpacemiT (spacemit-com 4 repos, spacemit-robotics 3 repos), Sipeed (3 repos), Espressif (34 repos, mostly generic components and non-RISC-V core targets such as ESP32-S3/ESP32-S31, no version-level activity this period), DAMO XuanTie (2 repos, pushes verified but no new commits on maintenance branches); No pushes: ESWIN Computing, Nuclei, openhwgroup, Radxa Linkr (latest push September 9, outside window)
openRuyi distro official site and repos September release page still does not exist (latest official release 2026.08); repos continue merging spec files, no version-level signal (included in 1.6)
RISC-V International member company website sweep (391 companies) 391 swept, no substantive updates: 225 unchanged, 100 with ordinary homepage content changes (all marketing pages, job postings, and university news; no product, funding, or architecture announcements), 66 failed to fetch (including sites such as ISCAS, Beijing Institute of Open Source Chip, Andes Technology, Tencent; failures are non-blocking)
deepin community (community monthly report, planet.deepin weekly, deepin-ports SIG blog) Valid: RVA23 repo toolchain and K3 adaptation progress, as the technical basis for 2.3; the latest deepin-ports SIG weekly is September 11, with no new weekly within this period’s window

Full Source List