Research window: Past 24 hours (2026-09-15 05:18 ~ 2026-09-16 05:18, Beijing time) Sources: Hacker News, Google News aggregation (multiple Chinese and English queries, via proxy), Phoronix, SiFive official website, Jiemian News, Guandian Web, Guancha, Sina Finance, Securities Times, Jiwei.com, Beijing Business Today, openRuyi official website, RISC-V International member company website inspection (391 companies), and GitHub API (XiangShan, XSCache, NEMU, GEM5, difftest, CORE-V, DAMO XuanTie, Sophgo, SpacemiT, Sipeed, revyos, Radxa Linkr and other organizations’ and key repositories’ push and commit searches)

This Issue’s Index

  • Today’s Highlights: Dual signals of policy and capital for RISC-V industrialization — MIIT and NDRC’s “15th Five-Year Plan” names RISC-V R&D and industrialization; Nuclei launches Beijing Stock Exchange listing counseling (09-15)
  • I. Open Source Community and Software Ecosystem
    • XiangShan: CommonHR and instruction fetch exception fixes merged (09-15)
    • XiangShan simulation chain NEMU: page table reads and MMU identity address cache speedup, visibility check added to matrix memory access (09-15)
    • XiangShan simulation chain GEM5: cbo.zero implemented via O3 store buffer, pending interrupt handling after ROB drain (09-15)
    • CORE-V: CVW fixes illegal mstatus.MPP reset value when U mode is absent (09-15)
    • revyos: K3/K1 kernel config batch merge, LinuxBoot and cross-build CI added (09-15)
    • openRuyi: September release page still nonexistent, latest stable remains 2026.08 (09-15 check)
  • II. Product and Ecosystem Updates
    • SiFive and AMD collaborate to optimize ROCm on RISC-V data center servers (09-15)
    • Aowei Lingxin RV9000 series heterogeneous SoC taped out and lit up, modular configurable architecture completes on-silicon validation (09-15)
    • Shenzhen IoT Industry Association holds RISC-V and OpenHarmony industrial IoT salon (09-15)
    • ECOS team to showcase fully open-source chip at JLC Open Hardware Spark Conference (held 09-19)
  • III. Deep Dive into Domestic Teams
    • Nuclei: World’s first ASIL-D automotive certification, H1 2026 net loss widened 24.9% (09-15)
    • Jiachen Plan student Chen Hao merges one fix each into llama.cpp and LLVM upstream (September)
    • Sophgo: LLM-TPU supports text-only Qwen3.5, sophon-demo fully adapted to BM1684X2 (09-15)
    • SpacemiT: SpaceMiT branch fixes multi-channel ASR decoder thread parameter passing (09-15)
    • Sipeed: wiki adds NanoKVM-Go power-on restart troubleshooting and slogic-agent guide (09-15)
    • DAMO XuanTie: No new pushes in window, cove-dp1-poc etc. already covered previous trading day (09-15 check)
  • IV. Embodied Intelligence and Robotics Special Chapter
    • SpacemiT spacemit-robotics: No new pushes in window, Linglong humanoid and whole-body control pending update (09-15 check)
    • Aowei Lingxin RV9000’s industrial robotics and AI PC applications (09-15)
  • V. Summary and Trend Observations

Today’s Focus: Dual Signals of Policy and Capital for RISC-V Industrialization

Date: 2026-09-15　Sources: Guandian 《Two Ministries: Advance RISC-V Industrialization》, Guancha 《Strengthen the Adoption of Domestic Operating Systems Such as Open Source HarmonyOS, Advance RISC-V R&D and Industrialization》, Sina Finance 《”15th Five-Year Plan” for the Development of the Electronic Information Manufacturing Industry》, Beijing Business Today 《Aiming for a BSE IPO! Nuclei Initiates Listing Guidance》

On September 15, the Ministry of Industry and Information Technology and the National Development and Reform Commission jointly issued the “15th Five-Year Plan” for the Development of the Electronic Information Manufacturing Industry. Article 9 of the plan, “Advance Software-Hardware Synergy and Breakthroughs in Electronic System Equipment,” explicitly states: advance the R&D and industrialization of the fifth-generation reduced instruction set (RISC-V), and support the application of RISC-V chips in fields such as artificial intelligence and embedded systems. The same article also proposes “strengthening open-source openness and collaborative co-construction, enhancing the adoption of domestic operating systems such as open source HarmonyOS, building a full-stack ecosystem of AI software and hardware based on computing, and improving supporting tools for software-hardware collaborative adaptation,” as well as “deepening chip-model collaborative innovation and strengthening the collaborative design and optimization of algorithms and hardware architectures.”

The weight of this statement lies in three points. First, level: this is a five-year industrial plan jointly signed by two ministries—MIIT and the NDRC—rather than a local plan or industry initiative. In early September, Beijing’s “15th Five-Year Plan” for the digital economy had named the RISC-V intelligent computing instruction set and the FlagOS open-source ecosystem; this latest move sets a similar tone at the national ministry level, forming a “central plus local” policy overlay. Second, wording: RISC-V is written into the “software-hardware synergy” item and placed alongside open source HarmonyOS, pointing to a combined path of “open instruction set plus domestic operating system” rather than a single-point chip breakthrough; “supporting application in fields such as artificial intelligence and embedded systems” provides a clear application-driven direction, consistent with the domestic industry consensus that “edge inference is the best entry point for RISC-V.” Third, timing: the plan’s release coincides with upstream software breakthroughs for RISC-V on the data center side (on the same day, SiFive and AMD announced ROCm adaptation, see 2.1) and the launch of capitalization by a leading domestic CPU IP player (Nuclei, see 3.1)—policy, technology, and capital converging in the same week.

Corresponding signal on the capital side: The disclosure around the same time of Nuclei’s Beijing Stock Exchange listing guidance is a direct mapping of “policy tone-setting” onto the capital market. The guidance filing report shows that this Shanghai RISC-V CPU IP company, founded in 2018 by Hu Zhenbo, signed a guidance agreement with China Merchants Securities on September 8, submitted filing materials to the Shanghai Securities Regulatory Bureau on September 9, and completed filing on September 11; the company had previously listed on the NEEQ Innovation Tier on August 28 and plans to submit its BSE issuance and listing application documents within 12 months of listing. If all proceeds smoothly, it will become the first A-share listed company whose main business is RISC-V commercial CPU IP. Detailed financial and equity analysis is in Chapter 3, Section 3.1.

Assessment and boundaries: The policy item itself is “planning language” and does not constitute specific funding or project arrangements; its fulfillment depends on subsequent supporting rules, local uptake, and actual industry investment. This report records it faithfully according to the public planning text and does not engage in excessive extrapolation of implementation expectations. Three observation points warrant continued tracking: whether supporting special funds or first-unit/first-set policies follow, whether a national-level testing and certification system for RISC-V is established, and whether the “open source HarmonyOS plus RISC-V” combination produces large-scale complete-device deployment cases.

I. Open-Source Community and Software Ecosystem

1.1 XiangShan: Two Fixes Merged for CommonHR and Fetch Exceptions

Date: 2026-09-15　Source: OpenXiangShan/XiangShan commit log

The open-source high-performance RISC-V processor XiangShan recorded 2 commits in the window, continuing the prior trading day’s rhythm of “shifting from branch prediction convergence to correctness polishing.” The first is #6557, which fixes incorrect use of s0_commonHR after s2_override in CommonHR (shared history register)—CommonHR is the structure XiangShan uses to share history information in the branch predictor; if the s0 stage still reads stale values after the s2 stage overwrites them, the prediction history becomes inconsistent with the actual execution path, a typical correctness fix for shared state across multiple pipeline stages. The second is #6207, which narrows IFU exception support to only the fb(1) form, i.e., retaining only a single class of exception path at the fetch buffer level—a convergence of exception classification and trigger conditions. Both are small, boundary-type fixes with no feature-level advancement; items already merged in a concentrated batch on the prior trading day (09-14)—the ITTAGE useful counter mask, IFU/FTQ self-modifying code branch training, and vector VMove floating-point boxing—are not repeated in this report.

1.2 XiangShan Simulation Chain NEMU: Page Table Reads and MMU Identity Address Caching Sped Up, Visibility Check Added for Matrix Memory Access

Date: 2026-09-15　Source: OpenXiangShan/NEMU commit log

The XiangShan reference simulator NEMU recorded 5 commits in the window, with the main thrust being performance optimization rather than feature expansion. #1138 streamlines the riscv64 general page table read path, reducing redundant checks on the common path; #1011 caches the “identity-mapped effective address” state for the riscv64 MMU, i.e., skipping translation table walks when the virtual address is known to equal the physical address—both directly target memory access, a simulation hotspot. #1137 adds an “off when inactive” gate to per-basic-block profiling, preventing profiling overhead from contaminating benchmark data; #1210 suppresses configuration warnings on clang-18 and above. Most noteworthy is #1212 (feat(ame)): checking scalar and vector store visibility before matrix loads—AME is XiangShan’s simulation support for matrix extensions, and this fix targets the memory model consistency issue of “whether data previously written by scalar/vector instructions is already visible when the matrix unit reads data,” a correctness-level reinforcement of matrix extension simulation. Overall, NEMU is advancing on both fronts simultaneously: “running fast” (page table/MMU caching, profiling gating) and “simulating accurately” (AME visibility).

1.3 XiangShan Simulation Chain GEM5: cbo.zero Implemented via O3 Store Buffer, Pending Interrupts Handled After ROB Drain

Date: 2026-09-15　Source: OpenXiangShan/GEM5 commit log

The GEM5 simulation model accompanying XiangShan recorded 5 valid commits in the window, concentrated on RISC-V architectural semantics and out-of-order core timing. #1153 makes cbo.zero (the cache block zero instruction, an RVA23-related infrastructure instruction) execute through the out-of-order core’s store buffer—meaning the instruction no longer needs a separate special path and can directly reuse the store pipeline, both simplifying the implementation and giving the zeroing operation ordering semantics consistent with ordinary stores. #1149 handles pending interrupts after ROB (reorder buffer) drain: ROB drain is a critical moment for precise exceptions and interrupt delivery, and interrupts arriving at the instant of drain could previously be missed; this fix closes that window. #1154 improves XiangShan SE (system call emulation) mode support, and #1157 replaces test assertions with supported syntax. This batch of changes shows that XiangShan’s simulation fidelity on GEM5 is moving from “functionally runnable” into the stage of “aligning timing and exception semantics with real hardware.”

1.4 CORE-V: CVW Fixes Illegal mstatus.MPP Reset Value When U Mode Is Absent

Date: 2026-09-15　Source: openhwgroup/cvw commit log

CVW (the Wally teaching and verification processor) in the CORE-V ecosystem submitted #1870 in the window, fixing the issue of “illegal mstatus.MPP reset value when U mode is unsupported.” The MPP field of mstatus records the previous privilege level so that mret can return to the correct level; when the core is configured without user-mode support (M-mode only), an MPP reset value indicating U mode constitutes an illegal state that causes undefined behavior during privilege-level switches and exception returns. This belongs to the same batch of privilege-state boundary cleanup as #1864 (illegal mcounteren access when U mode is absent), already covered on the prior trading day—i.e., the team is systematically sorting out the consistency of “privileged register reset values and access permissions under a reduced configuration (no U mode).” The companion CVA6 repository had no new commits in the window (the most recent being the HLVX execution permission fix on 09-13).

1.5 revyos: Batch Merge of K3/K1 Kernel Configs, LinuxBoot and Cross-Build CI Added

Date: 2026-09-15　Source: revyos/linux commit log

The revyos distribution kernel repository for the SpacemiT platform (K1/K3) merged a batch of 8 commits in the window, with author dates spanning 2026-04-03 to 2026-09-15—a typical backlog batch landing (by merge time). The content is almost entirely kernel configuration options: enabling UFS and DC (display controller) for K3, enabling K1 USB2 for Banana Pi F3, enabling the SENSORS_LM63 temperature sensor, enabling CONFIG_ERRATA_PICOHEART erratum handling, enabling RESET_GPIO, and adding a LinuxBoot configuration and a “cross-compilation plus native compilation” CI flow. On the same day, four repositories in the revyos ecosystem firmware stack (firmware-sg204x, sophgo-edk2, edk2-platforms, edk2) were pushed within the same minute, constituting a synchronized EDK2/UEFI firmware update. The signal is that K3’s display and storage (UFS) paths are being brought up item by item, and the introduction of LinuxBoot and CI indicates that the distribution’s build and boot chain is becoming engineered rather than remaining at the single-board debugging stage.

1.6 openRuyi: September Release Page Still Nonexistent, Latest Official Release Remains 2026.08

Date: 2026-09-15 (verification)　Source: openRuyi news page

Routine source verification of the openRuyi distribution led by the Institute of Software, Chinese Academy of Sciences: https://openruyi.cn/zh-Hans/news/2026-09/release returns 404, and the latest version release in the news list remains openRuyi 2026.08 release, i.e., the September version has not yet been released. There were no new entries on the site in the window; this issue does not include an openRuyi entry, only a progress note.

II. Product and Ecosystem Developments

2.1 SiFive and AMD Collaborate to Optimize ROCm on RISC-V Data Center Servers

Date: 2026-09-15　Source: SiFive Official Press Release, Business Wire Original Release, Yahoo Finance Reprint

RISC-V founding company SiFive and AMD jointly announced that the two parties are collaborating to port and optimize AMD’s open-source software ecosystem ROCm to RISC-V data center server platforms, with a demonstration completed on SiFive’s BigSky data center development platform. The demonstration hardware is the BigSky SF-2U870: 32 P870-D cores running at 2.0 GHz, 256 GB DDR5-5600 memory, 4x PCIe Gen5 x16 (64 lanes total) plus PCIe Gen3 x4, 2x 7.68 TB U.2 NVMe SSDs, 10/25 Gb OCP 3.0 NIC; the platform is now orderable. The live demonstration took place September 15–17 at the AI Infra Summit held at the Santa Clara Convention Center in the United States, at the SiFive booth within the RISC-V International pavilion.

The measured framing from both parties is worth noting. Matt Langman, SiFive’s Senior Vice President of Data Center, said that bringing the ROCm open-source software ecosystem to the BigSky platform “enables hyperscalers and developers to seamlessly run advanced AI workloads on RISC-V,” calling it “yet another key milestone” accelerating RISC-V’s entry into the data center. On AMD’s side, Ramine Roane, Corporate Vice President of AI Software Product Management, characterized it as an “early step“—that is, the significance of the demonstration lies in “letting developers begin exploring” the feasibility of ROCm-based AI acceleration on RISC-V host platforms, rather than claiming production readiness. Both companies said they will continue to evaluate optimizing ROCm on RISC-V servers, with the goal of accelerating processing speed and supporting more acceleration scenarios and larger models.

Why it matters: This is a key node for the RISC-V data center path on the software stack. Previously, the public narrative of RISC-V entering the data center mostly revolved around CPU core performance and IP licensing (SiFive P870-D, Ventana, Tenstorrent, etc.), whereas the real barrier to entry for AI servers lies in the accelerator software ecosystem: if ROCm can run on a RISC-V host, it means “RISC-V CPU plus AMD GPU” can form a compute combination that does not depend on x86. In terms of resonance, the Institute of Software at the Chinese Academy of Sciences had previously publicly completed ROCm adaptation to the RISC-V architecture and claimed an order-of-magnitude improvement in large-model inference performance; this is the first time AMD has officially endorsed this direction as a collaborator. The boundaries are equally clear: a demonstration does not equal productization, and ROCm’s operator coverage, performance maturity, and long-term maintenance commitment on RISC-V all remain to be verified. AMD’s use of “early step” also suggests it should not be overinterpreted as a strategic pivot.

2.2 Aowei Lingxin RV9000 Series Heterogeneous SoC Tapes Out and Lights Up, Modular Configurable Architecture Completes On-Silicon Validation

Date: 2026-09-15　Source: Jiemian News “Aowei Lingxin RV9000 Tapes Out and Lights Up, RISC-V Modular Configurable Heterogeneous Platform Achieves Engineering Deployment”, 36Kr Project Database: Aowei Lingxin

Shenzhen Aowei Lingxin Technology Co., Ltd. (founded in April 2023, focused on RISC-V high-performance processor chips and CPU IP) announced that its self-developed RV9000 series heterogeneous SoC chip has completed tape-out and packaging, the chip powers on and boots normally, core basic module tests passed on the first attempt, and operation meets design expectations. The specific model that lit up this time is the RV9311, marking the completion of on-silicon physical validation of the company’s modular configurable heterogeneous computing architecture. The company said its R&D team has begun full functional debugging, performance validation, SDK and operating system porting and adaptation, while simultaneously advancing reliability baseline testing and Alpha customer sample evaluation.

At the architecture level, the RV9000 adopts a modular configurable many-core heterogeneous design combining RISC-V with DSA (Domain-Specific Architecture), achieving low-latency interconnection between compute cores through a NoC on-chip network; it offers two general-purpose core configurations of 4 cores and 8 cores, with some models additionally integrating 16 SDPA (Software-Defined Processing Accelerator) dedicated processing cores, bringing the heterogeneous compute combination up to 24 cores, and users can also optionally add HNA (Hardware Network Accelerator). The product is positioned for network communications, network security, edge computing, control plane processing, distributed storage, and other fields, targeting hardware such as communications equipment, industrial robots, AI PCs, power equipment, and storage devices, emphasizing systematic adaptation for domestic substitution scenarios. The company’s investors include Shenzhen Capital Group, Guoxin Guozheng Investment, Chuangdongfang Investment, and Leaguer Capital, and it completed a Pre-A round of over RMB 100 million in December 2025.

Why it matters: This item, together with the previous trading day’s Suzhou Ruixin “Gaoguang D35,” forms the second example of “architectural path divergence” among domestic RISC-V chips. Ruixin takes the “RISC-V plus dataflow architecture” route, while Aowei Lingxin takes the “RISC-V plus DSA plus NoC many-core” route; both stack dedicated compute units on top of general-purpose CPUs, and both emphasize networking and industrial scenarios. Aowei Lingxin’s differentiation lies in its building-block approach of “deriving multiple spec models from the same die through configuration”—the combinations of 4 cores, 8 cores, plus 16 SDPA, plus HNA essentially replace the parallel development of multiple chips with software-defined configurability, which shares the same lineage as the SoC generator approach of vendors such as InCore. Boundaries to note: neither the official website nor the reprinted article disclosed specific performance metrics (TOPS, energy efficiency ratio, clock frequency), the degree of SDK openness, or the mass production timeline; “lighting up on the first attempt” remains an R&D milestone rather than a commercial product, and the source article is labeled as an advertising reprint, so this report includes it per the vendor’s account with that noted.

2.3 Shenzhen Internet of Things Industry Association Holds RISC-V and OpenHarmony Industrial IoT Salon

Date: 2026-09-15　Source: Shenzhen News, RFID World

The Shenzhen Internet of Things Industry Association held the “RISC-V plus OpenHarmony Empowering Industrial IoT Innovative Applications Salon” on September 15. Based on public reports, the event focused on applying the combination of RISC-V chips and the open-source HarmonyOS operating system to industrial IoT scenarios, and was an ecosystem matchmaking event led by a local industry association.

Background connection: This salon echoes the statement in the “15th Five-Year Plan for the Development of the Electronic Information Manufacturing Industry” released the same day to “strengthen the adoption of domestic operating systems such as open-source HarmonyOS and advance RISC-V R&D and industrialization”—the policy text places the two side by side, while the local association had already begun organizing corresponding industry matchmaking earlier. Shenzhen’s “Action Plan for Accelerating the High-Quality Development of the AI Server Industry Chain (2026-2028)” issued in August 2026 also explicitly proposed to “support deep adaptation of open-source HarmonyOS, openEuler, and the RISC-V architecture.” This is an event-type item with no product launch or technical achievement disclosure, included to record the momentum of the “RISC-V plus open-source HarmonyOS” combination in the industrial IoT direction.

2.4 ECOS Team to Showcase Fully Open-Source Chip at JLC Open-Source Hardware Spark Conference

Date: 2026-09-19 (event date)　Source: ECOS Team “ECOS Team Heads to the Spark Conference! Fully Open-Source Chip, Booth Waiting for You!”

The ECOS open-source chip team announced that it will participate as an exhibitor in the 4th JLC Open-Source Hardware Spark Conference and Global AI Hardware Innovation Ecosystem Conference, to be held on September 19, 2026, from 09:00 to 17:30, at Hall 6 of the Shenzhen Futian Convention and Exhibition Center, Booth No. 15, showcasing its full-stack open-source achievements. On site it will display the world’s first fully open-source chip based on open-source EDA plus open-source IP plus open-source SoC plus open-source PDK (Zhejiang Chuangxin 55 nm) (successfully lit up in December 2025), along with other chips from the team that have completed lighting-up tests.

Supporting exhibits include: the Starry Sky series development boards (L series L1.2 to L4, C series C1/C2 Pi/C2 Pico and T1 Pico, all designed using JLC EDA with PCB manufacturing and SMT assembly completed); the GamerZero retro gaming handheld based on the fully open-source chip (OLED display, buttons, buzzer, RGB lighting effects, driven via SPI/GPIO/PWM/I2C/QSPI interfaces); and the Little Chip Robot family (Mambo voice robot, a robotic arm based on the LeRobot SO-101 body, and a Mecanum-wheel four-wheeled robot). On the software side, it will showcase ECOS Studio (a local chip design IDE integrating Yosys plus ECC-Tools plus KLayout and an open-source PDK, supporting the full RTL2GDS flow) and the ECOS Factory cloud tape-out platform (supporting three templates: MPW/MPC-Frame/OSOC). Regarding tape-out progress, the ECOS-ICS55-2610 free shuttle call has closed and the project is under review; this round introduces the MPC (Multi Project Chip) mode for the first time, and future tape-out costs are expected to drop to around one hundred yuan.

III. Deep Dive into Domestic Teams

3.1 Nuclei: World’s First ASIL-D Automotive-Grade Certification, H1 2026 Net Loss Widens 24.9%

Date: Disclosed 2026-09-10 (interpretation clustered on 09-15)　Sources: 36Kr, “The Shanghai CPU Company Backed by Xiaomi Launches IPO”, Jiwei, “Nuclei Initiates Beijing Stock Exchange Listing Tutoring”, Sina Finance, “H1 Revenue Up 40%, Net Loss Widens 24.94%”, Phoenix, “Ninety Percent of Revenue from RISC-V IP Licensing”, Beijing Business Today

Nuclei Zhirong Semiconductor Technology (Shanghai) Co., Ltd. (securities abbreviation: Nuclei; securities code: 875127) disclosed on September 10, 2026 its “Announcement on the Filing of Tutoring for Application for Public Offering of Shares and Listing on the Beijing Stock Exchange and Related Progress”: the company signed a Beijing Stock Exchange listing tutoring agreement with China Merchants Securities on September 8, submitted tutoring filing application materials to the Shanghai Securities Regulatory Bureau on September 9, and the Shanghai bureau accepted and completed the filing on September 11, formally launching the Beijing Stock Exchange listing process. The company had already listed on the NEEQ Innovation Tier on August 28, 2026, raising approximately RMB 42 million through a concurrent targeted issuance for a RISC-V chip customization platform R&D project, with subscribers including industrial capital such as the Heilongjiang Zhenxing Advanced Manufacturing Industry Private Equity Fund and SMIC Xicheng (Beijing) Digital Technology Fund.

On equity and governance: the company was founded on September 20, 2018, headquartered in Pudong, Shanghai, with registered capital of RMB 5,093,681, legal representative Hu Zhenbo, and no controlling shareholder. Hu Zhenbo directly holds 14.97% and controls 27.53% of voting rights through two employee shareholding platforms, Xinlai Gongchuang and Xinlai Hechuang, giving him control over voting rights corresponding to 42.50% of shares in total—making him the actual controller (he previously worked at Marvell, Synopsys, and Bitmain). The top ten shareholders include the Hubei Xiaomi Yangtze River Industry Fund (6.12%), Shanghai Junlian Shenghao (5.26%), and VeriSilicon (directly holding 2.99%).

On financials and business: the company’s main business is RISC-V CPU IP and subsystem licensing, chip customization, and solutions, applied in automotive electronics, industrial control, AI and data centers, consumer IoT, and other fields, with more than 300 formally licensed customers and projects in total, covering listed companies and central and state-owned enterprises. Operating revenue for fiscal years 2024 and 2025 was RMB 73.9987 million and RMB 82.9411 million respectively, with net losses attributable to parent of RMB 74.3558 million and RMB 84.5981 million; H1 2026 operating revenue was RMB 36.8745 million (up 41.09% year-on-year), net profit attributable to parent was -RMB 57.3016 million (loss widened approximately 24.9% year-on-year), and R&D investment was RMB 57.3041 million, accounting for as much as 155.40% of operating revenue—R&D investment and share-based payment are the core reasons for the book loss. The company holds the world’s first RISC-V automotive-grade ASIL-D certification, with IP gross margin exceeding 87%, approximately RMB 485 million in cash on the books, and zero debt.

Background: Before initiating this IPO, the company had one acquisition attempt that did not go through. In September 2025, STAR Market-listed VeriSilicon disclosed a plan to acquire, by issuing shares and paying cash, 97.007% of Nuclei’s equity held in aggregate by 31 counterparties including Xinlai Gongchuang, Hu Zhenbo, and Xinlai Hechuang, at an issue price of RMB 106.66 per share; more than three months later, VeriSilicon announced termination of the transaction, citing deviations between the core demands and key matters raised by the target company’s management and counterparties and the market environment, policy requirements, and the interests of all shareholders. Comparable peers are VeriSilicon, ARM, Andes, and SiFive.

Assessment: This is the first case in this publication’s 2026 coverage of a RISC-V CPU IP company entering A-share (Beijing Stock Exchange) listing tutoring—if it proceeds smoothly, Nuclei will become the first A-share listed company with RISC-V commercial CPU IP as its main business. Its industrial significance lies in the fact that RISC-V in China is shifting from an “open-source community narrative” to a “business model that can be priced by the capital markets,” and Nuclei’s revenue structure, dominated by IP licensing (over ninety percent of revenue), is also the link in the domestic RISC-V industry chain closest to ARM’s business model. What warrants a sober view: the company is still in a period of widening losses, with R&D investment exceeding 155% of revenue; penetration of the RISC-V ecosystem from IoT into high-end scenarios such as automotive and AI will take time; and the global CPU IP market remains dominated by ARM (the top four vendors together account for roughly 75% share). From tutoring filing to formal application, multiple stages remain, including compliance rectification, internal control system development, and justification of fundraising projects.

3.2 Jiachen Project Trainee Chen Hao Lands One Fix Each in llama.cpp and LLVM Upstream

Date: 2026-09 (Jiachen Project WeChat account)　Source: [Jiachen Project, “Chen Hao A University Student’s Open-Source Growth in the AI Era”](https://mp.weixin.qq.com/s/7MbqOlZKCYEeM11092v0nQ)

The Jiachen Project published a trainee internship record: Chen Hao, an undergraduate mathematics major at Hefei University of Technology, entered the open-source community through the Jiachen Project’s online internship and, during his summer internship, submitted and had merged one fix each to two upstream projects, llama.cpp and LLVM, becoming a RISC-V ecosystem contributor. On the llama.cpp side, PR #26792: while running quantized model benchmarks on a SpacemiT K3 cloud instance, he found that Q4_K_M output was garbled and speed was abnormal, tracing it to the SpaceMiT backend dispatch table missing a GGML_TYPE_Q5_0 branch (Q4_K_M is a mixed quantization format containing Q5_0 shards internally); after adding the branch, the garbling disappeared and speed recovered; he also documented the practical detail that TCM (tightly coupled memory) crashes require cleanup with spacemit-tcm-smi. On the LLVM side, PR #215724: clangd and clang-tidy repeatedly crashed on a specific file, with a minimal reproduction reduced to 6 lines (an undefined type used as a std::map key with pointer subscript operations), traced to the isPolymorphic matcher not first confirming the type has a definition; the fix added Node.hasDefinition() plus Node.isPolymorphic() and a regression test, and was merged after review revisions.

The student was introduced through a Jiachen Project presentation (the organizer visited his school), completed real-hardware verification using free K3 resources provided by SpacemiT, and his test data has been compiled and published on his personal blog. Related context: the SpacemiT spacemit-com/llama.cpp repository also had commits within the window (see 3.4), indicating sustained maintenance activity on that upstream branch.

3.3 SOPHGO: LLM-TPU Supports Text-Only Qwen3.5, sophon-demo Fully Adapts to BM1684X2

Date: 2026-09-15　Sources: sophgo/LLM-TPU commit log, sophgo/sophon-demo commit log, sophgo/sophon-tools commit log

SOPHGO pushed across three repositories within the window. LLM-TPU commit feat: support LLM-only Qwen3.5 bmodels without vit, i.e., support for text-only Qwen3.5 bmodels without a vision encoder—previous Qwen3.5 deployment relied on the multimodal version with vit, and the new text-only path allows choosing a lighter model file depending on the scenario. sophon-demo commit sample/FunASR_Nano: 全模型 TPU 运行 (SE7-32/SE9-16) + RTF + CER, running all models of the speech recognition sample FunASR_Nano on the TPU and adding two evaluation metrics, real-time factor (RTF) and character error rate (CER); on the same day, another commit sample/Qwen3_5: 适配 BM1684X2(SE13-64) continued the batch work since 09-14 adapting various samples to the new board BM1684X2. sophon-tools migrated in the SE flashing tool (feat(psewriter), by default producing only a Windows version without a built-in image) and fixed failure when writing nested packages from a directory source, with the version bumped to 2.0.6.

3.4 SpacemiT: SpaceMiT Branch Fixes Thread Parameter Propagation in Multi-Channel ASR Decoder

Date: 2026-09-15　Source: spacemit-com/llama.cpp commit log

The llama.cpp branch maintained by SpacemiT committed within the window fix(asr): propagate -t into multi-ASR decoder context (#38)—fixing the issue where the thread count parameter -t was not propagated into the multi-channel ASR decoder context, i.e., in concurrent speech recognition scenarios the decoder still used the default thread configuration rather than the user-specified value, a parameter pass-through class of defect. The repository’s recent mainline has been ASR and media capabilities: on August 24 it integrated an isolated multi-channel ASR service, on August 28 it optimized the continuous batching pipeline, on July 24 it added Qwen3-TTS support to the media backend, and on July 20 it completed the mtmd media refactor. The signal significance is that SpacemiT’s llama.cpp branch has clearly moved beyond “porting an inference backend” toward “on-device multimodal and speech servitization”—the K3 platform simultaneously hosts LLM, VLM (mtmd), TTS, and ASR, forming a complete on-device AI service stack.

3.5 Sipeed: Wiki Adds NanoKVM-Go Power-On Reboot Troubleshooting and slogic-agent Guide

Date: 2026-09-15　Source: sipeed/sipeed_wiki commit log

The Sipeed wiki repository had 3 commits within the window, all documentation-type: adding a “reboots after power-on” troubleshooting entry to the NanoKVM-Go FAQ; merging the slogic-agent story solicitation campaign into a single plugin guide page and nesting the submission entry under that guide (two commits); and one commit switching virtual environment management to uv. The NanoKVM series is a RISC-V-based IP-KVM product line; the addition of its default SSH credentials and USB flashing instructions was covered on 09-14, and this issue continues the ongoing documentation completion for the same product.

3.6 DAMO XuanTie: No New Pushes Within the Window; cove-dp1-poc et al. Already Covered the Previous Trading Day

Date: 2026-09-15 (verification)　Source: XUANTIE-RV organization repositories

A window verification of DAMO XuanTie (XUANTIE-RV, 73 repositories): no repository pushes within 24 hours. The three most recent pushes were cove-dp1-poc (09-14, a proof-of-concept repository for confidential virtual machine extension direction), damo-rv-priv-ATS (09-14, Hypervisor test plan update), and binutils-gdb (09-13), all already covered in the previous trading day’s report and not repeated here. There were no XuanTie-related news-side hits this issue (the gnews “玄铁 when:3d” query results were polluted by wuxia novels and gambling SEO, and were culled wholesale by title semantics).

IV. Embodied Intelligence and Robotics Special Chapter

4.1 SpacemiT spacemit-robotics: No New Pushes Within the Window; Linglong Humanoid and Whole-Body Control Await Updates

Date: 2026-09-15 (verification)　Source: spacemit-robotics organization repositories

A window verification of SpacemiT’s robotics software stack organization spacemit-robotics (78 repositories): no repository pushes within 24 hours. The three most recent pushes were perception (09-14, unified code standards for perception modules), humanoid_linglong (09-14, Linglong humanoid robot), and control_whole_body (09-14, whole-body control), all already covered in the 09-15 report and not repeated here. There are no new robotics-direction entries this issue, and this special chapter is mainly a verification conclusion.

4.2 Aowei Lingxin RV9000’s Industrial Robotics and AI PC Positioning

Date: 2026-09-15　Source: See 2.2

Combined with the RV9000 tape-out bring-up event in 2.2, its officially stated application list explicitly includes industrial robotics and AI PC. From an architectural perspective, RV9000’s combination of “general-purpose cores plus SDPA software-defined acceleration cores plus HNA hardware network accelerator” is significant for robotics scenarios in that: control flow (motion planning, state machines) is handled by RISC-V general-purpose cores, perception and inference operators by programmable acceleration cores, and real-time communication and bus load by the network accelerator, with the three interconnected via NoC—this is precisely the typical architectural approach of current domestic RISC-V chip vendors targeting embodied intelligence (forming a three-route contrast with Suzhou Ruixin’s “dataflow architecture anchored in physical AI” and SpacemiT’s “CPU plus AI plus robotics software stack”). It should be noted that RV9000 has so far only completed tape-out bring-up and basic module testing; the SDK, operator libraries, and real-machine adaptation for robotics scenarios are still in progress, and this report only records its product positioning without making judgments on deployment capability.

V. Summary and Trend Observations

The most notable feature of this period is that RISC-V made progress simultaneously on two non-technical dimensions: policy and capital. The Ministry of Industry and Information Technology and the National Development and Reform Commission’s “15th Five-Year Plan for the Development of the Electronic Information Manufacturing Industry” for the first time included in a national-level five-year industrial plan the statement “advance R&D and industrialization of RISC-V, support the application of RISC-V chips in artificial intelligence, embedded systems, and other fields,” and placed it alongside “strengthen the adoption of domestic operating systems such as OpenHarmony,” laying out a combined path of “open instruction set plus domestic operating system.” Around the same time, Nuclei, China’s earliest commercial RISC-V CPU IP company, completed filing for pre-listing tutoring with the Beijing Stock Exchange; if successful, it would become the first A-share listed company whose main business is commercial RISC-V CPU IP. Policy positioning and capital pricing emerging in the same week marks a landmark moment for RISC-V in China as it moves from ecosystem narrative to industrial valuation.

On the technical side, this period was mainly about “patching and fixing,” but where the patches landed is worth noting. XiangShan’s two commits were both boundary fixes for pipeline shared state and exception classification; of NEMU’s five commits, four were performance optimizations (page table reads, MMU identity address caching, profiling gating) and one was a memory visibility correctness check for matrix extensions; GEM5 routed cbo.zero through the out-of-order core’s store buffer and closed an interrupt delivery window at the moment the ROB drains. All three repositories point to the same thing: the XiangShan ecosystem’s simulation and reference models are moving from “functionally working” into the stage of aligning timing and memory models with real hardware—work that typically happens before tape-out or performance benchmarking.

On the international side, the key signal is loosening in the data center software stack. SiFive and AMD announced optimization of ROCm on RISC-V servers. Although AMD explicitly called it an “early step,” this is the first time AMD has officially endorsed a RISC-V host platform as a partner. If ROCm’s operator coverage and maintenance commitment on RISC-V can be sustained, “RISC-V CPU plus AMD GPU” will become an AI server combination path independent of x86, with strategic implications greater than any single technical advance.

On the domestic chip side, divergence in architecture routes is now a fact. Following Suzhou Ruixin’s “RISC-V plus dataflow architecture,” this period saw Aowei Lingxin’s RV9000 complete tape-out and bring-up in the form of “RISC-V plus DSA plus NoC many-core, with multiple SKUs derived from configurations on the same die.” Both companies are layering dedicated compute units on top of general-purpose CPUs, and both have chosen networking and industrial (including robotics) as their primary scenarios, indicating that domestic RISC-V vendors are no longer attempting to compete head-on with ARM/x86 on general-purpose compute, but rather entering niche markets through “configurable heterogeneity.” Whether this route holds depends on the degree of SDK openness and real customer cases; neither company disclosed quantitative performance or mass-production timelines this period, so continued tracking is needed.

Three observation points to track: First, whether supporting rules and dedicated funding for the RISC-V item in the “15th Five-Year Plan” follow, and whether the “OpenHarmony plus RISC-V” combination sees large-scale complete-device deployment (the Shenzhen Internet of Things Industry Association’s 09-15 salon and Shenzhen’s August AI server action plan are already advancing at the local level); second, when ROCm’s operator coverage and performance data on RISC-V will be made public, and whether the two tracks—Chinese Academy of Sciences Institute of Software and SiFive—converge; third, the pace of Nuclei’s progression from tutoring filing to formal application, and its path to narrowing losses—this will be an important sample for judging whether the domestic RISC-V IP business model is viable.

Appendix

Source Verification Table

Source Verification Result
fetch_news.py 24-hour candidates (50 items) 1 valid: SiFive and AMD ROCm collaboration (HN 09-15, included in 2.1); the rest were personal learning/course-type RISC-V core repos (20-plus low-star repos such as guru753, bipul144, HaibaraTaffy), unrelated general project pushes (platformio-core, simdutf, DietPi, renode), and finance and cryptocurrency noise (TSMC revenue, TapeOut token, Nordic Bluetooth SoC, SCMP five-year plan), all removed
gnews English queries (“SiFive AMD ROCm”, RISC-V when:2d, SiFive when:3d, Andes Technology OR 晶心 when:7d) Valid: SiFive/AMD ROCm collaboration (included in 2.1), English coverage of Nuclei IPO (digitimes and finance.biggo, included in 3.1); background: Infineon automotive RISC-V (09-13 Hot Chips, already reported around 09-14, outside window); noise: Andes matched Chilean glaciers and Polish memory modules (removed), CryptoRank token page (removed)
gnews Chinese queries (XiangShan processor, XuanTie, SpacemiT, Sophgo, ESWIN, Nuclei, RISC-V processor, RISC-V conference, 睿擎 when:2d/3d/7d) Valid: Aowei Lingxin RV9000 tape-out and bring-up (Jiemian News, included in 2.2), RISC-V named in the two ministries’ 15th Five-Year Plan (included in today’s highlights), Shenzhen RISC-V plus OpenHarmony salon (included in 2.3), Nuclei IPO series (included in 3.1); removed: CPython Tier 3 (Chinese reprint on 09-15 of the 08-24 announcement, already reported on 08-25/09-01, removed per deduplication rules), Andes Technology Silicon Valley event (09-11 official site, already reported 09-14, removed), XiangShan Co. (listed company, not the XiangShan processor), ESWIN Materials (688783 silicon wafer business, not relevant to this topic), generic “computing power” topic articles matched by the Sophgo query (numerous), gambling and sports SEO spam articles (entire batch removed)
GitHub org check (check_orgs.py, 24h) Pushes within window: sophgo (3 repos), espressif (34 repos, ESP32-C series are RISC-V cores, no version-level developments this issue), spacemit-com (llama.cpp), sipeed (5 repos), revyos (5 repos), openhwgroup (cva6 and cvw), key XiangShan-series repos (XiangShan, XSCache, NEMU, GEM5, difftest). No pushes: DAMO XuanTie XUANTIE-RV, ESWIN eswincomputing, Nuclei Nuclei-Software, spacemit-robotics, radxa-linkr (latest push 09-09, outside window)
RISC-V member company website inspection (check_members.py, 391 companies) 256 unchanged, 68 changed, 67 fetch failures (including sites related to ISCAS, Beijing Institute of Open Source Chip, Andes Technology, Alibaba T-Head, etc.; failures mostly due to anti-scraping or overly short content, non-blocking). All 68 changes were verified item by item to be marketing content, section, or navigation updates, with no substantive developments; among them, the InCore Semiconductors homepage headline “SoC Generator platform completes silicon validation” was old news from June to July 2025 re-placed on the homepage, not news within the window, so it was not included. No substantive updates on the member side this issue
openRuyi official website check September release page 404, latest official version remains 2026.08, no new entries within window
Vendor English supplementary queries (SiFive when:3d, etc.) SiFive official site published the AMD ROCm collaboration press release on 09-15 (included in 2.1); the previous standalone release in the SiFive newsroom was 2026-05-12 (P570 Gen 3), nothing else within window

Complete Source List