Research window: Past 24 hours (2026-09-14 08:18 ~ 2026-09-15 08:18, Beijing time) Sources: Hacker News, Google News aggregation, CNX Software, Suzhou Industrial Park Administrative Committee official website, Geek Park, Sina Finance, 36Kr, Phoenix News, Edge AI and Vision Alliance, Andes Technology official website, openRuyi official website, and GitHub API (XiangShan, XSCache, NEMU, GEM5, difftest, LLVM, CORE-V, DAMO XuanTie, Sophgo, SpacemiT, Sipeed and other organization repo pushes and commit searches) (see appendix source verification table for details)

Index

  • Today’s Highlights: Suzhou Ruixin “Gaoguang D35” RISC-V dataflow physical AI chip mass production officially confirmed by the park—128 GB VRAM anchors edge-side physical AI, “Guangrong Community” to be launched (09-14)
  • I. Open Source Community and Software Ecosystem
    • XiangShan Kunminghu: Branch prediction and vector pipeline fixes merged in batch, IFU/FTQ supplement self-modifying code branch training (09-14)
    • XSCache: ZhuJiang (L3) submodule batch merged, HN performance counters renamed by module path (09-14)
    • XiangShan simulation and verification chain: NEMU streamlines single-step boundary, GEM5 calibrates SBUFFER, difftest switches to slim container (09-14)
    • LLVM/Clang RISC-V backend: f16 conversion decomposition under RV32, new packed widening add accumulate builtin (09-14)
    • CORE-V ecosystem: Wally fixes PWM self-test and IFU triple defects, CVFPU adds division/sqrt NaN boxing (09-14)
    • openRuyi: September release page does not exist, latest stable version remains 2026.08 (09-14 verification)
  • II. Product and Ecosystem Updates
    • JetKVM Mini: $39 IP-KVM with ESP32-P4X dual-core RISC-V, built-in H.264 hardware encoding, on sale October 26 (09-14)
    • Andes Technology to hold “Maximize RISC-V Performance with Custom Design” in Silicon Valley on October 7 (09-11 official website, 09-14 Chinese reprint)
  • III. Domestic Team Updates and Deep Dives
    • DAMO XuanTie: New cove-dp1-poc repo points to confidential VM extension direction, priv-ATS updates Hypervisor test plan (09-14)
    • Sophgo: sophon-demo adapts to BM1684X2 (SE13-64) new board, Qwen3.5 adapts to new toolchain bmodel (09-14)
    • SpacemiT: Media processing platform fixes RTSP client disconnection, ROS documentation repo updated same day (09-14)
    • Sipeed: wiki adds NanoKVM-Go default SSH credentials and NanoKVM-Cube flashing instructions (09-14)
    • Nuclei IPO follow-up: H1 net loss widened 24.94%, gross margin 87.6%, licensing customers exceed 300 (09-10 disclosure, 09-14 interpretation)
  • IV. Embodied Intelligence and Robotics Special Section
    • SpacemiT spacemit-robotics four repos advance together: Perception unified code standards, Linglong humanoid adjusts support state and heartbeat strategy (09-14)
    • Convergence of dataflow architecture and physical AI: Ruixin Gaoguang D35’s embodied intelligence landing point (09-14)
  • V. Summary and Trend Observations

Today’s Highlight: Suzhou Ruixin “Gaoguang D35” RISC-V Dataflow Physical AI Chip Mass Production Officially Confirmed by the Park

Date: 2026-09-14 (vendor mass-production launch in early September)　Sources: Suzhou Industrial Park Administrative Committee official website “RISC-V Dataflow Physical AI Chip Mass Production!”, Geek Park “World’s First RISC-V Dataflow Physical AI Chip ‘Gaoguang D35’ Mass Produced”, Sina Finance “Crossing Architecture Cycles: Ruixin Gaoguang D35 and the Edge Breakthrough of Dataflow”

The Suzhou Industrial Park Administrative Committee official website published a real-time update on 09-14 at 14:25, confirming that the “Gaoguang D35” dataflow AI chip independently developed by Suzhou Ruixin Integrated Circuit Technology Co., Ltd. has officially entered mass production, calling it a “world-leading RISC-V instruction set-based dataflow architecture physical AI chip,” marking the transition of dataflow computing—an architectural approach proposed more than 60 years ago—from academic research into large-scale commercialization. The vendor’s three “leading-level” positioning claims are: the first dataflow architecture AI chip to achieve commercial mass production; a dual-route solution deeply integrating the open RISC-V instruction set with a dataflow computing architecture; and a product positioning explicitly anchored to “physical AI” rather than cloud-based large-model compute. A key hardware parameter disclosed is 128 GB of large VRAM, used to support local deployment of larger-scale models at the edge, emphasizing that data does not leave the device and response is faster. On the corporate side, Ruixin was founded in August 2020, headquartered in Suzhou Industrial Park (Dushu Lake Science and Education Innovation District), with a core team from the Institute of Computing Technology, Chinese Academy of Sciences, the Institute of Automation, Chinese Academy of Sciences, IBM, Intel, and other institutions; R&D personnel account for over 70%, master’s and doctoral degree holders reach 50%, more than 100 academic papers have been published, and related achievements received a best paper nomination at ISCA 2026, a top international conference on computer architecture; other reports state that the company’s chief scientist is Sun Ninghui, an academician of the Chinese Academy of Engineering. The company has completed five rounds of financing.

On the product deployment side, the official announcement and vendor materials jointly delineate four categories of scenarios: industry intelligent computing (AI PC acceleration, video compression and analysis, industrial intelligent control), embodied intelligence (integrated perception-decision-control scenarios such as robots and unmanned vehicle domain controllers), cockpit-driving integration (fusion of intelligent cockpit and driving domain control), and communications (5G small cells, millimeter wave, AI RAN). On the ecosystem side, Ruixin announced that it will soon launch the “Guangrong Community,” positioned as a RISC-V developer community for dataflow architecture, providing a documentation center, SDK toolchain, model library, online training, and technical forums, and establishing the “Ruixin Guangrong Fund” to support ecosystem innovation. On technical justification, the vendor uses energy efficiency as its core selling point, claiming that the fully dataflow architecture achieves several times the energy efficiency of comparable competitors, citing the reasons of eliminating instruction scheduling overhead, data flowing directly between compute units rather than repeatedly reading and writing memory, and no latency uncertainty from branch misprediction or cache misses.

Why it matters: This is the first mass-production event for dataflow architecture recorded by this publication in September, and it was not previously covered by this daily series (confirmed via full-database search). Its significance lies in three points: first, the dataflow route has long remained at the stage of papers and small-batch validation; if a vendor claims to have entered mass-production delivery, it means a commercialization template for this route has emerged in China; second, it is a rare combination of “RISC-V plus non-von-Neumann architecture,” contrasting with the mainstream domestic route of “RISC-V plus vector/matrix acceleration,” offering another compute paradigm for edge-side physical AI; third, embodied intelligence is listed as one of its four deployment scenarios, forming an upstream-downstream echo with the robot software stack developments in Chapter 4 of this issue. Boundaries to note: this item’s mass-production claim, energy-efficiency multiples, and statements such as “self-developed RISC-V CPU core received Intel’s only global procurement recognition” all come from vendor and media materials, with no third-party independent testing or customer mass-production case yet to corroborate them; this report records and annotates them according to the vendor’s account, and follow-up should track the degree of SDK openness, the actual status of community launch, and real shipment scale.

I. Open-Source Community and Software Ecosystem

1.1 XiangShan Kunminghu: Branch Prediction and Vector Path Fixes Merged in Bulk, IFU/FTQ Add Self-Modifying Code Branch Training

Date: 2026-09-14　Source: OpenXiangShan/XiangShan commit log

The open-source high-performance RISC-V processor XiangShan (Kunminghu V3 branch) recorded 8 commits in the window, continuing the rhythm of “shifting to correctness polishing after new-feature convergence,” with focus concentrated on branch prediction and the fetch side. On branch prediction, zhou tao submitted #6484 at 22:42 on 09-14, adding “direct-jump branch training on misprediction” for the IFU and FTQ, specifically handling mispredictions caused by self-modifying code—a scenario common in dynamically generated code, JIT, and loader self-rewriting, and a typical source of divergence between simulation and real execution; Muzi submitted #6569 at 22:41, fixing the logic that derives the useful counter mask in the ITTAGE predictor from entry fields, and updated the performance checkpoint the same day (#6568); Zhihao Xu submitted #6461 at 22:50, applying enable fixes and debug-related fixes to Bpu and cleaning up code. On fetch and exceptions, lengard2019 submitted #6428 at 14:42, fixing exception PC propagation in the IFU when exceptions and uncacheable accesses trigger simultaneously—a privileged-state boundary correctness fix; Zhihao Xu submitted #6553 the same day, cleaning up the deprecated 0604 legacy performance test baseline. On the vector path, Xuan Hu made two consecutive commits at 11:02 (#6565, #6564), moving the timing of vector source operand reversal to after register read, and adding floating-point boxing to VMove results to prevent narrow-width floating-point values from losing NaN-box semantics during register merging. Overall, nearly all commits that day were “correctness and boundary condition” fixes, with no new-feature-level advances.

1.2 XSCache: ZhuJiang (L3) Submodule Batch Merged, HN Performance Counters Renamed by Module Path

Date: 2026-09-14　Source: OpenXiangShan/XSCache commit log

XSCache, the open-source L2 (RN) and LLC (HN) cache repository accompanying XiangShan, landed 18 commits at once in the window, but the commit timestamps are concentrated at 09-14 17:48 (Beijing time), while author dates span 2026-06-10 to 09-10—a typical batch-merge wrap-up (author and commit dates differ; this report counts by merge time). There are three main threads: first, concentrated landing of ZhuJiang (XiangShan L3 cache direction submodule) work, including parameterizing cfgAxiDataBits, adapting ZhuJiang to the gsim simulation environment, fixing resetgen and reset synchronization, fixing FIRRTL build compatibility, enabling stash refill tracking, and adding a new TestTopZhuJiang test top level (supporting CoupledL2 plus ZhuJiang combinations, minimizing DongJiang configuration to accelerate simulation, and initializing ChiselDB); second, performance counter capability, with zhengzhongqiang submitting feat(perf): name HN collectors by module path, changing HN (Home Node) performance counters from anonymous numbering to naming by module path, facilitating joint counter collection with the XiangShan top level, and adding in the same batch the ability to “collect ZhuJiang counters in coordination with XiangShan”; third, several test and adaptation fixes (disabling DataCheck and Poison in the ZhuJiang test top level, preserving the DCT home node ID). The value of this item lies in revealing that XiangShan’s memory system is evolving toward a “CoupledL2 plus independent L3 (ZhuJiang)” configuration, with the accompanying simulation, reset, build, and performance collection chains now filled in synchronously—a signal that the L3 cache has entered a verifiable state.

1.3 XiangShan Simulation and Verification Chain: NEMU Trims Single-Step Boundary, GEM5 Calibrates SBUFFER, difftest Switches to slim Container

Date: 2026-09-14　Source: OpenXiangShan/NEMU commit log, OpenXiangShan/GEM5 commit log, OpenXiangShan/difftest commit log

The XiangShan verification toolchain saw a group of changes in the window aimed at “performance and efficiency.” NEMU (the XiangShan reference model, an ultra-high-speed RISC-V ISA simulator) received two consecutive commits from Kamimiao at 10:42: perf(difftest): lazily prepare CSR shadow for REF (lazily preparing the CSR shadow copy for the reference model to reduce per-step overhead) and perf(share): trim single-step execution boundary (trimming the single-step execution boundary), both directly targeting the fixed per-step cost of differential testing (difftest)—simulation throughput optimizations. The GEM5 XiangShan branch received a commit from ZHEN HAO at 19:23, cpu-o3: Calibrated SBUFFER behaviour (calibrating Store Buffer behavior in the out-of-order pipeline to better match real hardware). The difftest framework received #965 from Kunlin You at 16:49, switching the CI container from the full image to the slim image and removing the GSIM installation step, reducing the size and preparation time of the continuous integration environment. Viewed together: XiangShan’s verification infrastructure is simultaneously doing two things—”running faster (NEMU/GEM5)” and “starting lighter (CI container)”—routine optimization ahead of large-scale regression testing.

1.4 LLVM/Clang RISC-V Backend: f16 Conversion Decomposed on RV32, New packed widening add accumulate Intrinsic

Date: 2026-09-14　Source: OpenXiangShan/llvm-project commit log

The XiangShan-maintained LLVM branch advanced 17 commits in the window, two of which are RISC-V target-related: Kane Wang submitted [RISCV] Lower f16 to i64 fp_to_[su]int via i32 on RV32 (#222829) at 15:42, decomposing half-precision floating-point to 64-bit integer conversion on 32-bit RISC-V into a two-step path via i32—a code generation legalization fix for the RV32 target; Chen Zi’ang submitted [Clang][RISCV] Add packed widening add accumulate intrinsics (#221622) at 15:05, adding “packed widening add accumulate” intrinsics for the RISC-V vector extension—such intrinsics map directly to vector dot-product/matrix multiply-accumulate scenarios, common primitives in AI inference and signal processing kernels. The remaining commits are upstream general changes (GlobalOpt assertion fixes, allocator alignment, ORC runtime, libc math functions, LoongArch/SPARC tests, etc.). Combined with XiangShan’s multiple vector-path fixes this period, it is clear that XiangShan’s software side (compiler and reference model) and hardware side (vector execution) advanced in sync within the same week.

1.5 CORE-V Ecosystem: Wally Fixes PWM Self-Test and Three IFU Defects, CVFPU Adds NaN Boxing for Division and Square Root

Date: 2026-09-14　Source: openhwgroup/cvw commit log, openhwgroup/cvfpu commit log, openhwgroup/uap commit log

The OpenHW Group’s open-source core ecosystem advanced on multiple fronts in the window. CORE-V Wally (cvw, a configurable RISC-V processor for teaching) received #1830 from David Harris at 09-15 03:56, fixing the PWM (pulse-width modulation) peripheral’s pending bit, counter reset, and pwms register writes, and adding a complete self-checking PWM test; the same day, IFU (instruction fetch unit) defects were fixed in a batch, with Rose Thompson merging #1855 (satp-related), #1862 (JALR least-significant-bit handling), #1861 (flushm), and #1860 (bus fault), all four being fetch-path correctness issues; Syed-Moeed-Ali submitted #1864 at 13:01, fixing illegal access to mcounteren when U-mode is unsupported. CVFPU (a parameterized floating-point unit supporting standard RISC-V floating-point formats) received merge #185 from Ihsane Tahir at 16:32, fixing NaN boxing in the division and square-root paths. UAP (Unified RISC-V Access Platform) received #168 from sergialcaide at 18:31, adding BSC IP card support. Overall, the CORE-V family’s changes in this window are concentrated on peripheral self-test and fetch/privileged-state correctness, consistent with XiangShan’s “correctness polishing” orientation in the same period, reflecting that the open-source core community is broadly entering the deep waters of functional verification.

1.6 openRuyi: No September Release Page Exists, Latest Official Version Still 2026.08

Date: Checked 2026-09-14　Source: openRuyi news and release list

Per routine checking of whether the openRuyi distribution (the RISC-V-native distribution led by the Institute of Software, Chinese Academy of Sciences) has released a new version: its news and release list currently shows the latest official version still as openRuyi 2026.08 (released 2026-08-27, focused on security fixes, advancing RVA23 integration, expanding cloud-native and accelerated computing capabilities, and updating the kernel, toolchain, scientific computing stack, and KDE desktop); the September release page (/zh-Hans/news/2026-09/release) returns 404, meaning the 2026.09 version has not yet been released. Based on the monthly release cadence, the September version is expected to be released in the latter half of this month, and this publication will continue to track it. There was no other news-level activity for this distribution in the window.

II. Product and Ecosystem Updates

2.1 JetKVM Mini: A $39 IP-KVM with Dual-Core RISC-V ESP32-P4X, Built-In H.264 Hardware Encoding, on Sale October 26

Date: 2026-09-14　Source: CNX Software, JetKVM Official Blog “Introducing JetKVM Mini”, Product Page

JetKVM has released JetKVM Mini, a compact, low-cost version of its IP-KVM. The product page confirms its main controller is the ESP32-P4X (dual-core RISC-V, 400 MHz), paired with 32 MB PSRAM and 16 MB flash, and featuring a built-in hardware H.264 encoder—video is captured and encoded on-chip, then streamed to the browser via WebRTC, supporting up to 1080p30 or 720p60; with JetKVM OS Services installed on the host side (Windows/macOS/Linux), it supports up to 4K capture, shared clipboard, guest terminal, and file transfer. The product comes in two versions: the wired JetKVM Mini (RJ45 100 Mbps Ethernet) at $39, and the wireless JetKVM Mini W at $42 (three-packs drop to $33 and $36 per unit); the Mini W additionally carries an ESP32-C5 (also a RISC-V core, single-core 32-bit RISC-V up to 240 MHz) providing dual-band Wi-Fi 6, Bluetooth LE provisioning, and 802.15.4 (Zigbee/Thread). The form factor is 42 × 42 × 23 mm, 5 V 500 mA, with a 240 × 240 IPS status screen, and supports TF card virtual media, JetKVM Cloud remote access, Wake-on-LAN, MQTT and Home Assistant, OIDC login, and OTA with automatic rollback. The vendor states that the firmware was rewritten for the ESP32-P4X and open-sourced from day one, reusing the same web interface and cloud protocol. The product goes on sale through authorized channels on October 26, 2026.

Observation: This marks another productization milestone for the ESP32-P4 series (RISC-V application-class MCU) in the “remote out-of-band management” niche, sharing the same lineage as “ESP32-P4 runs Tomb Raider” covered in our 09-14 issue—the same dual-core 400 MHz RISC-V chip demonstrates the boundaries of graphics rendering capability at one end, while at the other it underpins a $39 commercial IP-KVM with built-in H.264 hardware encoding, showing that both the “capability ceiling” and the “cost floor” of RISC-V application-class MCUs are being pushed outward simultaneously. It is also worth noting that this product uses two RISC-V chips—the ESP32-P4X and the ESP32-C5 (a Wi-Fi 6 connectivity chip)—making it another example of domestic RISC-V wireless connectivity chips entering overseas open-source hardware products.

2.2 Andes Technology to Host “Maximize RISC-V Performance with Custom Design” in Silicon Valley on October 7

Date: Published on official website 2026-09-11, reposted by Chinese media 2026-09-14　Source: Edge AI and Vision Alliance, Event Registration Page

Andes Technology (TWSE: 6533), a founding premier member of the RISC-V International Foundation and a major CPU IP vendor, has announced it will host an in-person event titled “Maximize RISC-V Performance with Custom Design” on October 7, 2026, from 10:00 to 14:00 (Pacific Time) in Milpitas, California, USA. The theme is RISC-V performance optimization and improving project efficiency through custom design. The agenda covers four items: RISC-V market trends and ecosystem collaboration, Andes processor IP product lines and solutions, customer success stories, and “Accelerating RISC-V with Andes Custom Extensions.” Speakers include Emerson Hsiao, Darren Jones, Mia Chang, and Trevor Cooper, with a format featuring technical talks, hands-on practice, and community networking. This item was published on the official website on 09-11 and reposted by Chinese media within the window, so it is included with the original publication date noted. Observation: Andes has maintained a coherent cadence over the past two months—on 09-02 it announced bringing the agentic AI platform ChipAgents into its custom processor design workflow (cutting design time by roughly 30% and compressing the verification cycle to about three weeks, covered in our 09-03 issue), and now it is promoting “Custom Extensions” in Silicon Valley, a high-value capability directly tied to its IP business model. Advancing AI-assisted design and custom extension services in parallel reflects that the competitive focus of IP vendors is shifting from “core performance metrics” to “end-to-end delivery efficiency from design to verification.”

III. Domestic Team Updates and Deep Dives

3.1 DAMO XuanTie: New cove-dp1-poc Repo Points to Confidential VM Extension Direction, priv-ATS Updates Hypervisor Test Plan

Date: 2026-09-14　Source: XUANTIE-RV/cove-dp1-poc, XUANTIE-RV/damo-rv-priv-ats commit history, XUANTIE-RV organization repository list

DAMO XuanTie (XUANTIE-RV, 72 public repositories) showed two signals within the window. First, a new public repository cove-dp1-poc (created 2026-09-14 10:59 Beijing time, one push on the day of creation, currently an empty repository with no description and no language annotation). Judging from the naming, CoVE corresponds to RISC-V’s Confidential VM Extension (used to build trusted execution environments and confidential computing on RISC-V, sharing the same lineage as the AP-TEE specification family), and dp1 may refer to a particular data plane version (data plane 1 or DP-1) implementation; the repository was public from the moment of creation, pointing to ongoing proof-of-concept work in the confidential computing direction. Combined with the organization’s existing damo-rv-priv-ats (RISC-V privileged architecture test suite) and damo-rv-ats, this indicates XuanTie has a sustained line of investment in specifications and testing around “privileged state/security features.” Second, damo-rv-priv-ats received commit #30 from James Shi at 09-14 09:56, Update test plan for Hypervisor test suites, updating the test plan for the Hypervisor-mode test suite. The aforementioned 09-08 issue of this newsletter covered the repository’s addition of Hypervisor_Za* atomic instruction tests; this issue is the accompanying test-plan consolidation, a routine progression of “extension definition—test reinforcement.”

Note: cove-dp1-poc is an empty repository, and its specific technical approach has no public content yet; this item is recorded only as a directional signal, without technical conclusions. There were no new items from XuanTie-side news channels within the window (Chinese “XuanTie/DAMO” query results were entirely gambling-related SEO articles, which were removed in bulk based on title semantics).

3.2 SOPHGO: sophon-demo Adapts to New BM1684X2 (SE13-64) Board, Qwen3.5 Adapted to New Toolchain bmodel

Date: 2026-09-14 (author dates 09-09 and 09-11)　Source: sophgo/sophon-demo commit history

SOPHGO’s example repository sophon-demo merged two commits within the window, both with clear product-adaptation implications. First, liheng.fang committed at 15:15 (author date 09-11) sample: 适配各 sample 到 BM1684X2(SE13-64), uniformly adapting the various samples to the BM1684X2 (SE13-64) hardware target. BM1684X is SOPHGO’s main TPU chip for edge and server inference (the SG2044 server platform also ships with this series of accelerator cards); BM1684X2 appears from its naming to be its successor or a dual-chip version, and SE13-64 is likely a specific board/module codename. This is a signal that a new hardware platform has entered the software adaptation phase, typically occurring in the preparation period before a new product launch. Second, junjie.liu committed at 11:37 (author date 09-09) fix(Qwen3_5): 适配新工具链 bmodel（history 多轮死循环 + FA block 移除 attention_mask）, adapting the Qwen3.5 large-model example to bmodel model files generated by the new toolchain, and fixing an infinite loop caused by multi-turn conversation history as well as behavioral differences after the FlashAttention block removed attention_mask. Taken together: SOPHGO is advancing adaptation simultaneously on two fronts—”new hardware targets” and “next-generation large-model examples”—consistent with its product positioning for RISC-V servers and edge inference.

3.3 SpacemiT: Media Processing Platform Fixes RTSP Client Disconnects, ROS Documentation Repo Updated Same Day

Date: 2026-09-14　Source: spacemit-com/mpp commit history, spacemit-com/docs-ros

SpacemiT had two repository updates within the window. The media processing platform mpp (Media Process Platform) received a commit from yanyongxian at 09:14, fix(mux): survive RTSP client disconnects, fixing issues caused by RTSP client disconnections in the muxer—RTSP is the mainstream protocol for IP cameras and video streaming scenarios, and this fix points to polishing around video codec and streaming service stability, consistent with its K-series chips’ positioning for edge vision and robot perception. On the same day, docs-ros (the ROS documentation repository) showed a push signal, but no retrievable new commits appeared on the default branch within the window (possibly a non-default branch or tag operation), so it is recorded only for reference. Combined with the “vision model library adds RF-DETR, SigLIP2 switching to a self-developed execution backend” covered in the 09-14 issue of this newsletter, SpacemiT’s edge vision and robotics companion software continues to densify, though the intensity within this window is noticeably lower than in the previous window.

3.4 Sipeed: Wiki Adds NanoKVM-Go Default SSH Credentials and NanoKVM-Cube Flashing Instructions

Date: 2026-09-14　Source: sipeed/sipeed_wiki commit history

Sipeed’s official wiki merged 4 documentation commits within the window, all centered on the NanoKVM product line: liangziyue committed twice at 17:53, correcting the default SSH credentials and password documentation for the NanoKVM-Go network guide and changing internal links to title anchors (improving documentation maintainability); kingo0807 at 14:45 removed a duplicate page title in the NanoKVM-Go network guide; liangziyue at 14:51 clarified how to press the BOOT button when flashing NanoKVM-Cube via USB. Sipeed is one of the most active domestic teams in RISC-V open-source hardware and companion firmware iteration, and its recent high-frequency commits center on documentation and usability polishing for the IP-KVM (NanoKVM series) product line rather than new feature development—typically a signal that a product is moving from “open-source project” to a “deliverable, self-serviceable operations” stage, forming a coherent rhythm with the “NanoKVM-Pro adds web display policy control, wiki adds two-factor authentication guide” covered in the 09-14 issue of this newsletter.

3.5 Nuclei IPO Follow-up: H1 Net Loss Widens 24.94%, Gross Margin 87.6%, Over 300 Licensed Customers

Date: Disclosed 2026-09-10, media interpretation 2026-09-14　Source: Sina Finance (Tongbi Finance) “Nuclei Technology Initiates Beijing Stock Exchange Listing Guidance Filing”, Phoenix Finance “Semiconductor Design Firm Nuclei Technology Initiates IPO Guidance, Ninety Percent of Revenue from RISC-V IP Licensing”, East Money (Beijing Business Today)

The Beijing Stock Exchange listing guidance event for Nuclei Technology (Nuclei Zhirong Semiconductor Technology (Shanghai) Co., Ltd., securities code 875127) has been covered continuously in the 09-10 to 09-13 issues of this newsletter; this issue consolidates the financial and business details supplemented by Chinese media within the window. Key figures under the disclosed basis: H1 2026 revenue of RMB 36.8745 million (up 41.09% year-on-year), net profit attributable to parent of RMB -57.3016 million (prior-year period -45.8629 million, net loss widening about 24.94% year-on-year), net profit attributable to parent after non-recurring items of RMB -61.6052 million; 2024 and 2025 revenue of RMB 73.9987 million and RMB 82.9411 million respectively, with net profit attributable to parent of RMB -74.3558 million and RMB -84.5981 million respectively; comprehensive gross margins for the three periods (2024, 2025, 2026H1) of 87.68%, 82.15%, and 87.59% respectively, remaining high, consistent with the high-margin characteristics of pure CPU IP licensing. R&D investment as a share of operating revenue was 129.55%, 119.96%, and 155.40% respectively (H1 2026 R&D investment of RMB 57.3041 million), with multiple rounds of equity incentives bringing large share-based payments; excluding the impact of share-based payments, the net loss scale shows a trend of narrowing period by period (from RMB -17.2273 million in 2023 narrowing to RMB -9.5863 million in 2025). On the business side, the company was founded in 2018, has over 300 licensed customers, covering mainstream domestic chip design, communications, and consumer electronics companies such as GigaDevice, VeriSilicon, Bestechnic, Amlogic, and Motorcomm, with the top five customers accounting for about 28% of revenue (28.58% in 2025). On the capital path, the company was listed on the NEEQ Innovation Tier on 2026-08-28, and simultaneously raised about RMB 42 million through a targeted issuance for R&D of a RISC-V chip customization platform, with subscribers including industrial capital funds; according to the plan, it intends to submit issuance and listing application documents to the Beijing Stock Exchange within 12 months after listing. The guidance filing process was: signing a guidance agreement with China Merchants Securities on 09-08, submitting filing materials to the Shanghai Securities Regulatory Bureau on 09-09, and acceptance and completion of filing on 09-11. The company has registered capital of RMB 5.093681 million, legal representative Hu Zhenbo, and no controlling shareholder; peer comparable companies are listed as VeriSilicon, ARM, Andes, and SiFive.

Observation: The interpretive value added in this issue lies in refining “high growth, unprofitable” into comparable financial coordinates—gross margin near ninety percent, R&D expense ratio above 100%, share-based payments dominating losses, and losses narrowing after excluding share-based payments. If the Beijing Stock Exchange path is cleared, Nuclei will become the first company in the domestic RISC-V IP first tier to enter the capital markets, and the revenue structure and customer list disclosed in its prospectus can serve as empirical evidence for observing “whether the domestic RISC-V IP licensing business model holds.”

IV. Special Chapter on Embodied Intelligence and Robotics

4.1 SpacemiT spacemit-robotics Advances Across Four Repos: Unified Perception Code Style, Linglong Humanoid Adjusts Support States and Heartbeat Policy

Date: 2026-09-14　Source: spacemit-robotics/perception, spacemit-robotics/humanoid_linglong, spacemit-robotics/control_whole_body, spacemit-robotics/humanoid_common

The SpacemiT robotics software stack (spacemit-robotics) advanced across four repositories on the same day within the window, all submitted by developers beililcj and TrAooooo, presenting a combination of “engineering convergence plus whole-body control refinement.” The perception repository perception merged #5 to unify code style at 17:38, and fixed the repository root path assignment issue in run.sh at 09:54—both laying groundwork for multi-person collaboration and reproducible runs. The humanoid direction continued to be refined: humanoid_linglong (Linglong humanoid) merged #9 at 14:26, adjusting support states and heart policy; the heartbeat policy typically relates to the underlying communication watchdog and safe shutdown, making it a key parameter for whole-machine reliability; control_whole_body (whole-body control) merged #4 at 14:03, fixing and preserving motor chain dependencies, a matter of actuator topology correctness in whole-body control; humanoid_common (humanoid common library) merged #17 at 11:18, refining RL handoff and support state definitions, indicating a clear handoff point between its learning-based controller and the traditional control chain. Taken together, SpacemiT’s RISC-V robotics stack is advancing from “peripheral drivers plus simulation” to the “whole-body control semantics and safety policy” layer, and the same group of developers is working continuously across multiple repositories, indicating a team that remains small and focused.

4.2 The Intersection of Dataflow Architecture and Physical AI: Ruixin Gaoguang D35’s Embodied Intelligence Landing Point

Date: 2026-09-14　Source: See today’s featured item sources

Viewing today’s featured Ruixin Gaoguang D35 from an embodied intelligence perspective, two of the four scenario lines it presents fall directly in the robotics direction: embodied intelligence (integrated “perception plus decision plus control” scenarios such as robots and unmanned vehicle domain controllers) and cockpit-driving integration (fusion of intelligent cockpit and driving domain control). The core of its technical argument is edge-side energy efficiency rather than peak compute—the rationale being that in physical AI scenarios, power supply, volume, and cost constitute hard constraints, and the edge side cannot connect to a data center externally; therefore “how much inference can be completed per watt” replaces “how large the model parameters are” as the deciding factor. The dataflow architecture, by eliminating instruction scheduling overhead, allowing data to flow directly between compute units, and lacking the latency uncertainty introduced by branch prediction and cache misses, is positioned by the company as a route better matched to this kind of deterministic low-latency inference. On the hardware side, the product definition of 128 GB of large VRAM points to the capability claim of “large models deployed locally on the edge, with data never leaving the device,” which directly corresponds to the privacy and real-time requirements of embodied intelligence. Comparative observation: The SpacemiT route continuously tracked by this newsletter over the same period is “RISC-V general-purpose CPU plus self-developed inference backend plus model library” (see 3.3 and 4.1), while Ruixin represents a non-general-purpose route of “RISC-V control core plus dedicated dataflow acceleration array”; the two offer different answers on the combination of RISC-V and embodied intelligence. The former has a low ecosystem barrier and reuses a general software stack; the latter has a high energy-efficiency ceiling but depends on its own SDK and operator library, making ecosystem building significantly more difficult—which is precisely why its “Glory Community” and SDK toolchain能否落地 have become key variables. This report maintains vendor-attributed labeling for its mass production and performance claims (see today’s featured item for details).

V. Summary and Trend Observations

  • A mass-production exemplar of dataflow architecture has emerged in China; the combination of RISC-V and “non-von Neumann” approaches is worth tracking. Suzhou Ruixin’s “Gaoguang D35” has been confirmed for mass production via official Suzhou Industrial Park channels. Positioned for end-side and edge physical AI acceleration, it features 128 GB of VRAM, emphasizes inference throughput per unit power, and plans a developer community oriented toward dataflow architecture. This is the first event of its kind recorded by this publication since September. The key point: if mass production and energy-efficiency claims receive third-party verification, RISC-V in AI acceleration will no longer be limited to the “general-purpose core plus vector/matrix extensions” path, and the history of dataflow approaches remaining stuck in academia may also be rewritten. Current evidence is solely from vendor and official park sources; SDK openness, community launch, and actual shipments must be tracked.

  • Open-source high-performance cores collectively enter the “correctness deep-water zone.” XiangShan’s 8 commits on the day were almost entirely boundary-condition fixes: branch prediction, self-modifying code branch training, PC propagation when exceptions and uncacheable accesses trigger simultaneously, vector register NaN boxing, and more. CORE-V Wally fixed PWM self-test and four consecutive IFU defects in the same window, while CVFPU fixed NaN boxing in division and square root. The advancement focus of both open-source cores has landed on “correctness-verification-driven” work, with the pace of new features giving way to reliability convergence of existing functionality.

  • XiangShan’s memory system evolves toward “CoupledL2 plus independent L3.” XSCache merged a single batch of 18 commits, centered on parameterization of the ZhuJiang (L3 direction) submodule, reset and build fixes, simulation environment adaptation, along with the companion TestTopZhuJiang test top-level and HN performance counters named by module path. This indicates that the L3 cache is moving from development toward a verifiable state, with the accompanying simulation, reset, and performance-collection chains now filled in synchronously.

  • Domestic RISC-V application-level MCUs simultaneously push the upper bound of capability and the lower bound of cost. JetKVM Mini uses an ESP32-P4X dual-core 400 MHz RISC-V with a built-in hardware H.264 encoder to achieve a $39 wired IP-KVM and a $42 wireless version, with firmware open-sourced on day one; the wireless version additionally uses an ESP32-C5 to provide Wi-Fi 6 and Zigbee/Thread. This corroborates this publication’s previous coverage of “ESP32-P4 runs Tomb Raider”: the same chip can both run a 3D game engine and support a commercial out-of-band management device.

  • The window rhythm of domestic teams is dominated by “new-product adaptation and engineering polish.” Sophgo’s sophon-demo uniformly adapts to the new BM1684X2 (SE13-64) hardware target, a signal of software preparation ahead of a new product launch; DAMO XuanTie created an empty cove-dp1-poc repository, pointing toward proof-of-concept for confidential VM extensions; and SpacemiT’s and Sipeed’s commits landed on video stream stability and IP-KVM documentation usability, respectively. On the news side there were no new-product-level releases, and substantive developments remain primarily GitHub commits.

  • The financial model of pure RISC-V IP licensing continues to be tested by reality. Nuclei’s disclosed figures show first-half revenue growth of 41% but a roughly 24.94% widening of net loss attributable to shareholders, with an 87.6% gross margin, R&D expense ratio exceeding 100%, and share-based payment dominating the loss; excluding share-based payment, the loss narrowed period by period. This structure of high gross margin, high R&D, and sustained losses provides a comparable empirical sample for the question of “whether the RISC-V IP licensing business model holds.”

  • Limitations note: This report window is a regular 24 hours (09-14 08:18 to 09-15 08:18). The Google News Chinese channel is severely polluted by gambling-related SEO articles (entries containing the words “sports/login/entry/official site/entertainment/gambling” were culled in bulk this issue; a single query for “XuanTie DAMO” alone hit 8 pieces of invalid noise), and Chinese entries are uniformly based on official channels or mainstream media original sites. The unauthenticated GitHub API has a 60-per-hour rate limit; organization checks used pushed sorting to spot-check recently active repositories, and pushes to non-default branches may be missed: this issue, CVA6 (openhwgroup/cva6) had pushed_at updated to 09-15 07:01 but had no retrievable new commits within the default-branch window, and riscv-software-src/sail-riscv-tests and XUANTIE-RV’s gcc and binutils-gdb repositories fall into the same category, none of which were used to create entries; ESWIN Computing (eswincomputing), Nuclei (Nuclei-Software), and StarFive (starfive-tech) had zero pushes within the window. This issue’s Suzhou Ruixin and Nuclei items are news-side inclusions, of which Ruixin’s mass-production and performance data are entirely from vendor and official park sources with no third-party test corroboration, and have been annotated at each occurrence; Andes Technology’s Silicon Valley event official site original publication date was 09-11 (outside the window), and this issue includes it based on 09-14 Chinese media reprints with a note; the Nuclei coaching filing event was already covered in this publication’s 09-10 to 09-13 issues, and this issue only provides follow-up financial details and reiterates the event’s original date. Overseas media on 09-14 still carried reprints from iNews Zoombangla, Geeky Gadgets, and others of “XuanTie C950 runs Qwen 3.8 without a GPU,” which upon verification is a delayed echo of the 08-18 Day 0 adaptation announcement (already reported in detail in this publication’s 08-19 and 08-20 issues, and also noted as an echo in the 09-08 issue), not a new event, and is not listed as a separate entry this issue. It should also be noted: the 09-14 Chinese media item “Loongson Technology’s LoongArch gains official support from LXC container template sources” concerns the LoongArch architecture and does not fall within the RISC-V scope, so it was not included.

Appendix: Source Verification Table and Complete Source List

Source Verification Table

Source Verification Result
fetch scripts (HN, Google News, CNX/LinuxGizmos/Phoronix/riscv.org RSS, GitHub) Produced 12 candidates within the window, with few valid items; CNX hit JetKVM Mini (included as 2.1), HN hit the Rvvts vector testing framework and a pure-Nix RISC-V emulator (project-level developments, not listed separately), the rest were irrelevant noise such as Vitalik/Ethereum, UPS, and NextSilicon personnel changes, which were excluded
Google News English queries (RISC-V when:2d, XuanTie/SiFive/Andes/StarFive/Milk-V/SpacemiT/SOPHGO/RISC-V Summit when:3d~7d) All six groups — SiFive, StarFive, Milk-V, SpacemiT, SOPHGO, RISC-V Summit — returned zero hits; the Andes group only hit the Chilean Andes volcanoes and Latin American AI events (same-name noise); the XuanTie group hit a late echo of C950 (already reported, excluded); the RISC-V group hit an Infineon Hot Chips item that was an echo already reported on 09-13
Google News Chinese queries (RISC-V when:2d, XuanTie/DAMO, XiangShan open source, Nuclei, ESWIN, Espressif ESP32, RISC-V embodied intelligence, Ruiqing Pai) Valid hits: RISC-V when:2d yielded the official Suzhou Ruixin release and a Jingxin Chinese reprint (included as today’s top story and 2.2 respectively); the Nuclei group yielded a 09-14 financial analysis (included as 3.5); the RISC-V embodied intelligence group yielded the IICIE closing report (the exhibition itself was reported on 09-12, not repeated); all 8 items in the XuanTie group were gambling SEO noise; XiangShan/Espressif/Ruiqing Pai returned zero hits or were all old news outside the window
Suzhou Industrial Park Administrative Committee official website Published “RISC-V Dataflow Physical AI Chip in Mass Production!” on 09-14 14:25, confirming mass production of Ruixin Gaoguang D35, same source as Geek Park (09-09), Sina Finance (09-10), and 36Kr, included as today’s top story
openRuyi official website news and release list The latest official version remains 2026.08 (released 08-27); the 2026-09 release page returns 404, no new version within the window (included as 1.6)
CNX Software / JetKVM official blog and product page Reported JetKVM Mini on 09-14 (ESP32-P4X dual-core RISC-V, from $39, on sale 10-26), firmware open-sourced on day one, included as 2.1
Edge AI and Vision Alliance / Andes event page Published Andes Technology’s 10-07 Silicon Valley custom design event on 09-11, reprinted by Chinese media on 09-14, included as 2.2 with the original date noted
GitHub org pushed verification (12 organizations) Pushes within the window: OpenXiangShan (12 repos), XUANTIE-RV (2), spacemit-com (2), spacemit-robotics (4), sophgo (1), espressif (42, mostly general progress such as ESP-IDF, no release-level developments), sipeed (1), revyos (1, CI runner image), openhwgroup (5), riscv-software-src (1); zero pushes: Nuclei-Software, eswincomputing
GitHub commit-level verification (24 repos) Substantive commits included: XiangShan (8), XSCache (18, batch merges), NEMU (2), GEM5 (1), difftest (1), llvm-project (17, including 2 RISC-V target changes), cvw (6), cvfpu (1), uap (2), core-v-verif (1), mpp (1), sophon-demo (2), sipeed_wiki (4), the four spacemit-robotics repos (1~2 each), damo-rv-priv-ats (1); zero commits (pushed_at updated but no new commits on the default branch): cva6, docs-ros, XiangShan-doc, gsim, sail-riscv-tests; cove-dp1-poc is an empty repo, recorded only as a signal
DAMO XuanTie org repository list Verified the newly created cove-dp1-poc (empty repo) on 09-14 and the priv-ats test plan update, included as 3.1 with the note “directional signal, not a technical conclusion”
Verification of already-reported echoes XuanTie C950 running Qwen (first reported 08-18, already reported in this newsletter on 08-19/20/09-08), Infineon Hot Chips (already reported 09-13), the IICIE exhibition itself (already reported 09-12), Shanghai Jiao Tong University SPMP (approved 08-31, already reported since 09-09), Nuclei IPO counseling (already reported since 09-10) — all treated as echoes, no duplicate entries

Complete Source List